JPH1197851A - Multilayered wiring board - Google Patents

Multilayered wiring board

Info

Publication number
JPH1197851A
JPH1197851A JP25210197A JP25210197A JPH1197851A JP H1197851 A JPH1197851 A JP H1197851A JP 25210197 A JP25210197 A JP 25210197A JP 25210197 A JP25210197 A JP 25210197A JP H1197851 A JPH1197851 A JP H1197851A
Authority
JP
Japan
Prior art keywords
organic resin
substrate
layer
wiring conductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25210197A
Other languages
Japanese (ja)
Inventor
Takeshi Kume
健士 久米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP25210197A priority Critical patent/JPH1197851A/en
Publication of JPH1197851A publication Critical patent/JPH1197851A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring board, in which a propagation speed of an electric signal in a conductive layer provided in a board is increased and a semiconductor device driven at a high-speed can be mounted. SOLUTION: In a multilayered wiring board, in which an organic resin insulation layer 2 and a thin-film wiring conductor layer 3 are alternately laminated in a multilayer on a board 1 having a conductive layer 6 to form a multilayered wiring part 4, and also the conductive layer 6 is electrically connected to the thin-film wiring conductor layer 3, the board 1 is formed in an organic resin by mixing aramid fibers of which the surface is coated with polytetrafluoroethylene.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層配線基板に関
し、より詳細には混成集積回路装置や半導体素子を収容
する半導体素子収納用パッケージ等に使用される多層配
線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.

【0002】[0002]

【従来の技術】従来、混成集積回路装置や半導体素子収
納用パッケージ等に使用される多層配線基板はその配線
導体がMo−Mn法等の厚膜形成技術によって形成され
ている。
2. Description of the Related Art Hitherto, a multilayer wiring board used in a hybrid integrated circuit device, a package for accommodating a semiconductor element, or the like, has its wiring conductor formed by a thick film forming technique such as the Mo-Mn method.

【0003】このMo−Mn法は通常、タングステン、
モリブデン、マンガン等の高融点金属粉末に有機溶剤、
溶媒を添加混合し、ペースト状となした金属ペーストを
生セラミック体の外表面にスクリーン印刷法により所定
パターンに印刷塗布し、次にこれを複数枚積層するとと
もに還元雰囲気中で焼成し、高融点金属粉末と生セラミ
ック体とを焼結一体化させる方法である。
[0003] This Mo-Mn method is generally used for tungsten,
Organic solvents for high melting point metal powders such as molybdenum and manganese,
A solvent is added and mixed, and a paste-shaped metal paste is printed and applied on the outer surface of the green ceramic body in a predetermined pattern by a screen printing method. Then, a plurality of these are laminated and fired in a reducing atmosphere to obtain a high melting point. This is a method of sintering and integrating a metal powder and a green ceramic body.

【0004】なお、前記配線導体が形成されるセラミッ
ク体としては、通常、酸化アルミニウム質焼結体やムラ
イト質焼結体等の酸化物系セラミックス、或いは表面に
酸化物膜を被着させた窒化アルミニウム質焼結体や炭化
珪素質焼結体等の非酸化物系セラミックスが使用されて
いる。
The ceramic body on which the wiring conductor is formed is usually an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a nitride having an oxide film deposited on the surface. Non-oxide ceramics such as aluminum sintered bodies and silicon carbide sintered bodies are used.

【0005】しかしながら、このMo−Mn法を用いて
配線導体を形成した場合、配線導体は金属ペーストをス
クリーン印刷することにより形成されることから微細化
が困難で配線導体を高密度に形成することができないと
いう欠点を有していた。
However, when the wiring conductor is formed by using the Mo-Mn method, the wiring conductor is formed by screen-printing a metal paste. Had the drawback that it could not be done.

【0006】そこで上記欠点を解消するために配線導体
の一部を従来の厚膜形成技術に変えて微細化が可能な薄
膜形成技術を用いて高密度に形成した多層配線基板が採
用されるようになってきた。
In order to solve the above-mentioned drawbacks, a multilayer wiring board in which a part of the wiring conductor is formed at a high density by using a thin film forming technique which can be miniaturized instead of the conventional thick film forming technique is adopted. It has become

【0007】かかる多層配線基板は、上下両面に貫通す
る貫通孔を形成した酸化アルミニウム質焼結体等から成
るセラミックスやガラス繊維を織り込んだ布にエポキシ
樹脂を含浸させて形成されるガラスエポキシ樹脂等から
成る絶縁基板と、該絶縁基板の上面から貫通孔内壁を経
て下面に導出する銅等の金属材料から成る導電層と、前
記絶縁基板の少なくとも一主面に被着され、エポキシ樹
脂等から成る有機樹脂絶縁層と、銅やアルミニウム等の
金属から成る薄膜配線導体層とを交互に多層に積層させ
るとともに薄膜配線導体層の一部を前記導電層に有機樹
脂絶縁層に設けたスルーホールの内壁面に被着されてい
るスルーホール導体を介して接続した多層配線部とから
構成されており、導電層を介して多層配線部の薄膜配線
導体層を外部電気回路に接続したり、絶縁基板の上下両
面に被着される多層配線部の薄膜配線導体層同士を電気
的に接続するようになっている。
[0007] Such a multilayer wiring board is formed by impregnating a ceramic or glass fiber woven cloth made of aluminum oxide sintered body or the like having through holes penetrating on both upper and lower surfaces with a glass epoxy resin formed by impregnating the cloth with an epoxy resin. And a conductive layer made of a metal material such as copper derived from the upper surface of the insulating substrate to the lower surface through the inner wall of the through-hole, and an epoxy resin or the like adhered to at least one main surface of the insulating substrate. An organic resin insulating layer and a thin film wiring conductor layer made of a metal such as copper or aluminum are alternately laminated in multiple layers, and a part of the thin film wiring conductor layer is formed in a through hole provided in the organic resin insulating layer in the conductive layer. And a multi-layer wiring portion connected through a through-hole conductor attached to the wall surface. Or connect to the road, so as to electrically connect the thin film wiring conductor layers to each other in the multilayer wiring portion is deposited on the upper and lower surfaces of the insulating substrate.

【0008】なお、前記多層配線基板は、貫通孔を有す
る絶縁基板の上面、貫通孔内壁及び下面に無電解めっき
法等により銅を被着させ、これをフォトリソグラフィー
技術により所定パターンに加工して絶縁基板の上面から
貫通孔内壁を経て下面に導出する導電層を被着させ、次
に前記絶縁基板の上面及び/又は下面にスピンコート法
及び熱硬化処理等によって形成されるエポキシ樹脂等の
有機樹脂から成る絶縁層と銅やアルミニウム等の金属を
無電解めっき法等の薄膜形成技術及びフォトリソグラフ
ィー技術を採用することによって成形される薄膜配線導
体層とを交互に多層に積層し多層配線部を形成すること
によって製作されている。
In the multilayer wiring board, copper is applied to the upper surface, the inner wall and the lower surface of the through hole by an electroless plating method or the like, and is processed into a predetermined pattern by a photolithography technique. A conductive layer extending from the upper surface of the insulating substrate to the lower surface via the inner wall of the through hole is applied, and then an organic resin such as an epoxy resin formed on the upper and / or lower surface of the insulating substrate by a spin coating method, a thermosetting treatment or the like. An insulating layer made of resin and a thin film wiring conductor layer formed by adopting a thin film forming technology such as electroless plating and a photolithography technology on a metal such as copper or aluminum are alternately laminated in multiple layers to form a multilayer wiring portion. It is manufactured by forming.

【0009】また前記絶縁基板に形成した導電層と薄膜
配線導体層とは有機樹脂絶縁層に設けたスルーホールの
内壁面に被着されているスルーホール導体を介して電気
的に接続されており、有機樹脂絶縁層に形成されている
スルーホールは有機樹脂絶縁層上にレジスト材を塗布す
るとともにこれを露光、現像を施すことによって所定位
置に所定形状の窓部を形成し、次に前記レジスト材の窓
部にエッチング液を配し、レジスト材の窓部に位置する
有機樹脂絶縁層を除去して、有機樹脂絶縁層に穴(スル
ーホール)を形成し、最後に前記レジスト材を有機樹脂
絶縁層より剥離させ除去することによって形成され、ま
たスルーホールの内壁面に被着されるスルーホール導体
はスルーホールの内壁面に例えば、銅等を無電解めっき
法により被着させることによって形成される。
The conductive layer and the thin-film wiring conductor layer formed on the insulating substrate are electrically connected to each other via a through-hole conductor attached to the inner wall surface of the through-hole provided in the organic resin insulating layer. The through holes formed in the organic resin insulating layer are formed by applying a resist material on the organic resin insulating layer and exposing and developing the resist material to form a window having a predetermined shape at a predetermined position. An etchant is placed in the window of the material, the organic resin insulating layer located in the window of the resist material is removed, a hole (through hole) is formed in the organic resin insulating layer, and finally, the resist material is coated with an organic resin. The through-hole conductor, which is formed by peeling and removing the insulating layer from the insulating layer and adhered to the inner wall surface of the through hole, is formed by, for example, applying copper or the like to the inner wall surface of the through hole by electroless plating. It is formed by.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、この多
層配線基板においては、基板を構成する酸化アルミニウ
ム質焼結体やガラスエポキシ樹脂の比誘電率が約5以上
(室温、1MHz)と高いため基板に形成された導電層
を伝達する電気信号に遅延が生じ、電気信号を高速で伝
達させる必要のある高速駆動の半導体素子はその実装が
不可能になる欠点を有していた。
However, in this multilayer wiring board, the relative permittivity of the aluminum oxide sintered body or the glass epoxy resin constituting the board is as high as about 5 or more (room temperature, 1 MHz). A delay occurs in an electric signal transmitted through the formed conductive layer, and a high-speed driven semiconductor element that needs to transmit the electric signal at a high speed has a disadvantage that it cannot be mounted.

【0011】本発明は上記欠点に鑑み案出されたもの
で、その目的は基板に設た導電層における電気信号の伝
搬速度を速いものとし、高速駆動を行う半導体素子を実
装することが可能な多層配線基板を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks. It is an object of the present invention to increase the propagation speed of an electric signal in a conductive layer provided on a substrate and to mount a semiconductor element for high-speed driving. It is to provide a multilayer wiring board.

【0012】[0012]

【課題を解決するための手段】本発明は、導電層を有す
る基板上に、有機樹脂絶縁層と薄膜配線導体層とを交互
に多層に積層して成る多層配線部を設けるとともに前記
導電層と薄膜配線導体層とを電気的に接続して成る多層
配線基板であって、前記基板は有機樹脂中に、表面がポ
リテトラフルオロエチレンで被覆されたアラミド繊維を
含浸させて形成されていることを特徴とするものであ
る。
According to the present invention, there is provided a multilayer wiring portion comprising an organic resin insulating layer and a thin film wiring conductor layer alternately laminated on a substrate having a conductive layer. A multilayer wiring board formed by electrically connecting a thin-film wiring conductor layer, wherein the substrate is formed by impregnating an organic resin with aramid fibers having a surface coated with polytetrafluoroethylene. It is a feature.

【0013】また本発明は、前記有機樹脂中におけるア
ラミド繊維の含浸率が10乃至60重量%であることを
特徴とするのである。
Further, the present invention is characterized in that the impregnation rate of the aramid fiber in the organic resin is 10 to 60% by weight.

【0014】本発明の多層配線基板によれば、基板を有
機樹脂中に、表面がポリテトラフルオロエチレンで被覆
されたアラミド繊維を10乃至60重量%含浸させて形
成したことから比誘電率が4(室温、1MHz)以下と
小さな値となり、これによって基板に形成されている導
電層を伝達する電気信号の伝搬速度を高速となすことが
出来、電気信号を高速で伝達させる必要のある高速駆動
の半導体素子等の実装が可能となる。
According to the multilayer wiring board of the present invention, the substrate is formed by impregnating an organic resin with an aramid fiber whose surface is coated with polytetrafluoroethylene in an amount of 10 to 60% by weight. (Room temperature, 1 MHz) or less, which makes it possible to increase the propagation speed of the electric signal transmitted through the conductive layer formed on the substrate, and to perform high-speed driving in which the electric signal needs to be transmitted at a high speed. Mounting of a semiconductor element or the like becomes possible.

【0015】[0015]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1は、本発明の多層配線基板の一実
施例を示し、1は基板、2は有機樹脂絶縁層、3は薄膜
配線導体層である。
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is a substrate, 2 is an organic resin insulating layer, and 3 is a thin-film wiring conductor layer.

【0016】前記基板1はその上面に有機樹脂絶縁層2
と薄膜配線導体層3とから成る多層配線部4が配設され
ており、該多層配線部4を支持する支持部材として作用
する。
The substrate 1 has an organic resin insulating layer 2 on its upper surface.
And a thin-film wiring conductor layer 3, and a multilayer wiring portion 4 is provided, and functions as a support member for supporting the multilayer wiring portion 4.

【0017】前記基板1は、例えば、エポキシ樹脂等か
ら成る有機樹脂中に、表面がポリテトラフルオロエチレ
ンで被覆されたアラミド繊維を含浸させたアラミド基板
等の電気絶縁基板を複数枚積層するとともにその各々を
一体的に接合させて形成されており、具体的にはエポキ
シ樹脂前駆体中にアラミド繊維を含浸させるとともにこ
れを80〜150℃の熱で1〜90分間熱処理を行いエ
ポキシ樹脂前駆体をBステージに硬化させて複数枚の電
気絶縁基板を得、しかる後、この電気絶縁基板を上下に
積層するとともに80〜200℃の熱で30〜180分
間熱処理を行いエポキシ樹脂前駆体を完全に熱硬化させ
ることによって作製される。
The substrate 1 is formed by laminating a plurality of electrically insulating substrates such as an aramid substrate in which an aramid fiber whose surface is coated with polytetrafluoroethylene is impregnated in an organic resin such as an epoxy resin. Each is formed by integrally joining, specifically, an epoxy resin precursor is impregnated with aramid fiber and heat-treated at 80 to 150 ° C. for 1 to 90 minutes to form an epoxy resin precursor. After curing to a B stage, a plurality of electric insulating substrates are obtained. Thereafter, the electric insulating substrates are stacked one on top of the other and heat-treated at 80 to 200 ° C. for 30 to 180 minutes to completely heat the epoxy resin precursor. It is made by curing.

【0018】また前記基板1には上下面に貫通する孔径
が例えば、直径0.3mm〜0.5mmの貫通孔5が基
板1にドリル孔あけ加工法等を施すことによって形成さ
れており、かつ基板1の内部、上下面及び貫通孔5の内
壁には銅やアルミニウム、銀、ニッケル等の金属材料か
ら成る導電層6が被着形成されている。
A through hole 5 having a diameter of, for example, 0.3 mm to 0.5 mm penetrating the upper and lower surfaces of the substrate 1 is formed by subjecting the substrate 1 to a drilling method or the like, and A conductive layer 6 made of a metal material such as copper, aluminum, silver, or nickel is formed on the inside, upper and lower surfaces of the substrate 1 and the inner wall of the through hole 5.

【0019】前記基板1の内部、上下面及び貫通孔5の
内壁に形成されている導電層6は後述する基板1の上面
に形成される多層配線部4の薄膜配線導体層3と外部電
気回路とを電気的に接続する、或いは多層配線部4の薄
膜配線導体層3同士を電気的に接続する、または基板1
の上下両面に多層配線部4を配設した場合には両面の多
層配線部4の薄膜配線導体層同士を電気的に接続する作
用をなし、基板1の内部及び上下両面に形成されている
導電層6は基板1を形成する各アラミド基板の上下面に
銅やアルミニウム、銀、ニッケル、鉄等の金属材料から
成る金属材料箔を被着させておき、これをエッチング加
工技術を用いて所定パターンに加工することによって形
成され、また基板1の貫通孔5の内壁に形成されている
導電層6は貫通孔5の内壁に従来周知のめっき法を採用
することによって銅やニッケル、鉄等の金属材料を被着
させ、しかる後、これを所定パターンに加工することに
よって形成される。
The conductive layer 6 formed on the inside, the upper and lower surfaces of the substrate 1 and the inner wall of the through hole 5 is connected to a thin-film wiring conductor layer 3 of a multilayer wiring portion 4 formed on the upper surface of the substrate 1 and an external electric circuit. Or the thin film wiring conductor layers 3 of the multilayer wiring portion 4 are electrically connected to each other, or the substrate 1
When the multilayer wiring portions 4 are provided on both upper and lower surfaces of the substrate 1, the thin film wiring conductor layers of the multilayer wiring portions 4 on both surfaces are electrically connected to each other, and the conductive layers formed inside the substrate 1 and on both upper and lower surfaces are formed. The layer 6 has a metal material foil made of a metal material such as copper, aluminum, silver, nickel, iron or the like adhered to the upper and lower surfaces of each aramid substrate forming the substrate 1, and this is patterned into a predetermined pattern using an etching technique. The conductive layer 6 formed on the inner wall of the through hole 5 of the substrate 1 is made of a metal such as copper, nickel, iron, or the like by employing a conventionally known plating method on the inner wall of the through hole 5. It is formed by depositing a material and then processing it into a predetermined pattern.

【0020】前記内部、上下両面及び貫通孔5の内壁に
導電層6を有する基板1はエポキシ樹脂等の有機樹脂中
に表面がポリテトラフルオロエチレンで被覆されたアラ
ミド繊維を含浸させて形成されるアラミド基板を複数
枚、上下に積層一体化して構成されており、その比誘電
率が4(室温、1MHz)以下と小さいため導電層6を
伝達する電気信号の伝搬速度を速いものとなすことがで
き、その結果、電気信号を高速で伝達させる高速駆動の
半導体素子等の実装が可能となる。
The substrate 1 having the conductive layer 6 on the inside, the upper and lower surfaces, and the inner wall of the through hole 5 is formed by impregnating an organic resin such as an epoxy resin with an aramid fiber whose surface is coated with polytetrafluoroethylene. A plurality of aramid substrates are vertically stacked and integrated, and their relative dielectric constant is as small as 4 (room temperature, 1 MHz) or less, so that the propagation speed of electric signals transmitted through the conductive layer 6 can be increased. As a result, it becomes possible to mount a high-speed driven semiconductor element or the like that transmits electric signals at high speed.

【0021】なお、前記基板1はエポキシ樹脂等の有機
樹脂中に含浸されるアラミド繊維の含浸率が10重量%
未満であると基板1の比誘電率を小さく下げることがで
きず、また60重量%を超えるとアラミド繊維と有機樹
脂との間に空隙が生じ、基板1の内部に配する導電層6
間の電気的絶縁の信頼性が低下してしまう傾向にある。
従って、前記基板1は該基板1の内部に配される導電層
6の電気的絶縁を維持し、かつ比誘電率を小さくするた
めにエポキシ樹脂等の有機樹脂中に含浸されるアラミド
繊維の含浸率を10〜60重量%の範囲としておくこと
が好ましい。
The substrate 1 has an aramid fiber impregnated in an organic resin such as an epoxy resin having an impregnation rate of 10% by weight.
If it is less than 60%, the relative permittivity of the substrate 1 cannot be reduced, and if it exceeds 60% by weight, a gap is formed between the aramid fiber and the organic resin, and the conductive layer 6 disposed inside the substrate 1
There is a tendency for the reliability of electrical insulation between the two to decrease.
Accordingly, the substrate 1 is provided with an aramid fiber impregnated in an organic resin such as an epoxy resin in order to maintain the electrical insulation of the conductive layer 6 disposed inside the substrate 1 and reduce the relative dielectric constant. It is preferable that the ratio be in the range of 10 to 60% by weight.

【0022】また、前記有機樹脂中に含浸されるアラミ
ド繊維は浸水性官能基(エステル化合物)を多数有して
いるため、水分が多量に付着し易く、アラミド繊維に水
分が多量に付着すると導電層6間に電気的短絡が発生し
てしまう。そのため前記有機樹脂中に含浸されるアラミ
ド繊維はその表面をポリテトラフルオロエチレンで被覆
し、アラミド繊維に水分が多量に付着するのを有効に防
止しておく必要がある。
Further, the aramid fiber impregnated in the organic resin has a large number of water-permeable functional groups (ester compounds), so that a large amount of water easily adheres thereto. An electric short circuit occurs between the layers 6. Therefore, it is necessary to coat the surface of the aramid fiber impregnated in the organic resin with polytetrafluoroethylene to effectively prevent a large amount of water from adhering to the aramid fiber.

【0023】前記アラミド繊維の表面をポリテトラフル
オロエチレンで被覆する方法としては、例えば、石油系
ナフサ等にポリテトラフルオロエチレンの粉末を分散さ
せて懸濁液を作成し、この懸濁液にアラミド繊維を浸漬
させ、しかる後、約100〜200℃の温度で熱処理
し、石油系ナフサ等を飛散させることによって行われ
る。
As a method of coating the surface of the aramid fiber with polytetrafluoroethylene, for example, a suspension is prepared by dispersing a polytetrafluoroethylene powder in petroleum naphtha or the like, and the suspension is formed with aramid. This is carried out by immersing the fiber, followed by a heat treatment at a temperature of about 100 to 200 ° C. to scatter petroleum naphtha and the like.

【0024】更に、前記基板1はそれを構成する各アラ
ミド基板の厚みが20μm未満であると基板1の内部に
配される導電層6間の電気絶的縁の信頼性が低下する傾
向にあり、また200μmを超えると基板1の内部に配
される導電層6をアラミド基板に形成するスルーホール
の内部に充填されたスルーホール導体を介して電気的に
接続する際、スルーホールをレーザー加工等によって所
定寸法、所定形状に形成することが困難となる傾向にあ
る。従って、前記基板1を構成する各アラミド基板はそ
の厚みを20〜200μmの範囲としておくことが好ま
しい。
Further, when the thickness of each aramid substrate constituting the substrate 1 is less than 20 μm, the reliability of the electrical connection between the conductive layers 6 disposed inside the substrate 1 tends to decrease. When the thickness exceeds 200 μm, when the conductive layer 6 disposed inside the substrate 1 is electrically connected via a through-hole conductor filled in the through-hole formed in the aramid substrate, the through-hole is formed by laser processing or the like. Therefore, it tends to be difficult to form a predetermined size and a predetermined shape. Therefore, it is preferable that each aramid substrate constituting the substrate 1 has a thickness in a range of 20 to 200 μm.

【0025】また更に、前記内部、上下両面及び貫通孔
5の内壁に導電層6が形成されている基板1は貫通孔5
の内部にエポキシ樹脂等からなる有機樹脂充填体8が充
填されており、該有機樹脂充填体8によって貫通孔5が
完全に埋められ、同時に有機樹脂充填体8の両端面が基
板1の上下両面に形成した導電層6の面と同一平面とな
っている。
Further, the substrate 1 in which the conductive layer 6 is formed on the inside, the upper and lower surfaces, and the inner wall of the through hole 5 is provided with the through hole 5.
Is filled with an organic resin filler 8 made of epoxy resin or the like, and the through hole 5 is completely filled with the organic resin filler 8. And the same plane as the surface of the conductive layer 6 formed on the substrate.

【0026】前記有機樹脂充填体8は基板1の上面及び
/又は下面に後述する有機樹脂絶縁層2と薄膜配線導体
層3とからなる多層配線部4を形成する際、多層配線部
4の有機樹脂絶縁層2と薄膜配線導体層3の平坦化を維
持する作用をなし、基板1の貫通孔5内にエポキシ樹脂
等の前駆体を充填し、しかる後、これに80〜200℃
の温度を0.5〜3時間印加し、完全に熱硬化させるこ
とによって基板1の貫通孔5内に充填される。
The organic resin filler 8 is used when forming a multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin film wiring conductor layer 3 on the upper surface and / or lower surface of the substrate 1. It serves to maintain the flatness of the resin insulating layer 2 and the thin-film wiring conductor layer 3, and fills the through-hole 5 of the substrate 1 with a precursor such as an epoxy resin.
Is applied for 0.5 to 3 hours to completely fill the inside of the through-hole 5 of the substrate 1 by thermosetting.

【0027】前記基板1は更にその上面に有機樹脂絶縁
層2と薄膜配線導体層3とが交互に多層に積層された多
層配線部4が形成されており、且つ薄膜配線導体層3の
一部は導電層6と電気的に接続されている。
On the upper surface of the substrate 1, a multilayer wiring portion 4 in which an organic resin insulating layer 2 and a thin film wiring conductor layer 3 are alternately laminated in a multilayer is formed, and a part of the thin film wiring conductor layer 3 is formed. Is electrically connected to the conductive layer 6.

【0028】前記多層配線部4を構成する有機樹脂絶縁
層2は上下に位置する薄膜配線導体層3の電気的絶縁を
図る作用をなし、薄膜配線導体層3は電気信号を伝達す
るための伝達路として作用する。
The organic resin insulating layer 2 constituting the multilayer wiring section 4 functions to electrically insulate the thin film wiring conductor layers 3 located above and below, and the thin film wiring conductor layer 3 is used for transmitting electric signals. Acts as a road.

【0029】前記多層配線部4の有機樹脂絶縁層2はエ
ポキシ樹脂、ビスマレイミドトリアジン樹脂、ポリフェ
ニレンエーテル樹脂、フッ素樹脂等の有機樹脂から成
り、例えば、エポキシ樹脂からなる場合、ビスフェノー
ルA型エポキシ樹脂、ノボラック型エポキシ樹脂、グリ
シジルエステル型エポキシ樹脂等にアミン系硬化剤、イ
ミダゾール系硬化剤、酸無水物系硬化剤等の硬化剤を添
加混合してペースト状のエポキシ樹脂前駆体を得るとと
もに該エポキシ樹脂前駆体を基板1の上部にスピンコー
ト法により被着させ、しかる後、これを約80℃〜20
0℃の熱で0.5乃至3時間処理し、熱硬化させること
によって形成される。
The organic resin insulating layer 2 of the multilayer wiring section 4 is made of an organic resin such as an epoxy resin, a bismaleimide triazine resin, a polyphenylene ether resin, a fluororesin, and the like. A novolak type epoxy resin, a glycidyl ester type epoxy resin, and the like are mixed with a curing agent such as an amine-based curing agent, an imidazole-based curing agent, and an acid anhydride-based curing agent to obtain a paste-like epoxy resin precursor, and the epoxy resin is obtained. The precursor is applied to the upper portion of the substrate 1 by spin coating, and then the precursor is applied at about 80 ° C. to 20 ° C.
It is formed by treating with heat of 0 ° C. for 0.5 to 3 hours and heat curing.

【0030】また前記有機樹脂絶縁層2はその各々の所
定位置に最小径が有機樹脂絶縁層2の厚みに対して約
1.5倍程度のスルーホール9が形成されており、該ス
ルーホール9は後述する有機樹脂絶縁層2を挟んで上下
に位置する薄膜配線導体層3の各々を電気的に接続する
スルーホール導体10を形成するための形成孔として作
用する。
The organic resin insulating layer 2 has a through hole 9 having a minimum diameter of about 1.5 times the thickness of the organic resin insulating layer 2 at each predetermined position. Serves as a forming hole for forming a through-hole conductor 10 that electrically connects each of the thin film wiring conductor layers 3 located above and below the organic resin insulating layer 2 described later.

【0031】前記有機樹脂絶縁層2に設けるスルーホー
ル9は例えば、フォトリソグラフィー技術、具体的には
有機樹脂絶縁層2上にレジスト材を塗布するとともにこ
れに露光、現像を施すことによって所定位置に所定形状
の窓部を形成し、次に前記レジスト材の窓部にエッチン
グ液を配し、レジスト材の窓部に位置する有機樹脂絶縁
層2を除去して、有機樹脂絶縁層2に穴(スルーホー
ル)を形成し、最後に前記レジスト材を有機樹脂絶縁層
2上より剥離させ除去することによって行われる。
The through holes 9 provided in the organic resin insulating layer 2 are formed at predetermined positions by, for example, a photolithography technique, specifically, applying a resist material onto the organic resin insulating layer 2 and exposing and developing the resist material. A window having a predetermined shape is formed, and then an etchant is disposed on the window of the resist material, the organic resin insulating layer 2 located on the window of the resist material is removed, and a hole ( A through hole is formed, and finally, the resist material is peeled off from the organic resin insulating layer 2 and removed.

【0032】更に前記各有機樹脂絶縁層2の上面には所
定パターンの薄膜配線導体層3が、また各有機樹脂絶縁
層2に設けたスルーホール9の内壁にはスルーホール導
体10が各々配設されており、スルーホール導体10に
よって間に有機樹脂絶縁層2を挟んで上下に位置する各
薄膜配線導体層3の各々が電気的に接続されるようにな
っている。
Further, a thin-film wiring conductor layer 3 having a predetermined pattern is provided on the upper surface of each organic resin insulating layer 2, and a through-hole conductor 10 is provided on the inner wall of a through hole 9 provided in each organic resin insulating layer 2. Each of the thin-film wiring conductor layers 3 positioned above and below the organic resin insulating layer 2 with the through-hole conductor 10 therebetween is electrically connected.

【0033】前記有機樹脂絶縁層2の上面及びスルーホ
ール9内に配設される薄膜配線導体層3及びスルーホー
ル導体10は銅、ニッケル、金、アルミニウム等の金属
材料を無電解めっき法や蒸着法、スパッタリング法等の
薄膜形成技術及びエッチング加工技術を採用することに
よって形成され、例えば銅で形成されている場合には、
有機樹脂絶縁層2の上面及びスルーホール9の内壁面に
硫酸銅0.06モル/リットル、ホルマリン0.3モル
/リットル、水酸化ナトリウム0.35モル/リット
ル、エチレンジアミン四酢酸0.35モル/リットルか
らなる無電解銅めっき浴を用いて厚さ1μm乃至40μ
mの銅層を被着させ、しかる後、前記銅層をエッチング
加工技術により所定パターンに加工することによって各
有機樹脂絶縁層2間及び各有機樹脂絶縁層2のスルーホ
ール9内壁に配設される。この場合、薄膜配線導体層3
は薄膜形成技術により形成されることから配線の微細化
が可能であり、これによって薄膜配線導体層3を極めて
高密度に形成することが可能になる。また同時に薄膜配
線導体層3は有機樹脂絶縁層2がエポキシ樹脂、ビスマ
レイミドトリアジン樹脂、ポリフェニレンエーテル樹
脂、フッ素樹脂等の有機樹脂で形成されており、その比
誘電率が4(室温、1MHz)以下と小さいことから電
気信号の伝搬速度を極めて速いものとなすことができ、
これによっても電気信号を高速で伝達させる必要のある
高速駆動の半導体素子等の実装が可能となる。
The thin-film wiring conductor layer 3 and the through-hole conductor 10 provided on the upper surface of the organic resin insulating layer 2 and in the through-hole 9 are made of a metal material such as copper, nickel, gold, or aluminum by electroless plating or vapor deposition. Method, is formed by employing a thin film forming technology such as a sputtering method and an etching technology, for example, when formed of copper,
0.06 mol / l of copper sulfate, 0.3 mol / l of formalin, 0.35 mol / l of sodium hydroxide, 0.35 mol / l of ethylenediaminetetraacetic acid are formed on the upper surface of the organic resin insulating layer 2 and the inner wall surface of the through hole 9. 1 µm to 40 µm using a 1 liter electroless copper plating bath
m, and then the copper layer is processed into a predetermined pattern by an etching technique to be disposed between the organic resin insulating layers 2 and on the inner walls of the through holes 9 of the organic resin insulating layers 2. You. In this case, the thin film wiring conductor layer 3
Since is formed by a thin film forming technique, the wiring can be miniaturized, and thereby the thin film wiring conductor layer 3 can be formed at an extremely high density. At the same time, in the thin film wiring conductor layer 3, the organic resin insulating layer 2 is formed of an organic resin such as an epoxy resin, a bismaleimide triazine resin, a polyphenylene ether resin, and a fluororesin, and has a relative dielectric constant of 4 (room temperature, 1 MHz) or less. And the propagation speed of the electric signal can be extremely high,
This also makes it possible to mount a high-speed driven semiconductor element or the like that needs to transmit electric signals at high speed.

【0034】なお、前記有機樹脂絶縁層2と薄膜配線導
体層3とを交互に多層に積層して形成される多層配線部
4は各有機樹脂絶縁層2の上面を中心線平均粗さ(R
a)で0.05μm≦Ra≦5μmの粗面としておく
と、有機樹脂絶縁層2と薄膜配線導体層3との接合及び
上下に位置する有機樹脂絶縁層2同士の接合を強固とな
すことができる。従って、前記多層配線部4の角有機樹
脂絶縁層2はその上面をエッチング加工技術等を採用す
ることによって粗し、中心線平均粗さ(Ra)で0.0
5μm≦Ra≦5μmの粗面としておくことが好まし
い。
The multilayer wiring section 4 formed by alternately laminating the organic resin insulating layers 2 and the thin film wiring conductor layers 3 in a multilayer manner has a center line average roughness (R
If a rough surface of 0.05 μm ≦ Ra ≦ 5 μm is set in a), the bonding between the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and the bonding between the organic resin insulating layers 2 located above and below can be made strong. it can. Accordingly, the corner organic resin insulating layer 2 of the multilayer wiring portion 4 is roughened on its upper surface by employing an etching technique or the like, and has a center line average roughness (Ra) of 0.0.
It is preferable to provide a rough surface of 5 μm ≦ Ra ≦ 5 μm.

【0035】また前記有機樹脂絶縁層2はその表面の
2.5mmの長さにおける凹凸の高さ(Pc)のカウン
ト値を、1μm≦Pc≦10μmが500個以上、0.
1μm≦Pc≦1μmが2500個以上、0.01μm
≦Pc≦0.1μmが12500個以上としておくと有
機樹脂絶縁層2と薄膜配線導体層3との接合及び上下に
位置する有機樹脂絶縁層2同士の接合がより強固とな
る。従って、前記有機樹脂絶縁層2はその表面の2.5
mmの長さにおける凹凸の高さ(Pc)のカウント値
を、1μm≦Pc≦10μmが500個以上、0.1μ
m≦Pc≦1μmが2500個以上、0.01μm≦P
c≦0.1μmが12500個以上としておくことが好
ましい。
The count value of the height (Pc) of the unevenness at a length of 2.5 mm on the surface of the organic resin insulating layer 2 is 500 when 1 μm ≦ Pc ≦ 10 μm.
2500 μm of 1 μm ≦ Pc ≦ 1 μm, 0.01 μm
If ≦ Pc ≦ 0.1 μm is set to 12,500 or more, the bonding between the organic resin insulating layer 2 and the thin-film wiring conductor layer 3 and the bonding between the organic resin insulating layers 2 located above and below become stronger. Therefore, the organic resin insulating layer 2 has a thickness of 2.5
The count value of the height (Pc) of the unevenness in the length of mm is 1 μm ≦ Pc ≦ 10 μm.
2500 or more m ≦ Pc ≦ 1 μm, 0.01 μm ≦ P
It is preferable that c ≦ 0.1 μm is set to 12,500 or more.

【0036】前記有機樹脂絶縁層2上面の中心線平均粗
さ(Ra)及び2.5mmの長さにおける凹凸の高さ
(Pc)のカウント値は、有機樹脂絶縁層2の表面を原
子間力顕微鏡(Digital Instruments Inc.製のDimensio
n 3000-Nano Scope III )で50μm角の対角(70μ
m)に走査させてその表面状態を検査測定し、その測定
結果より各々の数値を算出した。
The count value of the center line average roughness (Ra) of the upper surface of the organic resin insulating layer 2 and the height of the unevenness (Pc) at a length of 2.5 mm are obtained by measuring the surface of the organic resin insulating layer 2 with an atomic force. Microscope (Dimensio manufactured by Digital Instruments Inc.
n 3000-Nano Scope III) 50μm diagonal (70μm)
m), the surface condition was inspected and measured, and each numerical value was calculated from the measurement result.

【0037】また前記中心線平均粗さ(Ra)が0.0
5μm≦Ra≦5μm、2.5mmの長さにおける凹凸
の高さ(Pc)のカウント値を、1μm≦Pc≦10μ
mが500個以上、0.1μm≦Pc≦1μmが250
0個以上、0.01μm≦Pc≦0.1μmが1250
0個以上の有機樹脂絶縁層2は、該有機樹脂絶縁層2の
上面にCHF3 、CF4 、Ar等のガスを吹き付けリア
クティブイオンエッチング処理することによって表面が
所定の粗さに粗らされる。
The center line average roughness (Ra) is 0.0
5 μm ≦ Ra ≦ 5 μm, the count value of the height (Pc) of the unevenness at a length of 2.5 mm is 1 μm ≦ Pc ≦ 10 μm
m is 500 or more, and 0.1 μm ≦ Pc ≦ 1 μm is 250
0 or more, 0.01 μm ≦ Pc ≦ 0.1 μm is 1250
The surface of the zero or more organic resin insulating layers 2 is roughened to a predetermined roughness by performing reactive ion etching by spraying a gas such as CHF 3 , CF 4 , or Ar on the upper surface of the organic resin insulating layers 2. You.

【0038】更に前記有機樹脂絶縁層2はその各々の厚
みが100μmを超えると有機樹脂絶縁層2にフォトリ
ソグラフィー技術を採用することによってスルーホール
9を形成する際、エッチングの加工時間が長くなってス
ルーホール9を所望する鮮明な形状に形成するのが困難
となり、また5μm未満となると有機樹脂絶縁層2の上
面に上下に位置する有機樹脂絶縁層2の接合強度を上げ
るための粗面加工を施す際、有機樹脂絶縁層2に不要な
穴が形成され上下に位置する薄膜配線導体層3に不要な
電気的短絡を招来してしまう危険性がある。従って、前
記有機樹脂絶縁層2はその各々の厚みを5μm乃至10
0μmの範囲としておくことが好ましい。
Further, when the thickness of each of the organic resin insulating layers 2 exceeds 100 μm, the processing time of etching becomes long when the through holes 9 are formed by employing photolithography technology in the organic resin insulating layers 2. It is difficult to form the through hole 9 into a desired clear shape, and if the thickness is less than 5 μm, rough surface processing for increasing the bonding strength of the organic resin insulating layer 2 positioned above and below the organic resin insulating layer 2 is performed. At the time of application, there is a risk that an unnecessary hole is formed in the organic resin insulating layer 2 and an unnecessary electric short circuit is caused in the thin film wiring conductor layer 3 located above and below. Accordingly, the organic resin insulating layer 2 has a thickness of 5 μm to 10 μm.
It is preferable to set the range to 0 μm.

【0039】また更に前記多層配線部4の各薄膜配線導
体層3はその厚みが3μm未満であると薄膜配線導体層
3の電気抵抗値が大きなものとなって各薄膜配線導体層
3に所定の電気信号を伝達させることが困難となり、ま
た40μmを超えると薄膜配線導体層3を有機樹脂絶縁
層2に被着させる際に薄膜配線導体層3の内部に大きな
応力が内在し、該大きな内在応力によって薄膜配線導体
層3が有機樹脂絶縁層2から剥離し易いものとなる。従
って、前記多層配線部4の各薄膜配線導体層3の厚みは
3μm乃至40μmの範囲としておくことが好ましい。
Further, when the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 is less than 3 μm, the electric resistance of the thin-film wiring conductor layer 3 becomes large, and a predetermined value is applied to each thin-film wiring conductor layer 3. It is difficult to transmit an electric signal. If the thickness exceeds 40 μm, a large stress is present inside the thin-film wiring conductor layer 3 when the thin-film wiring conductor layer 3 is applied to the organic resin insulating layer 2. Thereby, the thin film wiring conductor layer 3 is easily peeled off from the organic resin insulating layer 2. Therefore, it is preferable that the thickness of each thin-film wiring conductor layer 3 of the multilayer wiring portion 4 be in the range of 3 μm to 40 μm.

【0040】かくして、本発明の多層配線基板によれ
ば、基板1の上面に被着させた多層配線部4上に半導体
素子や容量素子、抵抗器等の電子部品Aを搭載実装さ
せ、電子部品Aの各電極を薄膜配線導体層3に電気的に
接続させることによって半導体装置や混成集積回路装置
となり、基板1に形成されている導電層6を外部電気回
路に接続すれば半導体装置や混成集積回路装置は外部電
気回路に電気的に接続されることとなる。
Thus, according to the multilayer wiring board of the present invention, the electronic component A such as a semiconductor element, a capacitance element, and a resistor is mounted and mounted on the multilayer wiring section 4 attached to the upper surface of the substrate 1. By electrically connecting each of the electrodes A to the thin film wiring conductor layer 3, a semiconductor device or a hybrid integrated circuit device is obtained. If the conductive layer 6 formed on the substrate 1 is connected to an external electric circuit, the semiconductor device or the hybrid integrated circuit device can be obtained. The circuit device is electrically connected to an external electric circuit.

【0041】なお、本発明は上述した実施例に限定され
るものではなく、本発明の要旨を逸脱しない範囲であれ
ば種々の変更は可能であり、例えば、上述の実施例にお
いては基板1の上面のみに有機樹脂絶縁層2と薄膜配線
導体層3とからなる多層配線部4を設けたが、多層配線
部4を基板1の下面側のみに設けても、上下の両面に設
けてもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Although the multilayer wiring portion 4 including the organic resin insulating layer 2 and the thin film wiring conductor layer 3 is provided only on the upper surface, the multilayer wiring portion 4 may be provided only on the lower surface side of the substrate 1 or on both upper and lower surfaces. .

【0042】[0042]

【発明の効果】本発明の多層配線基板によれば、基板を
有機樹脂中に、表面がポリテトラフルオロエチレンで被
覆されたアラミド繊維を10乃至60重量%含浸させて
形成したことから比誘電率が4(室温、1MHz)以下
と小さな値となり、これによって基板に形成されている
導電層を伝達する電気信号の伝搬速度を高速となすこと
が出来、電気信号を高速で伝達させる必要のある高速駆
動の半導体素子等の実装が可能となる。
According to the multilayer wiring board of the present invention, the substrate is formed by impregnating an organic resin with an aramid fiber whose surface is coated with polytetrafluoroethylene in an amount of 10 to 60% by weight. Has a small value of 4 (room temperature, 1 MHz) or less, whereby the propagation speed of the electric signal transmitted through the conductive layer formed on the substrate can be made high, and the high speed at which the electric signal needs to be transmitted at a high speed can be obtained. It is possible to mount a driving semiconductor element or the like.

【0043】また本発明の多層配線基板によれば、基板
上に薄膜形成技術によって配線導体の一部を形成したこ
とから配線導体の微細化が可能となり、従来に比べて配
線を極めて高密度に形成することが可能となる。
Further, according to the multilayer wiring board of the present invention, since a part of the wiring conductor is formed on the substrate by a thin film forming technique, the wiring conductor can be miniaturized. It can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・基板 2・・・有機樹脂絶縁層 3・・・薄膜配線導体層 4・・・多層配線部 5・・・貫通孔 6・・・導電層 9・・・スルーホール 10・・スルーホール導体 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Organic resin insulating layer 3 ... Thin film wiring conductor layer 4 ... Multilayer wiring part 5 ... Through-hole 6 ... Conductive layer 9 ... Through-hole 10 ... Through Hall conductor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】導電層を有する基板上に、有機樹脂絶縁層
と薄膜配線導体層とを交互に多層に積層して成る多層配
線部を設けるとともに前記導電層と薄膜配線導体層とを
電気的に接続して成る多層配線基板であって、前記基板
は有機樹脂中に、表面がポリテトラフルオロエチレンで
被覆されたアラミド繊維を含浸させて形成されているこ
とを特徴とする多層配線基板。
1. A multi-layer wiring section comprising an organic resin insulating layer and a thin-film wiring conductor layer alternately laminated in multiple layers on a substrate having a conductive layer, and the conductive layer and the thin-film wiring conductor layer are electrically connected to each other. Wherein the substrate is formed by impregnating an organic resin with an aramid fiber whose surface is covered with polytetrafluoroethylene.
【請求項2】前記有機樹脂中におけるアラミド繊維の含
浸率が10乃至60重量%であることを特徴とする請求
項1に記載の多層配線基板。
2. The multilayer wiring board according to claim 1, wherein the impregnation rate of the aramid fiber in the organic resin is 10 to 60% by weight.
JP25210197A 1997-09-17 1997-09-17 Multilayered wiring board Pending JPH1197851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25210197A JPH1197851A (en) 1997-09-17 1997-09-17 Multilayered wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25210197A JPH1197851A (en) 1997-09-17 1997-09-17 Multilayered wiring board

Publications (1)

Publication Number Publication Date
JPH1197851A true JPH1197851A (en) 1999-04-09

Family

ID=17232531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25210197A Pending JPH1197851A (en) 1997-09-17 1997-09-17 Multilayered wiring board

Country Status (1)

Country Link
JP (1) JPH1197851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085373A (en) * 2007-12-19 2008-04-10 Ibiden Co Ltd Printed circuit board and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085373A (en) * 2007-12-19 2008-04-10 Ibiden Co Ltd Printed circuit board and its manufacturing method

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