JPH10124407A5 - - Google Patents

Info

Publication number
JPH10124407A5
JPH10124407A5 JP1997266553A JP26655397A JPH10124407A5 JP H10124407 A5 JPH10124407 A5 JP H10124407A5 JP 1997266553 A JP1997266553 A JP 1997266553A JP 26655397 A JP26655397 A JP 26655397A JP H10124407 A5 JPH10124407 A5 JP H10124407A5
Authority
JP
Japan
Prior art keywords
electronic devices
expansion bus
subgroup
detection means
transmission lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997266553A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10124407A (ja
Filing date
Publication date
Priority claimed from US08/723,767 external-priority patent/US5867645A/en
Application filed filed Critical
Publication of JPH10124407A publication Critical patent/JPH10124407A/ja
Publication of JPH10124407A5 publication Critical patent/JPH10124407A5/ja
Pending legal-status Critical Current

Links

JP9266553A 1996-09-30 1997-09-30 フォールト・トレラント相互接続装置を有するコンピュータ・システム Pending JPH10124407A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US723767 1985-04-16
US08/723,767 US5867645A (en) 1996-09-30 1996-09-30 Extended-bus functionality in conjunction with non-extended-bus functionality in the same bus system

Publications (2)

Publication Number Publication Date
JPH10124407A JPH10124407A (ja) 1998-05-15
JPH10124407A5 true JPH10124407A5 (enExample) 2005-04-21

Family

ID=24907587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9266553A Pending JPH10124407A (ja) 1996-09-30 1997-09-30 フォールト・トレラント相互接続装置を有するコンピュータ・システム

Country Status (4)

Country Link
US (1) US5867645A (enExample)
EP (1) EP0836141B1 (enExample)
JP (1) JPH10124407A (enExample)
DE (1) DE69717232T2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5941997A (en) * 1996-11-26 1999-08-24 Play Incorporated Current-based contention detection and handling system
US6035425A (en) * 1997-09-29 2000-03-07 Lsi Logic Corporation Testing a peripheral bus for data transfer integrity by detecting corruption of transferred data
US6018810A (en) * 1997-12-12 2000-01-25 Compaq Computer Corporation Fault-tolerant interconnection means in a computer system
US6212588B1 (en) * 1998-03-09 2001-04-03 Texas Instruments Incorporated Integrated circuit for controlling a remotely located mass storage peripheral device
US6449677B1 (en) * 1998-09-03 2002-09-10 Compaq Information Technologies Group, L.P. Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus
US6865615B1 (en) * 2000-07-20 2005-03-08 International Business Machines Corporation Method and an apparatus for dynamically reconfiguring a system bus topology
US6691193B1 (en) * 2000-10-18 2004-02-10 Sony Corporation Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
US6954209B2 (en) * 2000-12-06 2005-10-11 Hewlett-Packard Development Company, L.P. Computer CPU and memory to accelerated graphics port bridge having a plurality of physical buses with a single logical bus number
US6898740B2 (en) * 2001-01-25 2005-05-24 Hewlett-Packard Development Company, L.P. Computer system having configurable core logic chipset for connection to a fault-tolerant accelerated graphics port bus and peripheral component interconnect bus
US20030188080A1 (en) * 2002-03-28 2003-10-02 Olarig Sompong Paul Apparatus, method and system for remote registered peripheral component interconnect bus
US7392445B2 (en) 2003-09-11 2008-06-24 International Business Machines Corporation Autonomic bus reconfiguration for fault conditions
US7054966B2 (en) * 2004-06-14 2006-05-30 General Electric Company Data processing system
JP2006153927A (ja) * 2004-11-25 2006-06-15 Sanyo Electric Co Ltd 表示装置
US7788420B2 (en) * 2005-09-22 2010-08-31 Lsi Corporation Address buffer mode switching for varying request sizes
US10756857B2 (en) * 2013-01-25 2020-08-25 Infineon Technologies Ag Method, apparatus and computer program for digital transmission of messages
US9454419B2 (en) 2013-07-18 2016-09-27 Advanced Micro Devices, Inc. Partitionable data bus
WO2015006946A1 (en) * 2013-07-18 2015-01-22 Advanced Micro Devices, Inc. Partitionable data bus

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69331061T2 (de) * 1992-08-10 2002-06-06 Monolithic System Tech Inc Fehlertolerantes hierarchisiertes Bussystem
US5448703A (en) * 1993-05-28 1995-09-05 International Business Machines Corporation Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
US5499346A (en) * 1993-05-28 1996-03-12 International Business Machines Corporation Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
US5522050A (en) * 1993-05-28 1996-05-28 International Business Machines Corporation Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
US5450551A (en) * 1993-05-28 1995-09-12 International Business Machines Corporation System direct memory access (DMA) support logic for PCI based computer system
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
DE69518286T2 (de) * 1994-06-17 2001-02-22 Advanced Micro Devices, Inc. Speicherübertragungsgeschwindigkeitsbegrenzung für PCI-Meister
US5630056A (en) * 1994-09-20 1997-05-13 Stratus Computer, Inc. Digital data processing methods and apparatus for fault detection and fault tolerance
JPH08147241A (ja) * 1994-11-22 1996-06-07 Seiko Epson Corp 情報処理装置およびその構成方法
DE4442309C2 (de) * 1994-11-28 1997-03-13 Siemens Nixdorf Inf Syst Hochverfügbarkeitsanschluß für Single-Port Peripherie
DE19509558A1 (de) * 1995-03-16 1996-09-19 Abb Patent Gmbh Verfahren zur fehlertoleranten Kommunikation unter hohen Echtzeitbedingungen
US5754804A (en) * 1996-01-30 1998-05-19 International Business Machines Corporation Method and system for managing system bus communications in a data processing system

Similar Documents

Publication Publication Date Title
JPH10124407A5 (enExample)
US5682518A (en) System for updating inactive system memory using dual port memory
JPH10143387A5 (enExample)
ATE22360T1 (de) Steuerungseinrichtung fuer computerperipherie.
DE3275595D1 (en) Digital data processor with fault-tolerant bus protocol
CZ9701508A3 (cs) Počítačový systém se sběrnicovým rozhraním
CN104615297A (zh) 触摸感测系统和显示装置
CA2129825A1 (en) Real Time Processing System
JPH09230970A5 (enExample)
JPH10132908A5 (enExample)
JP2001256109A5 (enExample)
JP3574061B2 (ja) プロセッサ・バス構造
JP2000039934A5 (enExample)
JPH0155502B2 (enExample)
CN214311707U (zh) 一种基于腾云s2500的双路服务器冗余显示系统
JPH09212472A (ja) マルチプロセッサシステム
JP2007164722A (ja) Ｃｐｕ二重化用ベースユニットおよびｃｐｕ二重化システム
JPH087442Y2 (ja) プログラマブルコントローラの入出力装置
JP2004348580A (ja) シリアルインターフェース回路及び半導体集積回路
KR20050117924A (ko) 프로세서간 통신 향상을 위한 구조 및 방법
JPH02157952A (ja) 記憶装置
JPH07104795B2 (ja) エラ−検出方式
JP2640139B2 (ja) メモリカード
JPH05290008A (ja) マルチｃｐｕシステムのリセット方式
JPS63149748A (ja) 記憶装置