JPH10107188A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH10107188A JPH10107188A JP25667596A JP25667596A JPH10107188A JP H10107188 A JPH10107188 A JP H10107188A JP 25667596 A JP25667596 A JP 25667596A JP 25667596 A JP25667596 A JP 25667596A JP H10107188 A JPH10107188 A JP H10107188A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor element
- semiconductor device
- heat
- concave portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は各種の電子機器・電
子装置等の電子回路モジュール等として使用される、多
層配線基板を用いた半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a multi-layer wiring board, which is used as an electronic circuit module of various electronic devices and devices.
【０００２】[0002]
【従来の技術】近年、各種の電子機器や電子装置等に対
して小型化・薄型化・高機能化等の要求がますます高ま
っており、それらの要求を実現するために、それら機器
や装置の電子回路モジュールとして使用される半導体装
置にも小型化・薄型化・高密度化ならびに高速信号処理
に対応した高機能化さらには低コスト化が強く要求さ
れ、それに対して多層配線基板等の配線基板を用いた半
導体装置の実用化が進められている。2. Description of the Related Art In recent years, there has been an increasing demand for various electronic devices and electronic devices to be smaller, thinner, and more sophisticated. In order to realize these requirements, such devices and devices have been developed. For semiconductor devices used as electronic circuit modules, there is a strong demand for miniaturization, thinning, high-density, high functionality corresponding to high-speed signal processing, and low cost. Practical use of a semiconductor device using a substrate is in progress.
【０００３】そのような半導体装置に用いられる配線基
板には例えば以下のようなものがある。The following are examples of wiring boards used in such semiconductor devices.
【０００４】第１に、一般にアルミナや窒化アルミニウ
ム等のセラミックス材料を主成分とする絶縁基板の内部
に導体配線パターンを形成した配線基板がある。しか
し、この配線基板では、アルミナ等を主成分としたセラ
ミックス材料は1400〜1650℃程度の高温で焼成しなけれ
ばならないことから導体配線パターンには高融点金属で
あるタングステンやモリブデンを用いなければならない
が、これら高融点金属は比抵抗が高いため、高速信号処
理を行なう電子回路を有する半導体装置には適用できな
いという問題点があった。First, there is a wiring board in which a conductive wiring pattern is generally formed inside an insulating substrate mainly composed of a ceramic material such as alumina or aluminum nitride. However, in this wiring board, a ceramic material containing alumina or the like as a main component must be fired at a high temperature of about 1400 to 1650 ° C. Therefore, a high melting point metal such as tungsten or molybdenum must be used for the conductor wiring pattern. However, these refractory metals have a high specific resistance and cannot be applied to a semiconductor device having an electronic circuit for performing high-speed signal processing.
【０００５】また、窒化アルミニウム等の高熱伝導材料
を用いた配線基板では、良好な放熱特性を必要とする半
導体素子搭載用基板としては有効であるが、一般的な民
生分野に適用するには材料が高価であるため、低コスト
化が図れないという問題点もあった。A wiring board using a high heat conductive material such as aluminum nitride is effective as a substrate for mounting a semiconductor element requiring good heat radiation characteristics, but is not suitable for general consumer applications. However, since it is expensive, there is also a problem that cost reduction cannot be achieved.
【０００６】第２に、ガラス繊維と有機材料等から成る
ガラスエポキシ基板を用いた配線基板があるが、これは
安価ではあるが耐熱性に劣るため、上記の要求には十分
に応えられないという問題点があった。Secondly, there is a wiring board using a glass epoxy board made of glass fiber and an organic material, but this is inexpensive but has poor heat resistance, so that it cannot sufficiently meet the above requirements. There was a problem.
【０００７】第３に、ガラスフリットにアルミナ等の無
機フィラーを添加した材料から成るガラスセラミックス
基板を用いた配線基板がある。これは低温でかつ短時間
に焼成が可能なため低コスト化を図ることができ、また
内部の導体配線パターンには金系・銀系・銅系等の低融
点で比抵抗の小さい金属材料を用いることができるので
高速信号処理を行なう半導体装置にも有利である。Third, there is a wiring board using a glass ceramic substrate made of a material obtained by adding an inorganic filler such as alumina to glass frit. It can be fired at a low temperature and in a short time, so that the cost can be reduced.In addition, a metal material with low melting point and low specific resistance such as gold, silver or copper is used for the internal conductor wiring pattern. Since it can be used, it is advantageous for a semiconductor device which performs high-speed signal processing.
【０００８】[0008]
【発明が解決しようとする課題】これらの配線基板はそ
れぞれの特性ならびに用途に応じて使い分けられるが、
上記要求の実現のためには配線基板上に半導体素子を直
接搭載することが必要となってきており、半導体素子の
搭載方法においても実装面積の小型化を図るため、電気
的接続手法として従来のワイヤボンディング法に代わっ
て金属バンプ等を用いたいわゆるフリップチップ実装法
等が実用化されている。そして、近年の半導体素子の小
型化・高密度化・高電力化に伴って増大している半導体
素子の発熱による半導体素子の熱的破壊や信頼性劣化等
の悪影響をいかに抑えるかが重要な課題となっている。
特に、電子回路モジュールとして半導体装置にさらに小
型化と低コスト化が要求されている中で、配線基板に対
しても従来以上の良好な放熱性が必要とされている。These wiring boards can be used properly according to their characteristics and applications.
In order to fulfill the above requirements, it is necessary to mount the semiconductor element directly on the wiring board, and in order to reduce the mounting area in the method of mounting the semiconductor element, a conventional electrical connection method is used. Instead of the wire bonding method, a so-called flip-chip mounting method using a metal bump or the like has been put to practical use. An important issue is how to suppress adverse effects such as thermal destruction and reliability deterioration of semiconductor elements due to heat generation of semiconductor elements, which are increasing with recent miniaturization, higher density, and higher power of semiconductor elements. It has become.
In particular, while there is a demand for further miniaturization and cost reduction of a semiconductor device as an electronic circuit module, better heat dissipation than before is required for a wiring board.
【０００９】上記課題に対する対策としては従来、高熱
伝導率材料から成る基板に半導体素子を直接に実装する
方法や、半導体素子直下の基板中に多数のサーマルビア
ホールといわれる放熱部材を形成する方法等が挙げられ
ている。Conventionally, as a countermeasure against the above problem, a method of directly mounting a semiconductor element on a substrate made of a material having a high thermal conductivity, a method of forming a large number of heat radiating members called thermal via holes in a substrate immediately below the semiconductor element, and the like are known. Are listed.
【００１０】また、配線基板上に実装した半導体素子を
封止するためのキャップを利用する方法として、例えば
特開平８−17853 号公報には、回路基板の主表面に形成
された電極にバンプを介して半導体素子の一主表面上の
電極部分が固着され、少なくとも半導体素子・バンプお
よび電極を覆うように金属キャップを設け、金属キャッ
プと回路基板とで覆われた内部を樹脂で封止して成り、
金属キャップの内面に半導体素子の他の主表面と接触す
る突起が形成されている半導体装置が提案されている。
これによれば、金属キャップの内面と半導体素子の一主
表面とが全面で接触しないように突起が形成され、しか
もこの隙間が封止樹脂で充填されているため、半導体素
子の発熱や雰囲気温度の変動等に伴う熱膨張係数差に起
因するストレスを弾力的に受け止めてこの部分のはがれ
や破損等を防ぐことができ、また、熱伝導性の優れたフ
ィラー入りの封止樹脂を用いることにより放熱性を良く
することができて放熱効果が一定となるというものであ
る。As a method of using a cap for sealing a semiconductor element mounted on a wiring board, for example, Japanese Patent Application Laid-Open No. 8-17853 discloses a method in which a bump is formed on an electrode formed on a main surface of a circuit board. An electrode portion on one main surface of the semiconductor element is fixed via a metal cap provided so as to cover at least the semiconductor element, the bump and the electrode, and the inside covered with the metal cap and the circuit board is sealed with resin. Consisting of
There has been proposed a semiconductor device in which a projection is formed on the inner surface of a metal cap so as to contact another main surface of a semiconductor element.
According to this, a projection is formed so that the inner surface of the metal cap and one main surface of the semiconductor element do not come into contact with each other over the entire surface, and since this gap is filled with the sealing resin, heat generation of the semiconductor element and ambient temperature Can flexibly receive the stress caused by the difference in the coefficient of thermal expansion due to the fluctuation of the surface, preventing peeling or breakage of this part, and by using a sealing resin containing a filler with excellent thermal conductivity. The heat radiation property can be improved, and the heat radiation effect becomes constant.
【００１１】しかし、この特開平８−17853 号公報の半
導体装置によっては、金属キャップと半導体素子とが全
面で接触していないため、封止樹脂として熱伝導性の優
れたフィラー入りの樹脂を用いても十分に良好な放熱効
果は得られないという問題点があった。However, according to the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 8-17853, since the metal cap and the semiconductor element are not in contact over the entire surface, a resin containing a filler having excellent heat conductivity is used as a sealing resin. However, there is a problem that a sufficiently good heat radiation effect cannot be obtained.
【００１２】また、高密度化・高機能化の観点から多層
配線基板として近年配線基板に多用されるようになって
いるガラスセラミックス基板においては、小型化のため
にフリップチップ実装法が取り入れられ、半導体素子の
発熱対策として多数のサーマルビアホールが活用されて
いる。On the other hand, in a glass ceramic substrate which has recently been frequently used as a multilayer wiring substrate as a multilayer wiring substrate from the viewpoint of high density and high functionality, a flip chip mounting method has been adopted for downsizing. Many thermal via holes are used as a measure against heat generation of semiconductor elements.
【００１３】しかしながら、ガラスセラミックス基板で
は基板の焼成に伴う収縮率のばらつきが大きく、また電
極形成法として安価な印刷手法を採用しているため、フ
リップチップ実装法に必要な基板の寸法精度および表面
粗さを確保することが困難であるという問題点があっ
た。However, since the glass ceramic substrate has a large variation in shrinkage due to the firing of the substrate and employs an inexpensive printing method as an electrode forming method, the dimensional accuracy and surface of the substrate required for the flip chip mounting method are required. There is a problem that it is difficult to secure the roughness.
【００１４】一方、半導体装置に搭載される半導体素子
の側から見ると、配線基板に直接に半導体素子を実装す
ることは半導体素子の交換や再利用を図ることをできな
くする行為であると言えることから、高価な半導体素子
や配線基板あるいは半導体素子とともに実装される一般
電子部品等の受動回路素子といった半導体装置を構成す
る部材の省資源化の観点からは必ずしも好ましいものと
は言えないという問題点もあった。On the other hand, when viewed from the side of the semiconductor element mounted on the semiconductor device, it can be said that mounting the semiconductor element directly on the wiring board is an act that makes it impossible to replace or reuse the semiconductor element. Therefore, it is not always preferable from the viewpoint of resource saving of members constituting a semiconductor device such as an expensive semiconductor element, a wiring board, or a passive circuit element such as a general electronic component mounted together with the semiconductor element. There was also.
【００１５】本発明は、上記問題点に鑑みて本発明者が
鋭意研究を進めた結果完成したものであり、その目的
は、電子回路モジュール等に使用される、安価な配線基
板を用いた半導体装置について、半導体素子からの発熱
を効率良く放熱させることができ、小型化・薄型化・高
密度化ならびに高速信号処理に対応した高機能化さらに
は低コスト化が可能な半導体装置を提供することにあ
る。The present invention has been accomplished in view of the above problems and has been completed by the inventors of the present invention. The object of the present invention is to provide a semiconductor device using an inexpensive wiring board for an electronic circuit module or the like. To provide a semiconductor device that can efficiently radiate heat generated from a semiconductor element, and that can be miniaturized, thinned, and made high-density, and capable of achieving high functionality and high cost for signal processing. It is in.
【００１６】[0016]
【課題を解決するための手段】本発明の半導体装置は、
ガラスセラミックスから成り、表面に凹部を有する配線
基板と、前記凹部の開口寸法とほぼ同じ寸法の高熱伝導
材料から成る補助配線基板と、該補助配線基板の表面の
電極に金属バンプを介して電気的に接続された半導体素
子とから成り、前記配線基板は凹部の開口周辺に段差部
を有するとともに凹部底面から裏面にかけて複数個の熱
伝導部材が埋設されており、前記半導体素子の裏面を前
記凹部の底面にロウ付けするとともに前記補助配線基板
を前記凹部の段差部に封止材を介して接合させたことを
特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
A wiring board made of glass ceramic and having a concave portion on the surface, an auxiliary wiring board made of a high heat conductive material having substantially the same dimension as the opening dimension of the concave portion, and electrically connecting the electrodes on the surface of the auxiliary wiring board via metal bumps. The wiring board has a step around the opening of the recess, and a plurality of heat conducting members are embedded from the bottom to the back of the recess. The semiconductor device is characterized in that the auxiliary wiring board is joined to a step portion of the concave portion via a sealing material while being brazed to a bottom surface.
【００１７】本発明の半導体装置によれば、半導体素子
を配線基板の表面に形成した凹部の開口寸法とほぼ同じ
寸法の高熱伝導材料から成る補助配線基板に金属バンプ
を介して電気的に接続していわゆるフリップチップ実装
していることから、半導体素子の実装面積の小型化を図
ることができる。また、この補助配線基板を配線基板の
凹部の段差部に載置して封止材を介して接合し、かつ半
導体素子の裏面を複数個の熱伝導部材を有する凹部の底
面にロウ付けしたことから、半導体素子から発生する熱
は補助配線基板自体による放熱はもとより複数個の熱伝
導部材によっても効率良く伝導させて配線基板の裏面か
ら放熱させることが可能となり、優れた放熱効果を得る
ことができるものとなる。その結果、半導体素子の温度
上昇やそれによる悪影響を所望通りに抑制することがで
きて、半導体素子ならびに回路本来の性能を十分発揮さ
せ、電子回路モジュールとしての機能を十分に維持でき
る高信頼性の半導体装置を提供することができる。According to the semiconductor device of the present invention, the semiconductor element is electrically connected to the auxiliary wiring board made of a high heat conductive material having substantially the same dimension as the opening dimension of the concave portion formed on the surface of the wiring board via the metal bump. Therefore, the mounting area of the semiconductor element can be reduced because of the so-called flip-chip mounting. Further, the auxiliary wiring board is placed on the stepped portion of the concave portion of the wiring substrate and joined via a sealing material, and the back surface of the semiconductor element is brazed to the bottom surface of the concave portion having a plurality of heat conducting members. Therefore, the heat generated from the semiconductor element can be efficiently conducted not only by the auxiliary wiring board itself but also by a plurality of heat conducting members and can be radiated from the back surface of the wiring board, thereby obtaining an excellent heat dissipation effect. You can do it. As a result, the temperature rise of the semiconductor element and its adverse effects can be suppressed as desired, and the semiconductor element and the original performance of the circuit can be fully exhibited, and the high reliability which can sufficiently maintain the function as the electronic circuit module can be obtained. A semiconductor device can be provided.
【００１８】また、本発明の半導体装置によれば、配線
基板がガラスセラミックスから成るものであることか
ら、アルミナ等のセラミックス材料のような高温で焼成
する必要がなく、低温で焼成が可能なため安価であると
ともに内部の導体配線パターンには金系・銀系・銅系等
の低融点で比抵抗の小さい金属材料を用いることができ
るので回路の高速信号処理への対応が可能となる。Further, according to the semiconductor device of the present invention, since the wiring substrate is made of glass ceramic, it is not necessary to fire at a high temperature such as a ceramic material such as alumina. Since it is inexpensive and a metal material having a low melting point and low specific resistance such as gold, silver or copper can be used for the internal conductor wiring pattern, it is possible to cope with high-speed signal processing of the circuit.
【００１９】さらに、本発明の半導体装置によれば、半
導体素子が搭載された補助配線基板は配線基板の凹部の
段差部に載置されて封止材を介して接合されることか
ら、半導体素子を凹部内に収容して気密に封止すること
ができ、従来のように配線基板の表面に半導体素子を直
接搭載して樹脂封止したものよりも良好な封止ができる
ので、極めて信頼性の高い半導体装置となる。また、こ
の補助配線基板を樹脂封止することによりさらに信頼性
を高めることができる。Further, according to the semiconductor device of the present invention, since the auxiliary wiring board on which the semiconductor element is mounted is placed on the step of the concave portion of the wiring board and joined via the sealing material, Can be hermetically sealed by being housed in the concave portion, and it is possible to achieve better sealing than the case where the semiconductor element is directly mounted on the surface of the wiring board and resin-sealed as in the conventional case, thus achieving extremely high reliability. Semiconductor device. The reliability can be further improved by sealing the auxiliary wiring board with resin.
【００２０】さらにまた、本発明の半導体装置によれ
ば、半導体素子は補助配線基板に搭載され、この補助配
線基板は受動回路素子である一般的な電子部品、例えば
抵抗器やコンデンサ等と同様に配線基板に搭載されるこ
とから、それら受動回路素子と同様に交換可能な構造と
することができるので、半導体素子や受動回路素子ひい
ては配線基板の再利用を図ることができ、省資源化の観
点から好ましいものとすることができる。Further, according to the semiconductor device of the present invention, the semiconductor element is mounted on the auxiliary wiring board, and this auxiliary wiring board is the same as a general electronic component that is a passive circuit element, such as a resistor or a capacitor. Since it is mounted on a wiring board, the structure can be replaced similarly to those passive circuit elements, so that semiconductor elements and passive circuit elements, and furthermore, wiring boards can be reused, and a viewpoint of resource saving. Can be preferred.
【００２１】[0021]
【発明の実施の形態】以下、本発明の半導体装置につい
て図面を参照しながら詳細に説明する。図１は本発明の
半導体装置の実施の形態の一例を示す断面図であり、図
２はその平面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing an example of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof.
【００２２】これらの図において、１はガラスセラミッ
クスから成る配線基板であり、ここでは複数のガラスセ
ラミックス絶縁層２が積層されて成る多層配線基板を用
いた例を示している。この配線基板１の内部には半導体
装置の仕様に応じた所定の導体配線パターン（図示せ
ず）が配され、表面には開口周辺に段差部１ｂを有する
凹部１ａが形成されている。３は凹部１ａの開口寸法と
ほぼ同じ寸法を有する高熱伝導材料から成る補助配線基
板、４は補助配線基板３の表面にその表面の電極に金属
バンプを介して電気的に接続されて搭載された半導体素
子であり、半導体素子４を下にして補助配線基板３が段
差部１ｂに載置され封止材を介して接合されることによ
り、凹部１ａ内部に半導体素子４が収容される。In these figures, reference numeral 1 denotes a wiring board made of glass ceramics, and here, an example is shown in which a multilayer wiring board formed by laminating a plurality of glass ceramic insulating layers 2 is used. A predetermined conductor wiring pattern (not shown) according to the specifications of the semiconductor device is arranged inside the wiring board 1, and a concave portion 1a having a step portion 1b around the opening is formed on the surface. Reference numeral 3 denotes an auxiliary wiring board made of a high thermal conductive material having substantially the same dimension as the opening dimension of the concave portion 1a, and reference numeral 4 denotes a surface of the auxiliary wiring board 3, which is electrically connected to electrodes on the surface via metal bumps. The semiconductor element 4 is accommodated in the concave portion 1a by placing the auxiliary wiring board 3 on the stepped portion 1b with the semiconductor element 4 facing down and joining it via a sealing material.
【００２３】５は複数個の熱伝導部材であり、凹部１ａ
の底面から配線基板１の裏面にかけてガラスセラミック
ス絶縁層２を貫通して埋設され、半導体素子４から発生
する熱を凹部１ａの底面から配線基板１の裏面に伝導す
るためのものである。この熱伝導部材５は、凹部１ａの
段差部１ｂの底面からも埋設してよく、それにより高熱
伝導材料から成る補助配線基板３に伝わった半導体素子
４からの発熱も配線基板１の裏面に伝導させることがで
きる。これら複数個の熱伝導部材５は、搭載される半導
体素子４の寸法や発熱量・配線基板１の加工精度などに
応じて、最も効率よく放熱に寄与するように、例えば格
子状や千鳥状など、所定の位置精度を有して埋設され
る。Reference numeral 5 denotes a plurality of heat conducting members,
Is embedded from the bottom surface of the wiring board 1 to the back surface of the wiring board 1 so as to penetrate through the glass ceramic insulating layer 2 to conduct heat generated from the semiconductor element 4 from the bottom surface of the concave portion 1a to the back surface of the wiring board 1. The heat conductive member 5 may be embedded also from the bottom surface of the step portion 1b of the concave portion 1a, whereby heat generated from the semiconductor element 4 transmitted to the auxiliary wiring substrate 3 made of a high heat conductive material is also transmitted to the back surface of the wiring substrate 1. Can be done. Depending on the dimensions of the semiconductor element 4 to be mounted, the amount of heat generated, the processing accuracy of the wiring board 1, and the like, the plurality of heat conductive members 5 are, for example, in a lattice shape or a staggered shape so as to contribute to heat radiation most efficiently. Is buried with a predetermined positional accuracy.
【００２４】６は配線基板１の少なくとも凹部１ａと対
向する裏面に形成された裏面導体層である。この裏面導
体層６は必要に応じて設ければよく、これに熱伝導部材
５を接続することにより半導体素子４からの熱が裏面導
体層６に伝導されるので、この半導体装置が実装される
マザーボードや放熱フィン等に効率良く伝えて放熱させ
ることができる。Reference numeral 6 denotes a back surface conductor layer formed on the back surface of the wiring board 1 facing at least the concave portion 1a. The back conductor layer 6 may be provided as needed, and the heat from the semiconductor element 4 is conducted to the back conductor layer 6 by connecting the heat conducting member 5 to the back conductor layer 6, so that the semiconductor device is mounted. The heat can be efficiently transmitted to the motherboard, the radiating fins, and the like to release the heat.
【００２５】また、７は複数個の熱伝導部材５をガラス
セラミックス絶縁層２間において接続する内層導体層で
あり、これも必要に応じて設ければよく、これら内層導
体層７を配した場合には、熱伝導部材５による熱伝導を
その内層導体層７を介してより効率的に行なうことがで
きるものとなる。Reference numeral 7 denotes an inner conductor layer for connecting the plurality of heat conducting members 5 between the glass ceramic insulating layers 2. The inner conductor layer may be provided as needed. Thus, the heat conduction by the heat conducting member 5 can be more efficiently performed through the inner conductor layer 7.
【００２６】半導体素子４はその表面の電極を補助配線
基板３の表面の電極に金属バンプ８を介して電気的に接
続されているとともに、その裏面すなわち補助配線基板
３に面していない側の面を凹部１ａの底面にロウ材９に
よりロウ付けされている。なお、補助配線基板３と半導
体素子４との隙間には、いわゆるアンダーフィル樹脂を
充填してもよい。The semiconductor element 4 has its electrodes on the front surface electrically connected to the electrodes on the front surface of the auxiliary wiring substrate 3 via the metal bumps 8, and has its back surface, that is, on the side not facing the auxiliary wiring substrate 3. The surface is brazed with the brazing material 9 to the bottom surface of the concave portion 1a. The gap between the auxiliary wiring board 3 and the semiconductor element 4 may be filled with a so-called underfill resin.
【００２７】そして、補助配線基板３は段差部１ｂに載
置され、ロウ材等の封止材10を介して接合されるととも
に、補助配線基板３の表面の半導体素子４と電気的に接
続された電極から導出された裏面の電極11を多層配線基
板１の表面の電極12にＡｕやＡｌ等の金属材料から成る
ボンディングワイヤやリボン等の接続線13を介して電気
的に接続されている。また、補助配線基板３の表面の半
導体素子４と電気的に接続された電極から段差部１ｂに
対応する表面の周辺部に導出された電極を段差部１ｂに
形成された電極に封止材10とともに配設した金属バンプ
を介して電気的に接続してもよく、これを接続線13によ
る接続と併用してもよい。The auxiliary wiring substrate 3 is placed on the stepped portion 1b, is joined via a sealing material 10 such as a brazing material, and is electrically connected to the semiconductor element 4 on the surface of the auxiliary wiring substrate 3. The electrode 11 on the back surface derived from the electrode thus formed is electrically connected to the electrode 12 on the surface of the multilayer wiring board 1 via a connection line 13 such as a bonding wire or ribbon made of a metal material such as Au or Al. In addition, an electrode led out from an electrode electrically connected to the semiconductor element 4 on the surface of the auxiliary wiring board 3 to a peripheral portion of the surface corresponding to the step portion 1b is attached to the electrode formed on the step portion 1b by a sealing material 10. May be electrically connected via a metal bump provided together with the above, and this may be used together with the connection by the connection line 13.
【００２８】なお、14はエポキシ樹脂等の封止樹脂であ
り、必要に応じて用いることにより接続線13による接続
信頼性や環境安定性等を高めることができる。この封止
樹脂14には、補助配線基板３からの放熱を良好にすべく
熱伝導率の高いフィラーを含有させてもよい。また、15
は回路素子、16は回路素子用電極であり、回路素子15と
しての抵抗やコンデンサのようなチップ部品等が半田17
等により回路素子用電極16に接続されて、所望の電子回
路が構成される。Reference numeral 14 denotes a sealing resin such as an epoxy resin, which can be used as necessary to improve connection reliability and environmental stability of the connection line 13. The sealing resin 14 may contain a filler having a high thermal conductivity in order to improve heat radiation from the auxiliary wiring board 3. Also, 15
Is a circuit element, 16 is a circuit element electrode, and chip parts such as a resistor and a capacitor as the circuit element 15 are soldered 17.
It is connected to the circuit element electrode 16 by the above-mentioned method and the like to form a desired electronic circuit.
【００２９】かくして、電子回路モジュール等として使
用される、配線基板１を用いた本発明の半導体装置が構
成され、このように補助配線基板３を配線基板１の凹部
１ａの段差部１ｂに載置して封止材10を介して接合し、
かつ補助配線基板３に搭載された半導体素子４の裏面を
複数個の熱伝導部材５を有する凹部１ａの底面にロウ材
９によりロウ付けしたことから、半導体素子４から発生
する熱は補助配線基板３自体による放熱はもとより複数
個の熱伝導部材５によっても効率良く伝導させて配線基
板１の裏面から放熱させることが可能となり、優れた放
熱効果を得ることができ、その結果、半導体素子４の温
度上昇やそれによる悪影響を所望通りに抑制することが
できて、半導体素子４ならびに回路本来の性能を十分発
揮させることが可能な、電子回路モジュールとしての機
能を十分に維持できる高信頼性の半導体装置を提供する
ことができた。Thus, the semiconductor device of the present invention using the wiring board 1 used as an electronic circuit module or the like is constituted. In this manner, the auxiliary wiring board 3 is mounted on the step 1b of the concave portion 1a of the wiring board 1. And joined via the sealing material 10,
In addition, since the back surface of the semiconductor element 4 mounted on the auxiliary wiring board 3 is brazed to the bottom surface of the concave portion 1a having the plurality of heat conducting members 5 with the brazing material 9, the heat generated from the semiconductor element 4 does not increase. In addition to the heat radiation by itself 3, the heat can be efficiently conducted by the plurality of heat conducting members 5 and radiated from the back surface of the wiring board 1, and an excellent heat radiation effect can be obtained. A highly reliable semiconductor that can sufficiently suppress the temperature rise and its adverse effects, and can sufficiently exhibit the inherent performance of the semiconductor element 4 and the circuit, and can sufficiently maintain the function as an electronic circuit module. Equipment could be provided.
【００３０】また、半導体素子４が搭載された補助配線
基板３は配線基板１の凹部１ａの段差部１ｂに載置され
て封止材10を介して接合されることから、半導体素子４
を凹部１ａ内に収容して気密に封止することができ、従
来のように配線基板の表面に半導体素子を直接搭載して
樹脂封止したものよりも良好な封止ができるので、極め
て信頼性の高い半導体装置とすることができた。また、
この補助配線基板３を封止樹脂14で封止することにより
さらに信頼性を高めることができる。Since the auxiliary wiring board 3 on which the semiconductor element 4 is mounted is placed on the step 1b of the concave portion 1a of the wiring board 1 and joined via the sealing material 10, the semiconductor element 4
Can be housed in the recess 1a and hermetically sealed, and better sealing can be achieved than in the conventional case where the semiconductor element is directly mounted on the surface of the wiring board and resin-sealed. The semiconductor device has high performance. Also,
By sealing the auxiliary wiring board 3 with the sealing resin 14, the reliability can be further improved.
【００３１】さらに、半導体素子４は補助配線基板３に
搭載され、この補助配線基板３は受動回路素子15である
一般的な電子部品、例えば抵抗器やコンデンサ等と同様
に配線基板に搭載されることから、それら受動回路素子
15と同様に交換可能な構造とすることができるので、半
導体素子４や受動回路素子15ひいては配線基板１の再利
用を図ることができる。Further, the semiconductor element 4 is mounted on the auxiliary wiring board 3, and this auxiliary wiring board 3 is mounted on the wiring board in the same manner as general electronic components, such as resistors and capacitors, which are passive circuit elements 15. Therefore, those passive circuit elements
Since the structure can be replaced similarly to the structure 15, the semiconductor element 4 and the passive circuit element 15 and thus the wiring board 1 can be reused.
【００３２】配線基板１の製造方法としては以下のよう
なものがある。まず、ガラスセラミックス絶縁層２の原
材料、例えばＳｉＯ2 およびＡｌ2 Ｏ3 ・ＭｇＯ・Ｚｎ
Ｏ・Ｂ2 Ｏ3 ・ＰｂＯを主成分とするガラス粉末55重量
％と、無機フィラーとしてのＡｌ2 Ｏ3 粉末45重量％と
をバインダおよび可塑剤・溶剤とともに混練してスラリ
ー状とし、このスラリーをドクターブレード法によりシ
ート状に成形してガラスセラミックス絶縁層２を形成す
るためのグリーンシートを作製する。There are the following methods for manufacturing the wiring board 1. First, raw materials of the glass ceramic insulating layer 2, for example, SiO 2 and Al 2 O 3 .MgO.Zn
Glass powder 55 wt% of the O · B 2 O 3 · PbO as a main component and Al 2 O 3 powder 45% by weight of the inorganic filler is kneaded together with a binder and a plasticizer, solvent form a slurry, the slurry Is formed into a sheet by a doctor blade method to produce a green sheet for forming the glass-ceramic insulating layer 2.
【００３３】所定のグリーンシートには、各ガラスセラ
ミックス絶縁層２の層間の電気的導通を取るための導体
配線パターンとしてのビアホールならびに熱伝導部材５
としてのサーマルビアホールを形成するためのスルーホ
ールをパンチング加工により設ける。The predetermined green sheet includes via holes as conductor wiring patterns for establishing electrical continuity between the layers of each glass ceramic insulating layer 2 and a heat conductive member 5.
A through hole for forming a thermal via hole is formed by punching.
【００３４】次に、グリーンシートのスルーホールに銀
系・金系・銅系等の導電性材料から成る導電性ペースト
をスクリーン印刷法等により充填する。この導電性ペー
ストは、例えば粒径が 0.5〜５μｍの銀粉末と低熱膨張
性ガラスフリットとバインダとしてのエチルセルロース
と溶剤としての2,2,4-トリメチル−1,3-ペンタンジオー
ルモノイソブチレートとを均質に混練したものである。Next, a conductive paste made of a conductive material such as silver, gold, or copper is filled in the through holes of the green sheet by a screen printing method or the like. This conductive paste is, for example, a silver powder having a particle size of 0.5 to 5 μm, a low thermal expansion glass frit, ethyl cellulose as a binder, and 2,2,4-trimethyl-1,3-pentanediol monoisobutyrate as a solvent. Is homogeneously kneaded.
【００３５】次に、所定のグリーンシートの表面に同様
の導電性ペーストを用いて所望の導体配線パターンおよ
び裏面導体層６・内層導体層７等を印刷する。Next, a desired conductor wiring pattern, a back conductor layer 6, an inner conductor layer 7, and the like are printed on the surface of a predetermined green sheet using the same conductive paste.
【００３６】なお、これらの導体配線パターンや導体層
の材料となる導電性ペーストは、前述のビアホール用導
電性ペーストに含まれる低熱膨張性ガラスフリットに代
えて屈伏点が 700〜850 ℃のガラスフリットを加えたも
の等が用いられる。このような導電性ペーストを用いれ
ば、導電性ペーストの焼結開始温度とグリーンシートの
焼結開始温度とを近接させることが可能となり、反りや
変形のないガラスセラミックス絶縁層２から成る多層配
線基板として配線基板１が得られる。The conductive paste used as the material for these conductive wiring patterns and conductive layers is a glass frit having a yield point of 700 to 850 ° C. instead of the low thermal expansion glass frit contained in the conductive paste for via holes. Is used. If such a conductive paste is used, the sintering start temperature of the conductive paste and the sintering start temperature of the green sheet can be made close to each other, and the multilayer wiring board made of the glass ceramic insulating layer 2 without warpage or deformation. As a result, the wiring board 1 is obtained.
【００３７】次に、凹部１ａならびに段差部１ｂを形成
するため、所望の深さおよび面積になるように所定のグ
リーンシートを金型により打ち抜き加工する。Next, in order to form the concave portion 1a and the step portion 1b, a predetermined green sheet is punched by a mold so as to have a desired depth and area.
【００３８】そして、以上のグリーンシートを所定の順
に積層し、これを熱圧着して一体化した後、約 900℃の
酸化雰囲気中においてピーク時間を約30分に設定して焼
成すると、目的とする配線基板１が得られる。After laminating the above green sheets in a predetermined order, integrating them by thermocompression bonding, and firing in an oxidizing atmosphere at about 900 ° C. with a peak time of about 30 minutes, Is obtained.
【００３９】このように、配線基板１がガラスセラミッ
クスから成るものであることから、アルミナ等のセラミ
ックス材料のような高温で焼成する必要がなく、低温で
焼成が可能なため安価であるとともに内部の導体配線パ
ターンには金系・銀系・銅系等の低融点で比抵抗の小さ
い金属材料を用いることができるので回路の高速信号処
理への対応が可能な半導体装置を提供することができ
た。As described above, since the wiring board 1 is made of glass ceramic, it is not necessary to fire at a high temperature such as a ceramic material such as alumina. Since a metal material having a low melting point and a low specific resistance, such as gold, silver, and copper, can be used for the conductor wiring pattern, a semiconductor device capable of responding to high-speed signal processing of a circuit was provided. .
【００４０】補助配線基板３は高熱伝導材料から成るも
のであり、半導体素子４を金属バンプ８を介して接続す
る、いわゆるフリップチップ実装法が可能な電極位置精
度および表面粗さを必要とし、例えば窒化アルミニウム
や金属あるいはホーロー基板といった高熱伝導率の材料
を用いて、凹部１ａの開口寸法とほぼ同じ寸法に形成さ
れる。また、所望の表面平滑性を有し、表面には半導体
素子４の表面の電極パターンに対応した導体膜が電極と
して形成され、内部にはこの電極と裏面の電極または表
面の周辺部の電極とを電気的に接続するためのビアホー
ルや導体膜パターン等の内部配線パターンが形成されて
いる。また、補助配線基板３と凹部１ａの段差部１ｂと
を封止材10にロウ材を用いてロウ付けする場合には、表
面の周辺部にはそのための導体膜パターンが形成され
る。The auxiliary wiring board 3 is made of a material having a high thermal conductivity, and requires an electrode position accuracy and a surface roughness capable of performing a so-called flip-chip mounting method for connecting the semiconductor elements 4 via the metal bumps 8. The recess 1a is formed to have substantially the same size as the opening of the concave portion 1a using a material having high thermal conductivity such as aluminum nitride, a metal, or an enamel substrate. Also, a conductor film having a desired surface smoothness and corresponding to the electrode pattern on the surface of the semiconductor element 4 is formed as an electrode on the surface, and this electrode and the electrode on the back surface or the electrode on the peripheral portion of the surface are formed inside. Internal wiring patterns, such as via holes and conductive film patterns, for electrically connecting the wirings. When the auxiliary wiring board 3 and the stepped portion 1b of the concave portion 1a are brazed to the sealing material 10 by using a brazing material, a conductor film pattern is formed around the periphery of the surface.
【００４１】補助配線基板３への半導体素子４の搭載
は、金属バンプ８を介して一般的なフリップチップ実装
法により行なわれ、例えば半導体素子４の表面の電極に
Ａｕスタッドバンプを形成し、精密な位置合わせ機構を
備えた半導体素子実装装置等を用いて熱圧着法あるいは
超音波接合法（サーモソニック法）等により補助配線基
板３の表面の電極と電気的に接続される。The mounting of the semiconductor element 4 on the auxiliary wiring board 3 is performed by a general flip-chip mounting method via the metal bump 8. For example, an Au stud bump is formed on an electrode on the surface of the semiconductor element 4, and precision mounting is performed. It is electrically connected to the electrodes on the surface of the auxiliary wiring substrate 3 by a thermocompression bonding method or an ultrasonic bonding method (thermosonic method) using a semiconductor device mounting apparatus or the like having a suitable alignment mechanism.
【００４２】なお、この状態で半導体素子４が補助配線
基板３に正確に実装されたかどうかを検査することによ
り接続信頼性上の欠陥の有無を確認でき、そのような欠
陥を後工程に持ち込むことなく的確な処置を行なうこと
が可能となり、部材の再利用や省資源化を図ることがで
きる。In this state, whether or not there is a defect in connection reliability can be confirmed by inspecting whether or not the semiconductor element 4 is correctly mounted on the auxiliary wiring board 3, and such a defect can be brought to a later process. It is possible to perform an accurate treatment without any problem, and it is possible to reuse members and save resources.
【００４３】複数個の熱伝導部材５の配置については、
図１に示した例の他にも、例えば凹部１ａの底面から裏
面導体層６（配線基板１の裏面）にわたってガラスセラ
ミックス絶縁層２を貫通して埋設された熱伝導部材５の
周囲に、途中の内層導体層７から裏面導体層６にわたる
補助熱伝導部材を埋設してもよい。また、内層導体層７
を少なくとも２層以上配するとともに、各内層導体層７
と裏面導体層６との間の補助熱伝導部材の個数を、裏面
導体層６側に向かって、かつ、補助熱伝導部材の埋設さ
れた領域の外側に向かって、階段状あるいはピラミッド
状に増加させて埋設してもよい。これらのような配置と
すれば、凹部１ａの底面から配線基板１の裏面に向かっ
て熱伝導部材５の周囲に次第に拡散するようにガラスセ
ラミックス絶縁層２を伝導していく半導体素子４からの
発熱をさらに効率良く裏面導体層６に伝導させることが
でき、半導体素子４からの発熱をさらに一層効率良く安
定して放熱させることができるものとなる。Regarding the arrangement of the plurality of heat conducting members 5,
In addition to the example shown in FIG. 1, for example, around the heat conductive member 5 embedded through the glass ceramic insulating layer 2 from the bottom surface of the concave portion 1a to the back surface conductor layer 6 (the back surface of the wiring board 1). An auxiliary heat conducting member extending from the inner conductor layer 7 to the back conductor layer 6 may be embedded. Also, the inner conductor layer 7
At least two layers, and each inner conductor layer 7
The number of auxiliary heat conducting members between the heat conductive member and the back conductor layer 6 is increased stepwise or pyramid toward the back conductor layer 6 and outside the region where the auxiliary heat conducting member is embedded. It may be buried. With such an arrangement, heat generated from the semiconductor element 4 is transmitted through the glass ceramic insulating layer 2 so as to gradually diffuse from the bottom surface of the concave portion 1a toward the back surface of the wiring board 1 toward the periphery of the heat conductive member 5. Can be more efficiently conducted to the back surface conductor layer 6, and the heat generated from the semiconductor element 4 can be more efficiently and stably radiated.
【００４４】さらに、熱伝導部材５の形状は、円柱状の
他にも角柱状や楕円柱状・板状等の種々の形状としても
よい。Further, the shape of the heat conducting member 5 may be various shapes such as a rectangular column, an elliptical column, and a plate in addition to the column.
【００４５】半導体素子４の裏面を凹部１ａの底面にロ
ウ付けするためのロウ材９としては、例えばＳｎ系半田
やＡｕ系半田等の軟ロウ材を用いればよい。また、ロウ
材９としてＡｕ−ＳｉまたはＡｕ−Ｓｎ・Ｐｂ−Ｓｎ等
の金属接合剤等の高熱伝導率材料を用いてもよい。これ
らのロウ材９を用いることにより、半導体素子４からの
熱を効率良く伝達することができる。なお、半導体素子
４をロウ付けする場合、半導体素子４の裏面には例えば
Ａｕ等の金属層を被着しておくことが、接続信頼性が高
められるという点から好ましい。As the brazing material 9 for brazing the back surface of the semiconductor element 4 to the bottom surface of the concave portion 1a, for example, a soft brazing material such as Sn-based solder or Au-based solder may be used. Further, as the brazing material 9, a high thermal conductivity material such as a metal bonding agent such as Au-Si or Au-Sn.Pb-Sn may be used. By using these brazing materials 9, heat from the semiconductor element 4 can be efficiently transmitted. When the semiconductor element 4 is brazed, it is preferable to attach a metal layer such as Au on the back surface of the semiconductor element 4 from the viewpoint of improving connection reliability.
【００４６】補助配線基板３を段差部１ｂに取着するた
めの封止材10としては、ロウ材９と同様の軟ロウ材を用
いればよい。これらの封止材10を用いることにより、半
導体素子４を良好に気密に封止することができる。As the sealing material 10 for attaching the auxiliary wiring board 3 to the step portion 1b, a soft brazing material similar to the brazing material 9 may be used. By using these sealing materials 10, the semiconductor element 4 can be satisfactorily hermetically sealed.
【００４７】封止樹脂14としては、例えばエポキシ樹脂
やシリコーン樹脂・フェノール樹脂等を用いることがで
きる。なお、補助配線基板３を段差部１ｂに搭載して取
着し、また封止樹脂14で封止する場合、これらを窒素等
の不活性ガス雰囲気中で行なうことが好ましく、それに
より信頼性を一層高めることができる。As the sealing resin 14, for example, epoxy resin, silicone resin, phenol resin or the like can be used. When the auxiliary wiring board 3 is mounted and attached to the stepped portion 1b and sealed with the sealing resin 14, it is preferable that these are performed in an atmosphere of an inert gas such as nitrogen, thereby improving reliability. Can be further enhanced.
【００４８】なお、本発明は以上の例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲で種々の変更
・改良を加えることは何ら差し支えない。It should be noted that the present invention is not limited to the above examples, and various changes and improvements can be made without departing from the scope of the present invention.
【００４９】[0049]
【発明の効果】以上のように、本発明の半導体装置によ
れば、半導体素子を配線基板の表面に形成した凹部の開
口とほぼ同じ寸法の高熱伝導材料から成る補助配線基板
に金属バンプを介して電気的に接続していわゆるフリッ
プチップ実装していることから、半導体素子の実装面積
の小型化を図ることができた。また、補助配線基板を凹
部の段差部に載置して封止材を介して接合し、かつ半導
体素子の裏面を複数個の熱伝導部材を有する凹部の底面
にロウ付けしたことから、半導体素子から発生する熱は
補助配線基板自体による放熱はもとより複数個の熱伝導
部材によっても効率良く伝導させて配線基板の裏面から
放熱させることが可能となり、優れた放熱効果を得るこ
とができた。その結果、半導体素子の温度上昇やそれに
よる悪影響を所望通りに抑制することができて、半導体
素子ならびに回路本来の性能を十分発揮させ、電子回路
モジュールとしての機能を十分に維持できる高信頼性の
半導体装置を提供することができた。As described above, according to the semiconductor device of the present invention, the semiconductor element is formed on the auxiliary wiring board made of a high heat conductive material having substantially the same size as the opening of the concave portion formed on the surface of the wiring board via the metal bump. Since they are electrically connected by flip-chip mounting, the mounting area of the semiconductor element can be reduced. Further, since the auxiliary wiring board is placed on the step of the concave portion and joined via a sealing material, and the back surface of the semiconductor device is brazed to the bottom surface of the concave portion having a plurality of heat conducting members, The heat generated from the substrate can be efficiently conducted not only by the auxiliary wiring board itself but also by a plurality of heat conducting members and can be radiated from the back surface of the wiring board, and an excellent heat dissipation effect can be obtained. As a result, the temperature rise of the semiconductor element and its adverse effects can be suppressed as desired, and the semiconductor element and the original performance of the circuit can be fully exhibited, and the high reliability which can sufficiently maintain the function as the electronic circuit module can be obtained. A semiconductor device can be provided.
【００５０】また、本発明の半導体装置によれば、配線
基板がガラスセラミックスから成るものであることか
ら、低温で焼成が可能なため安価であり、また内部の導
体配線パターンには金系・銀系・銅系等の低融点で比抵
抗の小さい金属材料を用いることができたので回路の高
速信号処理への対応が可能となった。Further, according to the semiconductor device of the present invention, since the wiring substrate is made of glass ceramic, it can be fired at a low temperature and thus is inexpensive. A low-melting-point, low-resistance metal material such as a copper-based material could be used, which enabled the circuit to be compatible with high-speed signal processing.
【００５１】さらに、本発明の半導体装置によれば、半
導体素子が搭載された補助配線基板が凹部の段差部に載
置されて取着されることから半導体素子を凹部内に収容
して気密に封止することができ、配線基板の表面に半導
体素子を直接搭載して樹脂封止したものよりも良好な封
止ができるので、極めて信頼性の高い半導体装置となっ
た。また、この補助配線基板を樹脂封止することにより
さらに信頼性を高めることができた。Further, according to the semiconductor device of the present invention, since the auxiliary wiring board on which the semiconductor element is mounted is mounted and mounted on the step of the recess, the semiconductor element is housed in the recess and airtight. The semiconductor device can be sealed, and can be sealed better than a semiconductor device directly mounted on a surface of a wiring substrate and sealed with a resin, so that a highly reliable semiconductor device can be obtained. Further, the reliability was further improved by sealing the auxiliary wiring substrate with resin.
【００５２】従って、本発明の半導体装置によれば、電
子回路モジュール等に使用される、安価な配線基板を用
いた半導体装置について、半導体素子からの発熱を効率
良く放熱させることができ、小型化・薄型化・高密度化
ならびに高速信号処理に対応した高機能化さらには低コ
スト化が可能な高信頼性の半導体装置を提供することが
できた。Therefore, according to the semiconductor device of the present invention, it is possible to efficiently radiate heat from the semiconductor element and reduce the size of the semiconductor device using an inexpensive wiring board used for an electronic circuit module or the like. -A highly reliable semiconductor device that can be thinned, has a high density, and has high functionality corresponding to high-speed signal processing and can be reduced in cost can be provided.
【００５３】さらにまた、本発明の半導体装置によれ
ば、半導体素子は補助配線基板に搭載され、この補助配
線基板は他の受動回路素子と同様に配線基板に搭載され
ることから、それら受動回路素子と同様に交換可能な構
造とすることができ、半導体素子や受動回路素子ひいて
は配線基板の再利用を図ることができる、省資源化の観
点から好ましいものとすることができた。Further, according to the semiconductor device of the present invention, the semiconductor element is mounted on the auxiliary wiring board, and this auxiliary wiring board is mounted on the wiring board like other passive circuit elements. The structure can be replaced similarly to the element, and the semiconductor element and the passive circuit element, and furthermore, the wiring board can be reused, which is preferable from the viewpoint of resource saving.
【図１】本発明の半導体装置の実施の形態の一例を示す
断面図である。FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置の実施の形態の一例を示す
平面図である。FIG. 2 is a plan view illustrating an example of an embodiment of a semiconductor device of the present invention.
１・・・・・配線基板 １ａ・・・・凹部 １ｂ・・・・段差部 ２・・・・・ガラスセラミックス絶縁層 ３・・・・・補助配線基板 ４・・・・・半導体素子 ５・・・・・熱伝導部材 ８・・・・・金属バンプ ９・・・・・ロウ材 10・・・・・封止材 11・・・・・補助配線基板の裏面の電極 12・・・・・配線基板の表面の電極 13・・・・・接続線 1... Wiring board 1a... Recess 1b... Stepped portion 2... Glass ceramic insulating layer 3... Auxiliary wiring board 4. ························································································································ .Electrode on the surface of the wiring board 13 ... Connection wire
Claims (1)
部を有する配線基板と、前記凹部の開口寸法とほぼ同じ
寸法の高熱伝導材料から成る補助配線基板と、該補助配
線基板の表面の電極に金属バンプを介して電気的に接続
された半導体素子とから成り、前記配線基板は凹部の開
口周辺に段差部を有するとともに凹部底面から裏面にか
けて複数個の熱伝導部材が埋設されており、前記半導体
素子の裏面を前記凹部の底面にロウ付けするとともに前
記補助配線基板を前記凹部の段差部に封止材を介して接
合させたことを特徴とする半導体装置。1. A wiring board made of glass ceramic and having a concave portion on the surface, an auxiliary wiring board made of a high heat conductive material having substantially the same dimension as an opening dimension of the concave portion, and a metal bump on an electrode on the surface of the auxiliary wiring substrate. The wiring board has a step around the opening of the recess and a plurality of heat conducting members are buried from the bottom to the back of the recess. A semiconductor device, wherein a back surface is brazed to a bottom surface of the concave portion, and the auxiliary wiring substrate is joined to a step portion of the concave portion via a sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25667596A JP3314139B2 (en) | 1996-09-27 | 1996-09-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25667596A JP3314139B2 (en) | 1996-09-27 | 1996-09-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10107188A true JPH10107188A (en) | 1998-04-24 |
| JP3314139B2 JP3314139B2 (en) | 2002-08-12 |
Family
ID=17295914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25667596A Expired - Fee Related JP3314139B2 (en) | 1996-09-27 | 1996-09-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3314139B2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586354U (en) * | 1978-12-11 | 1980-06-14 | ||
| JPS58187151U (en) * | 1982-06-08 | 1983-12-12 | 富士通株式会社 | High density package |
| JPH05129516A (en) * | 1991-11-01 | 1993-05-25 | Hitachi Ltd | Semiconductor device |
| JPH05275611A (en) * | 1992-03-30 | 1993-10-22 | Nec Corp | Multichip module |
| JPH06275739A (en) * | 1993-03-23 | 1994-09-30 | Sony Corp | Adaptor made of ceramics, and ceramic package |
-
1996
- 1996-09-27 JP JP25667596A patent/JP3314139B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586354U (en) * | 1978-12-11 | 1980-06-14 | ||
| JPS58187151U (en) * | 1982-06-08 | 1983-12-12 | 富士通株式会社 | High density package |
| JPH05129516A (en) * | 1991-11-01 | 1993-05-25 | Hitachi Ltd | Semiconductor device |
| JPH05275611A (en) * | 1992-03-30 | 1993-10-22 | Nec Corp | Multichip module |
| JPH06275739A (en) * | 1993-03-23 | 1994-09-30 | Sony Corp | Adaptor made of ceramics, and ceramic package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3314139B2 (en) | 2002-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900003828B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP3150351B2 (en) | Electronic device and method of manufacturing the same | |
| US5677575A (en) | Semiconductor package having semiconductor chip mounted on board in face-down relation | |
| JP3266505B2 (en) | Multilayer circuit board | |
| KR100632459B1 (en) | Heat-dissipating semiconductor package and manufacturing method | |
| JPH0964099A (en) | Semiconductor device and its mounting structure | |
| JP2008091714A (en) | Semiconductor device | |
| JP2003068931A (en) | Semiconductor package and its manufacturing method | |
| JP2573809B2 (en) | Multi-chip module with built-in electronic components | |
| JP2826049B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2000138317A (en) | Semiconductor device and its manufacture | |
| JP3460559B2 (en) | Semiconductor device and its manufacturing method, circuit board, and electronic equipment | |
| JP3312611B2 (en) | Film carrier type semiconductor device | |
| JP6626735B2 (en) | Electronic component mounting board, electronic device and electronic module | |
| JPH1197570A (en) | Semiconductor device manufacture thereof and packaging method therefor | |
| JP3652102B2 (en) | Electronic circuit module | |
| JP2007242908A (en) | Ceramic package for housing electronic components | |
| JP3314139B2 (en) | Semiconductor device | |
| JP2001102475A (en) | Package for semiconductor element and its mouning structure | |
| JP3660817B2 (en) | Electronic circuit module | |
| JP3024596B2 (en) | BGA type semiconductor device using film carrier tape | |
| JPH09330994A (en) | Semiconductor device | |
| JPH10256413A (en) | Semiconductor package | |
| JP2007042848A (en) | Wiring board, electric element device and compound board | |
| JPH0773110B2 (en) | Semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090531 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090531 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100531 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110531 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110531 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120531 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120531 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130531 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140531 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |