JPH05129516A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH05129516A
JPH05129516A JP28763591A JP28763591A JPH05129516A JP H05129516 A JPH05129516 A JP H05129516A JP 28763591 A JP28763591 A JP 28763591A JP 28763591 A JP28763591 A JP 28763591A JP H05129516 A JPH05129516 A JP H05129516A
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Prior art keywords
semiconductor pellet
semiconductor
pellet
circuit
semiconductor device
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Pending
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JP28763591A
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Japanese (ja)
Inventor
Yoshiaki Hanabusa
Motonori Kawaji
幹規 河路
善明 英
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Hitachi Ltd
株式会社日立製作所
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE: To enhance the mounting density of a semiconductor device by a method wherein one out of a first semiconductor pellet and a second semiconductor pellet is arranged inside the area occupied by the other out of them.
CONSTITUTION: A semiconductor pellet 1 and a semiconductor pellet 3 are electrically and mechanically connected respectively via bump electrodes 10; they are connected by a facedown system. The semiconductor pellet 3 is mounted on the side of a pellet mounting face on a base substrate 5 in a state that its element formation face is faced with the element formation face of the semiconductor pellet 1. That is to say, the semiconductor pellet 3 is arranged inside the area occupied by the semiconductor pellet 1 via the bump electrodes 10. Thereby, the mounting density (in the plane direction) of a semiconductor device can be enhanced by a portion corresponding to the area occupied by the semiconductor pellet 3.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体装置に関し、特に、ベース基板の実装面上に半導体ペレットが実装される半導体装置に適用して有効な技術に関するものである。 BACKGROUND OF THE INVENTION This invention relates to a semiconductor device, particularly, to a technique effectively applied to a semiconductor device in which a semiconductor pellet is mounted on the mounting surface of the base substrate.

【0002】 [0002]

【従来の技術】高い実装密度が得られる半導体装置として、フェースダウン方式を利用した半導体装置が知られている。 2. Description of the Related Art As a semiconductor device having a high mounting density is obtained, a semiconductor device is known using a face-down type. この種の半導体装置は、ベース基板のペレット塔載面上にフェースダウン方式で半導体ペレット(半導体集積回路装置)を実装し、この半導体ペレットを封止用キャップで封止する。 This type of semiconductor device, by mounting a semiconductor pellet (semiconductor integrated circuit device) in a face-down method on the base substrate pellet column Nomen, sealing the semiconductor pellet with a sealing cap. 半導体ペレットはベース基板及び封止用キャップで形成されるキャビティ内に封止される。 Semiconductor pellet is sealed in a cavity formed in the base substrate and the sealing cap. フェースダウン方式は、半導体ペレットの素子形成面側に形成された外部端子(ボンディングパッド)、ベース基板のペレット塔載面側に形成された電極の夫々を例えば半田を使用したバンプ電極(CCB電極、突起電極) Face-down scheme, the external terminals (bonding pads) formed on the element formation surface side of the semiconductor pellet, the bump electrodes (CCB electrodes using the respective example, solder electrode formed into pellets tower Nomen side of the base substrate, protruding electrodes)
で電気的及び機械的に接続する方式である。 In a method of electrically and mechanically connected. フェースダウン方式は、半導体ペレットの占有面積内においてベース基板に実装できるので、ボンディングワイヤ方式に比べて実装面積並びに信号伝達経路を縮小できる。 Face-down method, it is possible to mount on the base board in the area occupied by the semiconductor pellet can be reduced mounting area and the signal transduction pathway as compared with the bonding wire system.

【0003】本発明者が開発中のフェースダウン方式を利用する半導体装置は、モジュール基板、PCB基板等の実装基板の実装面上に複数個実装され、冷却装置で強制冷却される冷却システムに組込まれる。 [0003] The semiconductor device to which the present inventor utilizes a face-down type under development module substrate and a plurality mounted on a mounting surface of the mounting substrate such as a PCB substrate, incorporated into cooling systems forced cooling in the refrigerator It is. この半導体装置は、半導体ペレットの素子形成面と対向する裏面が熱伝導用充填材を介在して封止用キャップのペレット連結面(内壁)に連結され、半導体ペレットの素子形成面側に塔載された回路システムの動作で発生する熱を封止用キャップに伝導している。 The semiconductor device is coupled to the pellet connecting surface of the sealing cap back side that faces the element formation surface of the semiconductor pellet is interposed a thermally conductive filler (inner wall), the tower on the element formation surface side of the semiconductor pellet It is conducted to the sealing cap heat generated by operation of the the circuit system. 封止用キャップに伝導された熱はさらに冷却装置に伝導される。 The heat conducted to the sealing cap is further conducted to the cooling device. 熱伝導用充填材は熱伝導性が高い半田を使用する。 Thermally conductive filler uses a solder high thermal conductivity.

【0004】前記半導体ペレットに塔載される回路システムは、集積度(半導体装置の実装密度)を高める目的として、例えばバイポーラトランジスタ、相補型MIS [0004] circuit systems the tower on the semiconductor pellet, the purpose of increasing the degree of integration (packaging density of the semiconductor device), for example bipolar transistors, complementary MIS
FET等の多種類の能動素子を主体に構成される。 Composed many kinds of active elements such as FET mainly. バイポーラトランジスタは高い駆動能力が得られ、相補型M Bipolar transistor provides high drive capability, complementary M
ISFETは高い集積度や低消費電力化が得られる。 ISFET is high integration and low power consumption can be obtained. また、半導体ペレットに塔載される回路システムは、論理回路システム、記憶回路システム等の混合回路システムで構成される。 The circuit system is the tower on a semiconductor pellet, a logic circuit system, and a mixing circuit system such as a memory circuit system.

【0005】なお、前記フェースダウン方式を利用する半導体装置については、特開昭62−249429号公報に記載されている。 [0005] Incidentally, a semiconductor device utilizing the face-down method is described in JP-A-62-249429.

【0006】 [0006]

【発明が解決しようとする課題】本発明者は、前記フェースダウン方式を利用する半導体装置について検討した結果、以下の問題点を見出した。 THE INVENTION Problems to be Solved] The present inventor has studied a semiconductor device using the face-down method, and found the following problems.

【0007】前記半導体装置の半導体ペレットに塔載される回路システムは、バイポーラトランジスタ、相補型MISFET等の多種類の能動素子を主体に構成される。 [0007] circuit systems the tower to the semiconductor pellet of the semiconductor device is configured bipolar transistor, many kinds of active elements such as complementary MISFET mainly. このため、半導体ペレットは、異なるデバイスが混在し、単純に約2倍の製造プロセス数の増大となるので、半導体ペレットの歩留まりが低下し、結果的に半導体装置の歩留まりが低下する。 Therefore, semiconductor pellet, different devices are mixed, which requires a simple about twice the manufacturing number of processes increases, the yield of the semiconductor pellet is reduced, resulting in yield of the semiconductor device is lowered.

【0008】本発明の目的は、ベース基板の実装面上に半導体ペレットが実装される半導体装置において、実装密度を高めることが可能な技術を提供することにある。 An object of the present invention is to provide a semiconductor device a semiconductor pellet is mounted on the mounting surface of the base substrate, it is to provide a capable of enhancing the mounting density technology.

【0009】本発明の他の目的は、前記半導体装置の動作速度の高速化を図ることが可能な技術を提供することにある。 Another object of the present invention is to provide the operation speed faster can be achieved technology of the semiconductor device.

【0010】本発明の他の目的は、前記目的を達成すると共に、前記半導体装置の歩留まりを高めることが可能な技術を提供することにある。 Another object of the present invention is to achieve the above object, it is to provide a yield capable of enhancing the technology of the semiconductor device.

【0011】本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

【0012】 [0012]

【課題を解決するための手段】本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 Among the inventions disclosed in the present application Means for Solving the Problems] To briefly explain the summary of typical,
下記のとおりである。 It is as follows.

【0013】(1)ベース基板の実装面上に半導体ペレットが実装される半導体装置において、前記ベース基板の実装面上に単一能動素子を主体に構成される第1回路を有する第1半導体ペレットを塔載し、この第1半導体ペレットの第1回路上に、この第1回路の能動素子と異なる他の単一能動素子を主体に構成される第2回路を有する第2半導体ペレットを、その第2回路と第1半導体ペレットの第1回路とが対向する状態で塔載し、この第1 [0013] (1) In the semiconductor device in which a semiconductor pellet is mounted on a base substrate mounting surface on a first semiconductor pellet having a first circuit configured mainly of a single active element on the mounting surface of the base substrate were towers, a first circuit on the first semiconductor pellet, the second semiconductor pellet having a second circuit configured to single active element and active element different from other of the first circuit mainly, its and the tower in a state where the first circuit of the second circuit and the first semiconductor pellet faces, the first
半導体ペレットの第1回路、第2半導体ペレットの第2 The first circuit of the semiconductor pellet, the second semiconductor pellet second
回路の夫々をバンプ電極を介在して電気的に接続する。 Electrically connecting the respective circuit interposed bump electrodes.

【0014】(2)前記第1半導体ペレットの第1回路、 [0014] (2) the first circuit of the first semiconductor pellet,
第2半導体ペレットの第2回路の夫々は、前記ベース基板側から夫々独立に電源が供給される。 Each of the second circuit of the second semiconductor pellet, power each independently supplied from the base substrate side.

【0015】(3)前記第1半導体ペレットの第1回路、 [0015] (3) the first circuit of the first semiconductor pellet,
第2半導体ペレットの第2回路のうち、回路動作で発生する熱量が大きい一方を、発生する熱量が小さい他方に比べて、冷却システムに近づけてベース基板の実装面上に塔載する。 Of the second circuit of the second semiconductor pellet, one amount of heat generated in the circuit operation is larger, than the other heat generated is small, and the tower on the mounting surface of the base substrate close to the cooling system.

【0016】 [0016]

【作用】上述した手段(1)によれば、第1半導体ペレット、第2半導体ペレットのうち、いずれか一方の占有面積内に他方を配置したので、この他方の占有面積に相当する分、半導体装置の実装密度を向上できる。 SUMMARY OF] According to the above means (1), first semiconductor pellet, of the second semiconductor pellet, since the place of the other in one of the occupied within the area, an amount corresponding to the area occupied by the other, a semiconductor mounting density of devices can be improved.

【0017】また、第1半導体ペレットの第1回路、第2半導体ペレットの第2回路の夫々をバンプ電極を介在して最短距離で電気的に接続したので、ワイヤボンディング方式でボンディングされたワイヤを介在する場合に比べて信号伝達径路を短くでき、半導体装置の動作速度の高速化を図ることができる。 Further, the first circuit of the first semiconductor pellet, since the respective second circuit of the second semiconductor pellet is electrically connected with the shortest distance interposed bump electrodes, the bonded wires by wire bonding method can shorten the signal transmission path as compared with the case of intervening, it is possible to increase the operation speed of the semiconductor device.

【0018】また、第1半導体ペレットの第1回路、第2半導体ペレットの第2回路の夫々に塔載される能動素子を相互に異なる最適かつ独立な製造プロセスで形成できるので、多種類の能動素子を1つの半導体ペレットに混在して形成する場合に比べて、第1半導体ペレット、 Further, the first circuit of the first semiconductor pellet, because the active element is the tower in each of the second circuit of the second semiconductor pellet can be formed mutually in different optimal and independent manufacturing processes, many kinds of active as compared with the case of forming a mix of elements in a single semiconductor pellet, the first semiconductor pellet,
第2半導体ペレットの夫々の製造プロセスを低減し、夫々の製造プロセスでの歩留まりを向上でき、結果的に最終的な半導体装置の歩留まりを向上できる。 Reducing the respective manufacturing processes of the second semiconductor pellet, it can improve the yield of the manufacturing process of each can consequently improve the yield of the final semiconductor device.

【0019】上述した手段(2)によれば、第1半導体ペレットの第1回路、第2半導体ペレットの第2回路の夫々の動作時に生じる電源ノイズを吸収できるので、夫々の回路の動作速度を速め、半導体装置の動作速度の高速化を図ることができる。 According to the above-mentioned means (2), the first circuit of the first semiconductor pellet, can be absorbed power supply noise generated when each of the operation of the second circuit of the second semiconductor pellet, the operating speed of the respective circuits faster, it is possible to increase the operation speed of the semiconductor device.

【0020】上述した手段(3)によれば、第1半導体ペレットの第1回路、第2半導体ペレットの第2回路のうち、回路動作で発生する熱量の大きい半導体ペレットを冷却システムで冷却でき、この半導体ペレットの放熱効率を高められるので、半導体ペレットの誤動作を防止し、半導体装置の信頼性を向上できる。 According to the above-mentioned means (3), the first circuit of the first semiconductor pellet, of the second circuit of the second semiconductor pellets can cool the large semiconductor pellet heat generated by the circuit operating in the cooling system, because enhanced heat dissipation efficiency of the semiconductor pellet, and prevent malfunction of the semiconductor pellet, it is possible to improve the reliability of the semiconductor device.

【0021】以下、本発明の構成について、フェースダウン方式を利用する半導体装置に本発明を適用した一実施例とともに説明する。 [0021] Hereinafter, the configuration of the present invention will be described with an example in which the present invention is applied to a semiconductor device utilizing a face-down type.

【0022】なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。 [0022] Incidentally, in all drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.

【0023】 [0023]

【実施例】本発明の一実施例であるフェースダウン方式を利用する半導体装置の概略構成を図1(断面図)で示す。 The schematic structure of a semiconductor device utilizing a face-down type, which is an embodiment of the embodiment of the present invention shown in FIG. 1 (sectional view).

【0024】図1に示すように、本発明の一実施例であるフェースダウン方式を利用する半導体装置は、ベース基板5のペレット塔載面(実装面)側に半導体ペレット1、半導体ペレット3の夫々を塔載し、この半導体ペレット1、半導体ペレット3の夫々を封止用キャップ11 As shown in FIG. 1, a semiconductor device utilizing a face-down method according to an embodiment of the present invention, the base substrate 5 semiconductor pellet 1 to the pellet column Nomen (mounting surface) side, of the semiconductor pellet 3 respectively and towers, the semiconductor pellet 1, the sealing cap 11 respectively of the semiconductor pellet 3
で封止する。 In sealed.

【0025】前記半導体ペレット1は、例えば単結晶珪素からなる半導体基板を主体に構成され、その素子形成面(図1中下面)に例えば論理回路システムを塔載している。 [0025] The semiconductor pellet 1, for example a semiconductor substrate made of single-crystal silicon is mainly composed, and the tower, for example, a logic circuit system that element formation surface (lower surface in FIG. 1). この論理回路システムは、例えば高い駆動能力が得られるバイポーラトランジスタを主体に構成され、単一能動素子で構成される。 The logic system is mainly composed of bipolar transistors are obtained such as high driving capability, and a single active element. 半導体ペレット1の素子形成面側には外部端子(ボンディングパッド)2が複数個配列される。 The element formation surface side of the semiconductor pellet 1 is an external terminal (bonding pad) 2 is a plurality sequences. この外部端子2は、前記論理回路システムを構成するバイポーラトランジスタ間を接続する配線層のうち最上層の配線層で形成され、例えばアルミニウム合金膜で形成される。 The external terminal 2, the formed by the uppermost wiring layer among the wiring layers for connecting the bipolar transistor constituting a logic circuit system is formed, for example, an aluminum alloy film. 半導体ペレット1は、単一能動素子(バイポーラトランジスタ)で論理回路システムを構成しているので、多種類の能動素子(例えばバイポーラトランジスタ、MISFET等)で論理回路システムを構成する場合に比べて製造プロセス数を低減でき、最適な製造プロセスで形成できる。 Semiconductor pellet 1, so constitute a logic circuit system with a single active element (bipolar transistor), many types of active devices (e.g. a bipolar transistor, MISFET, etc.) fabrication process as compared with the case where the logic circuit system can reduce the number it can be formed in an optimal manufacturing processes.

【0026】前記半導体ペレット3は、例えば単結晶珪素からなる半導体基板を主体に構成され、その素子形成面(図1中上面)に例えば記憶回路システムを塔載している。 [0026] The semiconductor pellet 3, for example, a semiconductor substrate made of single-crystal silicon is mainly composed, and the tower, for example, a memory circuit system that element forming surface (in FIG. 1 top). この記憶回路システムは、例えば高い集積度や低消費電力化が得られる相補型MISFET(CMOS)を主体に構成され、単一能動素子で構成される。 The memory circuit system, for example, high integration and low power consumption is mainly composed of complementary MISFET (CMOS) obtained, consisting of a single active element. 半導体ペレット3の素子形成面側には外部端子(ボンディングパッド)4が複数個配列される。 The element formation surface side of the semiconductor pellet 3 external terminals (bonding pads) 4 are a plurality sequences. この外部端子4は、前記記憶回路システムを構成する相補型MISFET間を接続する配線層のうち最上層の配線層で形成され、例えばアルミニウム合金膜で形成される。 The external terminal 4, the formed by the uppermost wiring layer among the storage circuit wiring layer for connecting the complementary MISFET composing the system is formed, for example, an aluminum alloy film. 半導体ペレット3は、 Semiconductor pellet 3,
単一能動素子(相補型MISFET)で記憶回路システムを構成しているので、多種類の能動素子で記憶回路システムを構成する場合に比べて製造プロセス数を低減でき、最適な製造プロセスで形成できる。 Since constitute a storage circuit system with a single active element (complementary MISFET), can reduce the number of manufacturing processes as compared with the case of configuring the memory circuit system in various types of active elements may be formed in an optimal manufacturing process .

【0027】前記ベース基板5は、例えばムライトで形成され、図示していないが多層配線構造で構成される。 [0027] The base substrate 5 is formed of, for example, mullite, although not shown composed of a multilayer wiring structure.
ベース基板5のペレット塔載面の中央部には凹部7が形成され、この凹部7内には前記半導体ペレット3が配置される。 The central portion of the pellet column Nomen of the base substrate 5 recess 7 is formed, the semiconductor pellet 3 is disposed in the recess 7. つまり、凹部7の開口サイズは半導体ペレット3の平面形状に比べてひとまわり大きなサイズで形成され、凹部7の底面の位置はベース基板5のペレット塔載面の位置よりも低く構成される。 In other words, the opening size of the concave portion 7 is formed with a larger size slightly as compared to the planar shape of the semiconductor pellet 3, the position of the bottom surface of the recess 7 is comprised lower than the position of the pellet column mounting surface of the base substrate 5. ベース基板5のペレット塔載面上には凹部7の周囲の領域において電極6が複数個配列され、ベース基板5のペレット塔載面と対向する裏面には電極9が複数個配列される。 Electrode 6 around the region of the recess 7 on the pellet column Nomen of the base substrate 5 are a plurality sequences, the back surface facing the pellets column Nomen base substrate 5 electrodes 9 are a plurality sequences. この電極6、電極9の夫々は前記多層配線構造の配線を介して電気的に接続される。 The electrodes 6, each of the electrodes 9 s are electrically connected through the wiring of the multilayer wiring structure.

【0028】前記ベース基板5の電極6、半導体ペレット1の外部端子2の夫々の間にはバンプ電極(CCB電極、突起電極)10が介在される。 [0028] The base electrode 6 of the substrate 5, the bump electrodes (CCB electrodes, protruding electrodes) between the respective external terminals 2 of the semiconductor pellet 1 10 is interposed. つまり、ベース基板5、半導体ペレット1の夫々は、バンプ電極10を介在して電気的及び機械的に接続され、フェースダウン方式で接続される。 That is, the base substrate 5, the respective semiconductor pellet 1 are electrically and mechanically connected by interposition of bump electrodes 10, are connected in a face-down method. 半導体ペレット1はバンプ電極10を介在してベース基板5のペレット塔載面上に実装される。 Semiconductor pellet 1 is mounted on the pellet column Nomen of the base substrate 5 by interposing the bump electrode 10.
つまり、半導体ペレット1はベース基板5の専有面積内に配置される。 That is, the semiconductor pellet 1 is placed within the footprint of the base substrate 5.

【0029】前記半導体ペレット1の外部端子2、半導体ペレット3の外部端子4の夫々の間にはバンプ電極1 [0029] The semiconductor external terminal 2 of the pellet 1, the bump electrodes 1 between the respective external terminals 4 of the semiconductor pellet 3
0が介在される。 0 is interposed. つまり、半導体ペレット1、半導体ペレット3の夫々は、バンプ電極10を介在して電気的及び機械的に接続され、フェースダウン方式で接続される。 That is, the semiconductor pellet 1, the respective semiconductor pellet 3 is electrically and mechanically connected by interposition of bump electrodes 10, are connected in a face-down method. 半導体ペレット3は、その素子形成面が半導体ペレット1の素子形成面と対向する状態でベース基板5のペレット塔載面側に塔載され、半導体ペレット1の素子形成面上に塔載される。 Semiconductor pellet 3, the element formation surface is the tower pelleted tower Nomen side of the base substrate 5 in a state facing the element formation surface of the semiconductor pellet 1 is the tower on the element formation surface of the semiconductor pellet 1. つまり、半導体ペレット3はバンプ電極10を介在して半導体ペレット1の占有面積内に配置されるので、この半導体ペレット3の専有面積内に相当する分、半導体装置の実装密度(平面方向)を向上できる。 That is, since the semiconductor pellet 3 is located within the area occupied by the semiconductor pellet 1 by interposing the bump electrode 10, the amount corresponding to the footprint of the semiconductor pellet 3, improving the packaging density of the semiconductor device (planar direction) it can. また、半導体ペレット1の論理回路システム、 Further, the semiconductor pellet 1 of a logic circuit system,
半導体ペレット2の記憶回路システムの夫々は、バンプ電極10を介在して最短距離で電気的に接続されるので、ワイヤーボンディング方式でボンディングされたワイヤを介在する場合に比ベて信号伝達経路を短くでき、 Each of the semiconductor pellet 2 of the memory circuit system, since it is electrically connected with the shortest distance interposed bump electrode 10, shortening the signal transmission path Te obtained comparing to the case of interposing the wires are bonded by a wire bonding method can,
半導体装置の動作速度の高速化を図ることができる。 It is possible to speed up the operating speed of the semiconductor device. 前記バンプ電極10は、温度階層の最っとも高い温度に位置する半田材料で形成される。 The bump electrode 10 is formed of a solder material positioned in the outermost Innovation temperature higher temperatures hierarchy.

【0030】前記封止用キャップ11は、断面形状がコの字形状に形成され、ベース基板5とで半導体ペレット1、半導体ペレット3の夫々を収納しかつ気密封止するキャビティを構成する。 [0030] The sealing cap 11, the cross-sectional shape is formed in U-shape, the semiconductor pellet 1 with a base substrate 5, housing a respective semiconductor pellet 3 and constituting the cavity to hermetically seal. 封止用キャップ11は熱伝導性の良好な例えば窒化アルミニウムで形成される。 Sealing cap 11 is formed of a good thermal conductivity such as aluminum nitride.

【0031】前記封止用キャップ11のペレット連結面 [0031] Pellets coupling surface of the sealing cap 11
(内壁)は熱伝導用充填材12を介在して半導体ペレット1の素子形面と対向する裏面に連結される。 (Inner wall) is connected to the rear surface opposite to the element shape surface of the semiconductor pellet 1 by interposing a filler material 12 for thermal conduction. 熱伝導用充填材12は、両者間をほぼ完全に密着し、半導体ペレット1の素子形面に塔載された論理回路システムの動作で発生する熱を封止用キャップ11に高い効率で伝達できる。 Thermally conductive filler 12 is in close contact between each other almost completely, the heat generated by the operation of the logic circuit system is the tower on the element shape surface of the semiconductor pellet 1 can be transmitted with high efficiency in the sealing cap 11 . この熱伝導用充填材12は、前記バンプ電極10に比べて融点が低い半田材料で形成される。 The thermally conductive filler 12 has a melting point as compared with the bump electrode 10 is formed at a lower solder material.

【0032】前記封止用キャップ12は、半導体ペレット1の周囲において、封止材13によりベース基板5に接着される。 [0032] The sealing cap 12, in the periphery of the semiconductor pellet 1 is bonded to the base substrate 5 with a plug 13. 封止材13は、半導体ペレット1の裏面に熱伝導用充填材12を介在して封止用キャップ11のペレット連結面を連結する際、熱伝導用充填材12の一部を封止用キャップ11とベース基板5との接着領域に流し込んだ熱伝導用充填材12で構成される。 Sealing member 13, when connecting the pellet connecting surface of the sealing cap 11 by interposing a heat conductive filler 12 to the back surface of the semiconductor pellet 1, the sealing cap a portion of the thermally conductive filler 12 11 and consists of a thermally conductive filler material 12 poured into the adhesion area of ​​the base substrate 5. 前記ベース基板5及び封止用キャップ11で形成され、封止材13 Formed in the base substrate 5 and the sealing cap 11, sealing member 13
で気密封止されるキャビティ内部には、組立プロセス中での封止工程で使用されるガスが充填される。 In the internal cavity is hermetically sealed, the gas used is filled with a sealing step in the assembly process.

【0033】図2(図1に示す半導体装置の要部拡大断面図)に示すように、前記半導体ペレット1の外部端子2のうち、外部端子2Aは、バンプ電極10、ベース基板5の電極6の夫々を介在してベース基板5の多層配線構造の配線8Aの一方に電気的に接続される。 As shown in FIG. 2 (enlarged sectional view of the semiconductor device shown in FIG. 1), wherein one of the external terminals 2 of the semiconductor pellet 1, the external terminal 2A is bump electrodes 10, the electrode 6 of the base substrate 5 intervening each being electrically connected to one of the wiring 8A of the multilayer wiring structure of the base substrate 5. 配線8A Wiring 8A
の他方はベース基板5の電極9に接続される。 The other is connected to the electrode 9 of the base substrate 5. この電極9には電源が印加され、配線8A、電極6、バンプ電極10及び外部端子2Aを通して半導体ペレット1の論理回路システムに供給される。 The power is applied to the electrode 9, the wiring 8A, electrodes 6 are supplied to a logic circuit system of the semiconductor pellet 1 through the bump electrode 10 and the external terminal 2A.

【0034】前記外部端子2のうち、外部端子2B1は隣接する外部端子2B2と一体に構成される。 [0034] Among the external terminals 2, the external terminals 2B1 are formed integrally with the external terminal 2B2 adjacent. この外部端子2B1、外部端子2B2の夫々は、半導体ペレット1の論理回路システムに接続されない所謂ダミーパッドとして構成される。 The external terminals 2B1, Each of the external terminals 2B2, configured as a so-called dummy pads which are not connected to the logic circuit system of the semiconductor pellet 1. 外部端子2B2は、バンプ電極10 External terminals 2B2 are bump electrodes 10
を介在して半導体ペレット3の外部端子4に電気的に接続される。 Interposed a is electrically connected to an external terminal 4 of the semiconductor pellet 3. 外部端子2B1は、バンプ電極10、ベース基板5の電極6の夫々を介在してベース基板5の多層配線構造の配線8Bの一方に接続される。 External terminals 2B1 are bump electrodes 10, are connected to one wiring 8B of the multilayer wiring structure of the base substrate 5 by interposing the respective electrodes 6 of the base substrate 5. 配線8Bの他方はベース基板5の電極9に接続される。 Other wiring 8B is connected to the electrode 9 of the base substrate 5. この電極9には電源が印加され、配線8B、電極6、バンプ電極10、 The power is applied to the electrode 9, the wiring 8B, electrodes 6, the bump electrode 10,
外部端子2B1、2B2、バンプ電極10及び外部端子4を通して半導体ペレット3の記憶回路システムに供給される。 External terminals 2B1 and 2B2, is supplied to the memory circuit system of the semiconductor pellet 3 through the bump electrode 10 and the external terminals 4. つまり、半導体ペレット1、半導体ペレット2 That is, the semiconductor pellet 1, the semiconductor pellet 2
の夫々にはベース基板5の配線8A、配線8Bの夫々で独立に電源が供給され、半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムの夫々の動作時に生じる電源ノイズを吸収し易いように構成される。 Each in the base substrate 5 wiring 8A, power is supplied independently in each of the lines 8B, the logic circuit system of the semiconductor pellet 1 is easy to absorb power supply noise generated at the time of each operation of the memory circuit system of the semiconductor pellet 3 configured.

【0035】このように構成される半導体装置は、図3 [0035] Thus constructed semiconductor device, FIG. 3
(システム構成図)に示すように、フェースダウン方式で冷却システム20の実装基板(モジュール基板又はPC As shown in (a system configuration diagram), the mounting substrate of the cooling system 20 by face-down type (module substrate or PC
B基板)23の実装面上に1個或は複数個実装される。 1 or is a plurality mounted on the mounting surface of the substrate B) 23.
つまり、半導体装置は、そのベース基板5の電極9にバンプ電極25を介在して実装基板23の電極24に電気的及び機械的に接続することにより実装基板23に実装される。 That is, the semiconductor device is mounted on the mounting board 23 by electrically and mechanically connected to the electrode 24 of the mounting substrate 23 by interposing the bump electrode 25 to the electrode 9 of the base substrate 5. この半導体装置は、実装基板23及び封止用キャップ22で形成されるキャビティ内部に封止される。 The semiconductor device is sealed within a cavity formed in the mounting substrate 23 and the sealing cap 22.
封止用キャップ22は封止材27により実装基板23に接着される。 Sealing cap 22 is bonded to the mounting board 23 with a plug 27. 冷却システム20の実装基板23は、前記半導体装置のベース基板5と同様に多層配線構造で構成される。 The mounting substrate 23 of the cooling system 20 is composed of a multilayer wiring structure like the base substrate 5 of the semiconductor device.

【0036】前記半導体装置の封止用キャップ11の上側表面上にはクシ歯形状で形成される放熱フィン21が構成される。 The fins 21 that are on the upper surface are formed in comb teeth shape of the sealing cap 11 of the semiconductor device is formed. この放熱フィン21は熱伝導用充填材1 The fins 21 of the filler 1 heat conductivity
2、封止用キャップ11の夫々を通して伝導される、半導体ペレット1に塔載された論理回路システムの動作で発生する熱を冷却システム20側に放熱する目的で構成される。 2, is conducted through each of the sealing cap 11, and the purpose of the heat generated by the operation of the tower logical circuit system in the semiconductor pellet 1 is radiated to the cooling system 20 side.

【0037】前記封止用キャップ22は例えば窒化アルミニウムで構成される。 [0037] The sealing cap 22 is made of, for example, aluminum nitride. この封止用キャップ22は、前記放熱フィン21と接触するクシ歯22Aが構成され、 The sealing cap 22, comb teeth 22A in contact with the fins 21 are configured,
放熱フィン21を通して伝導される熱を上部に配置された水冷ジャケット26に放出する。 Releasing heat that is conducted through the fins 21 to the cooling jacket 26 disposed in the upper portion. この水冷ジャケット26には複数個の冷却用水管26Aが構成され、この冷却用水管26A内には冷却水が循環する。 The a plurality of cooling water pipes 26A are configured to water-cooling jacket 26, the cooling water circulates in the cooling water pipe 26A. 前述の放熱フィン21から封止用キャップ22に伝導される熱は、この水冷ジャケット26の冷却用水管26A内を循環する冷却水に伝達され、冷却システム20の外部に放出される。 Heat conducted from the heat radiating fins 21 of the aforementioned sealing cap 22 is transmitted to the cooling water circulating in the cooling water pipe 26A of the water-cooling jacket 26 is discharged to the outside of the cooling system 20.

【0038】前記半導体装置は、冷却システム20側に半導体ペレット1を配置している。 [0038] The semiconductor device is arranged semiconductor pellet 1 to the cooling system 20 side. この半導体ペレット1は、相補型MISFETに比べて消費電力が高い、つまり発熱量が大きいバイポーラトランジスタで構成された論理回路システムを塔載している。 The semiconductor pellet 1, the power consumption than complementary MISFET is high, that is, to the tower a logic circuit system composed of the calorific value is large bipolar transistor. この論理回路システムの動作で発生する熱は、半導体ペレット1の裏面から熱伝導用充填材12を通して封止型キャップ11に効率的に伝導され、封止用キャップ11に伝導された熱は、放熱フィン21を通して効率的に冷却システム20 Heat generated by operation of the logic circuit system, efficiently conducted to the sealed type cap 11 through the heat conductive filler 12 from the back surface of the semiconductor pellet 1, the heat transferred to the sealing cap 11, the heat radiation efficient cooling system through fins 21 20
に伝導される。 It is conducted to.

【0039】このように、ベース基板5のペレット塔載面(実装面)上に半導体ペレットが実装される半導体装置において、前記ベース基板5のペレット塔載面上にバイポーラトランジスタ(単一能動素子)を主体に構成される論理回路システムを有する半導体ペレット1を塔載し、 [0039] Thus, the base substrate 5 pellet column Nomen in the semiconductor device a semiconductor pellet is mounted on (mounting surface), a bipolar transistor on the pellet column Nomen of the base substrate 5 (single active element) and the tower of the semiconductor pellet 1 having a logic circuit system configured to mainly,
この半導体ペレット1の論理回路システム上に、この論理回路システムのバイポーラトランジスタと異なる相補型MISFET(単一能動素子)を主体に構成される記憶回路システムを有する半導体ペレット3を、その記憶回路システムと半導体ペレット1の論理回路システムとが対向する状態で塔載し、前記半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムの夫々をバンプ電極10を介在して電気的に接続する。 On the semiconductor pellet 1 of a logic circuit system, the semiconductor pellet 3 having a memory circuit system configured to mainly complementary MISFET differs from the bipolar transistor of the logic circuit system (single active element), and the storage circuit system and the tower in a state in which a logic circuit system of the semiconductor pellet 1 is opposed, the semiconductor pellet 1 of a logic circuit system, electrically connecting the s husband storage circuit system of the semiconductor pellet 3 interposed bump electrode 10. この構成により、半導体ペレット1の占有面積内に半導体ペレット3を配置したので、この半導体ペレット3の占有面積に相当する分、半導体装置の実装密度を向上することができる。 With this configuration, since the arrangement of the semiconductor pellet 3 within the area occupied by the semiconductor pellet 1, an amount corresponding to the area occupied by the semiconductor pellet 3, it is possible to improve the mounting density of the semiconductor device.

【0040】また、半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムの夫々をバンプ電極10を介在して最短距離で電気的に接続したので、ワイヤボンディング方式でボンディングされたワイヤを介在する場合に比べて信号伝達経路を短くでき、半導体装置の動作速度の高速化を図ることができる。 Further, the logic circuit system of the semiconductor pellet 1, since the people each memory circuit system of the semiconductor pellet 3 and electrically connected with the shortest distance interposed bump electrodes 10, interposed bonded wires by wire bonding method to be short signal transmission path as compared with the case, it is possible to increase the operation speed of the semiconductor device.

【0041】また、半導体ペレット1の論理回路システムを構成するバイポーラトランジスタ、半導体ペレット3の記憶回路システムを構成する相補型MISFETの夫々を相互に異なる最適かつ独立な製造プロセスで形成でき、多種類の能動素子(バイポーラトランジスタ、相補型MISFET)を1つの半導体ペレットに混在して形成する場合に比べて、半導体ペレット1、半導体ペレット3の夫々の製造プロセス数を低減できるので、夫々の製造プロセスでの歩留まりを向上でき、結果的に最終的な半導体装置の歩留まりを向上できる。 Further, bipolar transistors constituting a logic circuit system of the semiconductor pellet 1, the respective complementary MISFET constituting the storage circuit system of the semiconductor pellet 3 can formed mutually in different optimal and independent manufacturing processes, many kinds of active element (bipolar transistor, complementary MISFET) as compared with the case of forming a mix of a single semiconductor pellet, the semiconductor pellet 1, it is possible to reduce the number of manufacturing processes of each of the semiconductor pellet 3, each of the manufacturing process can improve the yield, it can result in improved yield of the final semiconductor device.

【0042】また、前記半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムの夫々は、前記ベース基板5の配線8A、配線8Bの夫々から独立に電源が供給される。 Further, the semiconductor pellet 1 of a logic circuit system, each of the storage circuit system of the semiconductor pellet 3, the base substrate 5 wiring 8A, power is supplied independently from the respective wire 8B. この構成により、半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムの夫々の動作時に生じる電源ノイズを吸収できるので、夫々の回路の動作速度を速め、半導体装置の動作速度の高速化をより図ることができる。 With this configuration, the logic circuit system of the semiconductor pellet 1, it is possible to absorb the power supply noise generated during operation of each of the memory circuit system of the semiconductor pellet 3, accelerate the operating speed of the respective circuits, the operation speed of the semiconductor device it is possible to achieve more.

【0043】また、前記半導体ペレット1の論理回路システム、半導体ペレット3の記憶回路システムのうち、 [0043] In addition, the semiconductor pellet 1 of a logic circuit system, among the storage circuit system of the semiconductor pellet 3,
高い駆動能力が得られる(発熱量が大きい)バイポーラトランジスタで構成された論理回路システムを有する半導体ペレット1を、低消費電力化が得られる(発熱量が小さい)相補型MISFETで構成された記憶回路システムを有する半導体ペレット3に比ベて、冷却システム2 High driving capability can be obtained (a large heat generation amount) of the semiconductor pellet 1 having a logic circuit system composed of bipolar transistors, power consumption can be obtained (heat generation amount is small) configured memory circuit in complementary MISFET the semiconductor pellet 3 to have a system Te obtained comparing, the cooling system 2
0に近づけてベース基板5のペレット塔載面上に塔載する。 Close to 0 to the tower on the pellet tower Nomen of the base substrate 5. この構成により、回路動作で発生する熱量の大きい半導体ペレット1を冷却システム20で冷却でき、この半導体ペレット1の放熱効率を高められるので、半導体ペレット1の誤動作を防止し、半導体装置の信頼性を向上できる。 With this configuration, a large semiconductor pellet 1 of the amount of heat generated by the circuit operation can be cooled in a cooling system 20, since it is improved heat dissipation efficiency of the semiconductor pellet 1, and prevent malfunction of the semiconductor pellet 1, the reliability of the semiconductor device It can be improved.

【0044】なお、本実施例では、半導体ペレット1、 [0044] In the present embodiment, the semiconductor pellet 1,
半導体ペレット3の夫々を単晶珪素基板で構成したが、 The each of the semiconductor pellet 3 was composed of a monocrystalline silicon substrate,
このどちらか一方を例えばGaAs(ガリウム・砒素)からなる半絶縁性基板で構成し、多機能化を高めてもよい。 This either constitutes one example a semi-insulating substrate made of GaAs (gallium arsenide), may be increased multiple functions.

【0045】また、半導体ペレット1、半導体ペレット2のうちどちらか一方の半導体ペレットを他方の半導体ペレットの補修用として構成してもよい。 Further, the semiconductor pellet 1, either one of the semiconductor pellet of the semiconductor pellet 2 may be configured for repair of other semiconductor pellet.

【0046】以上、本発明者によってなされた発明を、 [0046] As described above, the invention made by the inventors of the present invention,
前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。 Has been specifically described based on the embodiments, the present invention is not the be construed as limited to the embodiments, it is needless to say that various changes can be made without departing from the spirit thereof.

【0047】 [0047]

【発明の効果】本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。 To briefly explain advantageous effects obtained by typical ones of the inventions disclosed in the present application, according to the present invention, it is as follows.

【0048】ベース基板の実装面上に半導体ペレットが実装される半導体装置において、実装密度を向上できる。 [0048] In the semiconductor device in which a semiconductor pellet is mounted on the base board of the mounting surface, thereby improving the mounting density.

【0049】また、前記半導体装置の動作速度の高速化を図ることができる。 [0049] Further, it is possible to increase the operation speed of the semiconductor device.

【0050】また、前記半導体装置の歩留まりを向上できる。 [0050] Further, it is possible to improve the yield of the semiconductor device.

【0051】また、前記半導体装置の動作速度の高速化をより図ることができる。 [0051] Further, it is possible to further the operation speed of the semiconductor device.

【0052】また、前記半導体装置の誤動作を防止できる。 [0052] Further, it is possible to prevent the malfunction of the semiconductor device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の一実施例である半導体装置の断面図。 Sectional view of a semiconductor device in an embodiment of the present invention; FIG.

【図2】 前記半導体装置の要部拡大断面図。 [Figure 2] enlarged sectional view of the semiconductor device.

【図3】 前記半導体装置を冷却システムに組込んだシステム構成図。 [3] The system configuration diagram incorporating the semiconductor device in the cooling system.

【符号の説明】 DESCRIPTION OF SYMBOLS

1…半導体ペレット、2…外部端子、3…半導体ペット、4…外部端子、5…ベース基板、6…電極、7…凹部、8A,8B…配線、9…電極、10…バンプ電極、 1 ... semiconductor pellet, 2 ... external terminal, 3 ... semiconductor pets, 4 ... external terminal, 5 ... base substrate, 6 ... electrode 7 ... recess, 8A, 8B ... wire, 9 ... electrode, 10 ... bump electrodes,
11…封止用キャップ、12…熱伝導用充填材、13… 11 ... sealing cap 12 ... heat conductive filler, 13 ...
封止材、20…冷却システム、21…放熱フィン、22 Sealing material, 20 ... cooling system, 21 ... radiator fins 22
…封止用キャップ、23…実装基板。 ... sealing cap, 23 ... mounting board.

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 ベース基板の実装面上に半導体ペレットが実装される半導体装置において、前記ベース基板の実装面上に単一能動素子を主体に構成される第1回路を有する第1半導体ペレットを塔載し、この第1半導体ペレットの第1回路上に、この第1回路の能動素子と異なる他の単一能動素子を主体に構成される第2回路を有する第2半導体ペレットを、その第2回路と第1半導体ペレットの第1回路とが対向する状態で塔載し、前記第1半導体ペレットの第1回路、第2半導体ペレットの第2回路の夫々をバンプ電極を介在して電気的に接続したことを特徴とする半導体装置。 1. A semiconductor device in which a semiconductor pellet is mounted on the base board of the mounting surface, the first semiconductor pellet having a first circuit configured mainly of a single active element on the mounting surface of the base substrate and towers, a first circuit on the first semiconductor pellet, the second semiconductor pellet having a second circuit configured to single active element and active element different from other of the first circuit mainly, its first and the tower in a state where two circuits with a first circuit of the first semiconductor pellet is opposed, first circuit of the first semiconductor pellet, electrical and respectively of the second circuit of the second semiconductor pellet interposed bump electrodes wherein a connected to.
  2. 【請求項2】 前記第1半導体ペレットの第1回路、第2半導体ペレットの第2回路のうち、一方はバイポーラトランジスタを主体に構成され、他方はMISFETを主体に構成されることを特徴する請求項1に記載の半導体装置。 Wherein the first circuit of the first semiconductor pellet, wherein one of the second circuit of the second semiconductor pellet, one of which is mainly composed of bipolar transistors, the other is characterized by being mainly composed of MISFET the semiconductor device according to claim 1.
  3. 【請求項3】 前記第1半導体ペレットの第1回路、第2半導体ペレットの第2回路の夫々は、前記ベース基板側から夫々独立に電源が供給されることを特徴とする請求項1又は請求項2に記載の半導体装置。 The first circuit of claim 3, wherein the first semiconductor pellet, each of the second circuit of the second semiconductor pellet according to claim 1 or claims, characterized in that the power each independently supplied from the base substrate side the semiconductor device according to claim 2.
  4. 【請求項4】 前記第1半導体ペレットの第1回路、第2半導体ペレットの第2回路のうち、回路動作で発生する熱量が大きい一方を、発生する熱量が小さい他方に比べて、冷却システムに近づけてベース基板の実装面上に塔載したことを特徴とする請求項1乃至請求項3に記載のいずれかの半導体装置。 4. A first circuit of the first semiconductor pellet, of the second circuit of the second semiconductor pellet, one amount of heat generated in the circuit operation is larger, than the other heat generated is small, the cooling system close any of the semiconductor device according to claim 1 to claim 3, characterized in that the towers on the mounting surface of the base substrate.
JP28763591A 1991-11-01 1991-11-01 Semiconductor device Pending JPH05129516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28763591A JPH05129516A (en) 1991-11-01 1991-11-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28763591A JPH05129516A (en) 1991-11-01 1991-11-01 Semiconductor device

Publications (1)

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JPH05129516A true true JPH05129516A (en) 1993-05-25

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Application Number Title Priority Date Filing Date
JP28763591A Pending JPH05129516A (en) 1991-11-01 1991-11-01 Semiconductor device

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Country Link
JP (1) JPH05129516A (en)

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