JPH05129516A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05129516A JPH05129516A JP3287635A JP28763591A JPH05129516A JP H05129516 A JPH05129516 A JP H05129516A JP 3287635 A JP3287635 A JP 3287635A JP 28763591 A JP28763591 A JP 28763591A JP H05129516 A JPH05129516 A JP H05129516A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor pellet
- pellet
- circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、ベース基板の実装面上に半導体ペレットが実装され
る半導体装置に適用して有効な技術に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a semiconductor pellet is mounted on a mounting surface of a base substrate.
【０００２】[0002]
【従来の技術】高い実装密度が得られる半導体装置とし
て、フェースダウン方式を利用した半導体装置が知られ
ている。この種の半導体装置は、ベース基板のペレット
塔載面上にフェースダウン方式で半導体ペレット(半導
体集積回路装置)を実装し、この半導体ペレットを封止
用キャップで封止する。半導体ペレットはベース基板及
び封止用キャップで形成されるキャビティ内に封止され
る。フェースダウン方式は、半導体ペレットの素子形成
面側に形成された外部端子(ボンディングパッド)、ベー
ス基板のペレット塔載面側に形成された電極の夫々を例
えば半田を使用したバンプ電極(ＣＣＢ電極、突起電極)
で電気的及び機械的に接続する方式である。フェースダ
ウン方式は、半導体ペレットの占有面積内においてベー
ス基板に実装できるので、ボンディングワイヤ方式に比
べて実装面積並びに信号伝達経路を縮小できる。2. Description of the Related Art A semiconductor device using a face-down method is known as a semiconductor device which can obtain a high packaging density. In this type of semiconductor device, a semiconductor pellet (semiconductor integrated circuit device) is mounted face down on a pellet mounting surface of a base substrate, and the semiconductor pellet is sealed with a sealing cap. The semiconductor pellet is sealed in the cavity formed by the base substrate and the sealing cap. The face-down method is an external terminal (bonding pad) formed on the element formation surface side of the semiconductor pellet, a bump electrode (CCB electrode, which uses solder for each of the electrodes formed on the pellet tower mounting surface side of the base substrate). (Projection electrode)
It is a method of connecting electrically and mechanically. Since the face-down method can be mounted on the base substrate within the area occupied by the semiconductor pellet, the mounting area and the signal transmission path can be reduced as compared with the bonding wire method.
【０００３】本発明者が開発中のフェースダウン方式を
利用する半導体装置は、モジュール基板、ＰＣＢ基板等
の実装基板の実装面上に複数個実装され、冷却装置で強
制冷却される冷却システムに組込まれる。この半導体装
置は、半導体ペレットの素子形成面と対向する裏面が熱
伝導用充填材を介在して封止用キャップのペレット連結
面(内壁)に連結され、半導体ペレットの素子形成面側に
塔載された回路システムの動作で発生する熱を封止用キ
ャップに伝導している。封止用キャップに伝導された熱
はさらに冷却装置に伝導される。熱伝導用充填材は熱伝
導性が高い半田を使用する。A plurality of semiconductor devices utilizing the face-down method, which the present inventor is developing, are mounted on a mounting surface of a mounting substrate such as a module substrate or a PCB substrate, and are incorporated in a cooling system forcibly cooled by a cooling device. Be done. In this semiconductor device, the back surface facing the element forming surface of the semiconductor pellet is connected to the pellet connecting surface (inner wall) of the sealing cap with the heat conducting filler interposed, and the semiconductor pellet is mounted on the element forming surface side. The heat generated by the operation of the circuit system is conducted to the sealing cap. The heat conducted to the sealing cap is further conducted to the cooling device. As the heat conduction filler, solder having high heat conductivity is used.
【０００４】前記半導体ペレットに塔載される回路シス
テムは、集積度（半導体装置の実装密度）を高める目的
として、例えばバイポーラトランジスタ、相補型ＭＩＳ
ＦＥＴ等の多種類の能動素子を主体に構成される。バイ
ポーラトランジスタは高い駆動能力が得られ、相補型Ｍ
ＩＳＦＥＴは高い集積度や低消費電力化が得られる。ま
た、半導体ペレットに塔載される回路システムは、論理
回路システム、記憶回路システム等の混合回路システム
で構成される。The circuit system mounted on the semiconductor pellet has, for example, a bipolar transistor or a complementary MIS for the purpose of increasing the degree of integration (mounting density of semiconductor devices).
It is mainly composed of various types of active elements such as FETs. The bipolar transistor has a high driving capability, and is a complementary M
The ISFET can achieve high integration and low power consumption. The circuit system mounted on the semiconductor pellet is composed of a mixed circuit system such as a logic circuit system and a storage circuit system.
【０００５】なお、前記フェースダウン方式を利用する
半導体装置については、特開昭６２−２４９４２９号公
報に記載されている。A semiconductor device utilizing the face-down method is described in Japanese Patent Laid-Open No. 62-249429.
【０００６】[0006]
【発明が解決しようとする課題】本発明者は、前記フェ
ースダウン方式を利用する半導体装置について検討した
結果、以下の問題点を見出した。The present inventor has found the following problems as a result of examining a semiconductor device using the face-down method.
【０００７】前記半導体装置の半導体ペレットに塔載さ
れる回路システムは、バイポーラトランジスタ、相補型
ＭＩＳＦＥＴ等の多種類の能動素子を主体に構成され
る。このため、半導体ペレットは、異なるデバイスが混
在し、単純に約２倍の製造プロセス数の増大となるの
で、半導体ペレットの歩留まりが低下し、結果的に半導
体装置の歩留まりが低下する。The circuit system mounted on the semiconductor pellet of the semiconductor device is mainly composed of various types of active elements such as bipolar transistors and complementary MISFETs. Therefore, in the semiconductor pellet, different devices are mixed and the number of manufacturing processes is simply increased by about twice, so that the yield of the semiconductor pellet is reduced, and as a result, the yield of the semiconductor device is reduced.
【０００８】本発明の目的は、ベース基板の実装面上に
半導体ペレットが実装される半導体装置において、実装
密度を高めることが可能な技術を提供することにある。An object of the present invention is to provide a technique capable of increasing the mounting density in a semiconductor device in which semiconductor pellets are mounted on the mounting surface of a base substrate.
【０００９】本発明の他の目的は、前記半導体装置の動
作速度の高速化を図ることが可能な技術を提供すること
にある。Another object of the present invention is to provide a technique capable of increasing the operating speed of the semiconductor device.
【００１０】本発明の他の目的は、前記目的を達成する
と共に、前記半導体装置の歩留まりを高めることが可能
な技術を提供することにある。Another object of the present invention is to provide a technique capable of achieving the above object and increasing the yield of the semiconductor device.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１３】(１)ベース基板の実装面上に半導体ペレッ
トが実装される半導体装置において、前記ベース基板の
実装面上に単一能動素子を主体に構成される第１回路を
有する第１半導体ペレットを塔載し、この第１半導体ペ
レットの第１回路上に、この第１回路の能動素子と異な
る他の単一能動素子を主体に構成される第２回路を有す
る第２半導体ペレットを、その第２回路と第１半導体ペ
レットの第１回路とが対向する状態で塔載し、この第１
半導体ペレットの第１回路、第２半導体ペレットの第２
回路の夫々をバンプ電極を介在して電気的に接続する。(1) In a semiconductor device in which a semiconductor pellet is mounted on a mounting surface of a base substrate, a first semiconductor pellet having a first circuit mainly composed of a single active element on the mounting surface of the base substrate. And a second semiconductor pellet having a second circuit mainly composed of another single active element different from the active element of the first circuit on the first circuit of the first semiconductor pellet. The second circuit and the first circuit of the first semiconductor pellet are mounted in a state of facing each other.
First circuit of semiconductor pellet, second circuit of second semiconductor pellet
Each of the circuits is electrically connected via the bump electrodes.
【００１４】(２)前記第１半導体ペレットの第１回路、
第２半導体ペレットの第２回路の夫々は、前記ベース基
板側から夫々独立に電源が供給される。(2) The first circuit of the first semiconductor pellet,
Power is supplied to each of the second circuits of the second semiconductor pellet independently from the base substrate side.
【００１５】(３)前記第１半導体ペレットの第１回路、
第２半導体ペレットの第２回路のうち、回路動作で発生
する熱量が大きい一方を、発生する熱量が小さい他方に
比べて、冷却システムに近づけてベース基板の実装面上
に塔載する。(3) The first circuit of the first semiconductor pellet,
One of the second circuits of the second semiconductor pellet, which generates a large amount of heat during the circuit operation, is placed closer to the cooling system on the mounting surface of the base substrate than the other which generates a small amount of heat.
【００１６】[0016]
【作用】上述した手段(１)によれば、第１半導体ペレッ
ト、第２半導体ペレットのうち、いずれか一方の占有面
積内に他方を配置したので、この他方の占有面積に相当
する分、半導体装置の実装密度を向上できる。According to the above-mentioned means (1), since the other of the first semiconductor pellet and the second semiconductor pellet is arranged within the occupied area of either one, the semiconductor corresponding to the other occupied area is The mounting density of the device can be improved.
【００１７】また、第１半導体ペレットの第１回路、第
２半導体ペレットの第２回路の夫々をバンプ電極を介在
して最短距離で電気的に接続したので、ワイヤボンディ
ング方式でボンディングされたワイヤを介在する場合に
比べて信号伝達径路を短くでき、半導体装置の動作速度
の高速化を図ることができる。Further, since the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet are electrically connected at the shortest distance via the bump electrodes, the wires bonded by the wire bonding method can be used. The signal transmission path can be shortened as compared with the case where it is interposed, and the operation speed of the semiconductor device can be increased.
【００１８】また、第１半導体ペレットの第１回路、第
２半導体ペレットの第２回路の夫々に塔載される能動素
子を相互に異なる最適かつ独立な製造プロセスで形成で
きるので、多種類の能動素子を１つの半導体ペレットに
混在して形成する場合に比べて、第１半導体ペレット、
第２半導体ペレットの夫々の製造プロセスを低減し、夫
々の製造プロセスでの歩留まりを向上でき、結果的に最
終的な半導体装置の歩留まりを向上できる。Further, since the active elements mounted in each of the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet can be formed by different optimal and independent manufacturing processes, various types of active elements can be formed. Compared with the case where the elements are mixedly formed in one semiconductor pellet, the first semiconductor pellet,
It is possible to reduce the respective manufacturing processes of the second semiconductor pellets, improve the yield in each manufacturing process, and consequently improve the final yield of the semiconductor device.
【００１９】上述した手段(２)によれば、第１半導体ペ
レットの第１回路、第２半導体ペレットの第２回路の夫
々の動作時に生じる電源ノイズを吸収できるので、夫々
の回路の動作速度を速め、半導体装置の動作速度の高速
化を図ることができる。According to the above-mentioned means (2), it is possible to absorb the power supply noise generated during the operation of each of the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet, so that the operating speed of each circuit can be increased. It is possible to increase the operating speed of the semiconductor device.
【００２０】上述した手段(３)によれば、第１半導体ペ
レットの第１回路、第２半導体ペレットの第２回路のう
ち、回路動作で発生する熱量の大きい半導体ペレットを
冷却システムで冷却でき、この半導体ペレットの放熱効
率を高められるので、半導体ペレットの誤動作を防止
し、半導体装置の信頼性を向上できる。According to the above-mentioned means (3), of the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet, the semiconductor pellet having a large amount of heat generated by the circuit operation can be cooled by the cooling system, Since the heat dissipation efficiency of the semiconductor pellet can be improved, malfunction of the semiconductor pellet can be prevented and the reliability of the semiconductor device can be improved.
【００２１】以下、本発明の構成について、フェースダ
ウン方式を利用する半導体装置に本発明を適用した一実
施例とともに説明する。The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor device utilizing a face-down method.
【００２２】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals and their repeated description will be omitted.
【００２３】[0023]
【実施例】本発明の一実施例であるフェースダウン方式
を利用する半導体装置の概略構成を図１(断面図)で示
す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (cross-sectional view) shows a schematic structure of a semiconductor device using a face-down method according to an embodiment of the present invention.
【００２４】図１に示すように、本発明の一実施例であ
るフェースダウン方式を利用する半導体装置は、ベース
基板５のペレット塔載面(実装面)側に半導体ペレット
１、半導体ペレット３の夫々を塔載し、この半導体ペレ
ット１、半導体ペレット３の夫々を封止用キャップ１１
で封止する。As shown in FIG. 1, in a semiconductor device using a face-down method according to an embodiment of the present invention, the semiconductor pellets 1 and 3 are placed on the pellet tower mounting surface (mounting surface) side of the base substrate 5. Each of them is mounted on a tower, and each of the semiconductor pellets 1 and 3 is sealed with a cap 11 for sealing.
Seal with.
【００２５】前記半導体ペレット１は、例えば単結晶珪
素からなる半導体基板を主体に構成され、その素子形成
面(図１中下面)に例えば論理回路システムを塔載してい
る。この論理回路システムは、例えば高い駆動能力が得
られるバイポーラトランジスタを主体に構成され、単一
能動素子で構成される。半導体ペレット１の素子形成面
側には外部端子(ボンディングパッド)２が複数個配列さ
れる。この外部端子２は、前記論理回路システムを構成
するバイポーラトランジスタ間を接続する配線層のうち
最上層の配線層で形成され、例えばアルミニウム合金膜
で形成される。半導体ペレット１は、単一能動素子(バ
イポーラトランジスタ)で論理回路システムを構成して
いるので、多種類の能動素子（例えばバイポーラトラン
ジスタ、ＭＩＳＦＥＴ等）で論理回路システムを構成す
る場合に比べて製造プロセス数を低減でき、最適な製造
プロセスで形成できる。The semiconductor pellet 1 is mainly composed of a semiconductor substrate made of, for example, single crystal silicon, and a logic circuit system is mounted on the element forming surface (the lower surface in FIG. 1). This logic circuit system is mainly composed of, for example, a bipolar transistor capable of obtaining high driving ability, and is composed of a single active element. A plurality of external terminals (bonding pads) 2 are arranged on the element forming surface side of the semiconductor pellet 1. The external terminal 2 is formed of the uppermost wiring layer of the wiring layers that connect the bipolar transistors that form the logic circuit system, and is formed of, for example, an aluminum alloy film. Since the semiconductor pellet 1 constitutes a logic circuit system with a single active element (bipolar transistor), the manufacturing process is different from that in the case where a logic circuit system is constituted with many kinds of active elements (eg bipolar transistor, MISFET, etc.). The number can be reduced and can be formed by an optimum manufacturing process.
【００２６】前記半導体ペレット３は、例えば単結晶珪
素からなる半導体基板を主体に構成され、その素子形成
面(図１中上面)に例えば記憶回路システムを塔載してい
る。この記憶回路システムは、例えば高い集積度や低消
費電力化が得られる相補型ＭＩＳＦＥＴ(ＣＭＯＳ)を主
体に構成され、単一能動素子で構成される。半導体ペレ
ット３の素子形成面側には外部端子(ボンディングパッ
ド)４が複数個配列される。この外部端子４は、前記記
憶回路システムを構成する相補型ＭＩＳＦＥＴ間を接続
する配線層のうち最上層の配線層で形成され、例えばア
ルミニウム合金膜で形成される。半導体ペレット３は、
単一能動素子（相補型ＭＩＳＦＥＴ）で記憶回路システ
ムを構成しているので、多種類の能動素子で記憶回路シ
ステムを構成する場合に比べて製造プロセス数を低減で
き、最適な製造プロセスで形成できる。The semiconductor pellet 3 is mainly composed of a semiconductor substrate made of, for example, single crystal silicon, and a memory circuit system is mounted on the element formation surface (upper surface in FIG. 1). This memory circuit system is mainly composed of, for example, a complementary MISFET (CMOS) that can achieve high integration and low power consumption, and is composed of a single active element. A plurality of external terminals (bonding pads) 4 are arranged on the element forming surface side of the semiconductor pellet 3. The external terminal 4 is formed of the uppermost wiring layer of the wiring layers connecting the complementary MISFETs constituting the memory circuit system, and is formed of, for example, an aluminum alloy film. The semiconductor pellet 3 is
Since the memory circuit system is composed of a single active element (complementary MISFET), the number of manufacturing processes can be reduced as compared with the case where the memory circuit system is composed of many kinds of active elements, and the optimum manufacturing process can be performed. ..
【００２７】前記ベース基板５は、例えばムライトで形
成され、図示していないが多層配線構造で構成される。
ベース基板５のペレット塔載面の中央部には凹部７が形
成され、この凹部７内には前記半導体ペレット３が配置
される。つまり、凹部７の開口サイズは半導体ペレット
３の平面形状に比べてひとまわり大きなサイズで形成さ
れ、凹部７の底面の位置はベース基板５のペレット塔載
面の位置よりも低く構成される。ベース基板５のペレッ
ト塔載面上には凹部７の周囲の領域において電極６が複
数個配列され、ベース基板５のペレット塔載面と対向す
る裏面には電極９が複数個配列される。この電極６、電
極９の夫々は前記多層配線構造の配線を介して電気的に
接続される。The base substrate 5 is formed of, for example, mullite and has a multilayer wiring structure (not shown).
A recess 7 is formed in the center of the pellet tower mounting surface of the base substrate 5, and the semiconductor pellet 3 is placed in the recess 7. That is, the opening size of the recess 7 is slightly larger than the planar shape of the semiconductor pellet 3, and the position of the bottom surface of the recess 7 is lower than the position of the pellet tower mounting surface of the base substrate 5. A plurality of electrodes 6 are arranged on the pellet tower mounting surface of the base substrate 5 in the region around the recess 7, and a plurality of electrodes 9 are arranged on the back surface of the base substrate 5 facing the pellet tower mounting surface. The electrodes 6 and 9 are electrically connected to each other through the wiring of the multilayer wiring structure.
【００２８】前記ベース基板５の電極６、半導体ペレッ
ト１の外部端子２の夫々の間にはバンプ電極(ＣＣＢ電
極、突起電極)１０が介在される。つまり、ベース基板
５、半導体ペレット１の夫々は、バンプ電極１０を介在
して電気的及び機械的に接続され、フェースダウン方式
で接続される。半導体ペレット１はバンプ電極１０を介
在してベース基板５のペレット塔載面上に実装される。
つまり、半導体ペレット１はベース基板５の専有面積内
に配置される。A bump electrode (CCB electrode, protruding electrode) 10 is interposed between the electrode 6 of the base substrate 5 and the external terminal 2 of the semiconductor pellet 1. That is, the base substrate 5 and the semiconductor pellet 1 are electrically and mechanically connected via the bump electrodes 10 and are connected in a face-down manner. The semiconductor pellet 1 is mounted on the pellet mounting surface of the base substrate 5 with the bump electrode 10 interposed therebetween.
That is, the semiconductor pellet 1 is arranged within the area occupied by the base substrate 5.
【００２９】前記半導体ペレット１の外部端子２、半導
体ペレット３の外部端子４の夫々の間にはバンプ電極１
０が介在される。つまり、半導体ペレット１、半導体ペ
レット３の夫々は、バンプ電極１０を介在して電気的及
び機械的に接続され、フェースダウン方式で接続され
る。半導体ペレット３は、その素子形成面が半導体ペレ
ット１の素子形成面と対向する状態でベース基板５のペ
レット塔載面側に塔載され、半導体ペレット１の素子形
成面上に塔載される。つまり、半導体ペレット３はバン
プ電極１０を介在して半導体ペレット１の占有面積内に
配置されるので、この半導体ペレット３の専有面積内に
相当する分、半導体装置の実装密度（平面方向）を向上
できる。また、半導体ペレット１の論理回路システム、
半導体ペレット２の記憶回路システムの夫々は、バンプ
電極１０を介在して最短距離で電気的に接続されるの
で、ワイヤーボンディング方式でボンディングされたワ
イヤを介在する場合に比ベて信号伝達経路を短くでき、
半導体装置の動作速度の高速化を図ることができる。前
記バンプ電極１０は、温度階層の最っとも高い温度に位
置する半田材料で形成される。The bump electrode 1 is provided between the external terminal 2 of the semiconductor pellet 1 and the external terminal 4 of the semiconductor pellet 3.
0 intervenes. That is, the semiconductor pellets 1 and the semiconductor pellets 3 are electrically and mechanically connected via the bump electrodes 10 and are connected in a face-down manner. The semiconductor pellet 3 is mounted on the pellet mounting surface side of the base substrate 5 with the element forming surface facing the element forming surface of the semiconductor pellet 1, and mounted on the element forming surface of the semiconductor pellet 1. That is, since the semiconductor pellets 3 are arranged in the area occupied by the semiconductor pellets 1 with the bump electrodes 10 interposed therebetween, the mounting density (plane direction) of the semiconductor device is improved by the amount corresponding to the area occupied by the semiconductor pellets 3. it can. Also, the logic circuit system of the semiconductor pellet 1,
Since each of the memory circuit systems of the semiconductor pellet 2 is electrically connected via the bump electrode 10 at the shortest distance, the signal transmission path is shorter than that when the wire bonded by the wire bonding method is interposed. You can
The operation speed of the semiconductor device can be increased. The bump electrode 10 is formed of a solder material located at the highest temperature in the temperature hierarchy.
【００３０】前記封止用キャップ１１は、断面形状がコ
の字形状に形成され、ベース基板５とで半導体ペレット
１、半導体ペレット３の夫々を収納しかつ気密封止する
キャビティを構成する。封止用キャップ１１は熱伝導性
の良好な例えば窒化アルミニウムで形成される。The sealing cap 11 has a U-shaped cross section, and together with the base substrate 5, constitutes a cavity for accommodating the semiconductor pellet 1 and the semiconductor pellet 3 and hermetically sealing them. The sealing cap 11 is made of, for example, aluminum nitride having good thermal conductivity.
【００３１】前記封止用キャップ１１のペレット連結面
(内壁)は熱伝導用充填材１２を介在して半導体ペレット
１の素子形面と対向する裏面に連結される。熱伝導用充
填材１２は、両者間をほぼ完全に密着し、半導体ペレッ
ト１の素子形面に塔載された論理回路システムの動作で
発生する熱を封止用キャップ１１に高い効率で伝達でき
る。この熱伝導用充填材１２は、前記バンプ電極１０に
比べて融点が低い半田材料で形成される。Pellet connecting surface of the sealing cap 11
The (inner wall) is connected to the back surface of the semiconductor pellet 1, which faces the element-shaped surface, with the heat-conducting filler 12 interposed therebetween. The heat-conducting filling material 12 adheres to each other almost completely, and the heat generated by the operation of the logic circuit system mounted on the element-shaped surface of the semiconductor pellet 1 can be transferred to the sealing cap 11 with high efficiency. .. The heat conduction filler 12 is formed of a solder material having a lower melting point than that of the bump electrode 10.
【００３２】前記封止用キャップ１２は、半導体ペレッ
ト１の周囲において、封止材１３によりベース基板５に
接着される。封止材１３は、半導体ペレット１の裏面に
熱伝導用充填材１２を介在して封止用キャップ１１のペ
レット連結面を連結する際、熱伝導用充填材１２の一部
を封止用キャップ１１とベース基板５との接着領域に流
し込んだ熱伝導用充填材１２で構成される。前記ベース
基板５及び封止用キャップ１１で形成され、封止材１３
で気密封止されるキャビティ内部には、組立プロセス中
での封止工程で使用されるガスが充填される。The sealing cap 12 is adhered to the base substrate 5 by the sealing material 13 around the semiconductor pellet 1. The sealing material 13 is a cap for sealing a part of the heat-conducting filling material 12 when the pellet connecting surface of the sealing cap 11 is connected to the back surface of the semiconductor pellet 1 with the heat-conducting filling material 12 interposed therebetween. The heat conductive filler 12 is poured into the bonding area between the base 11 and the base substrate 5. The encapsulating material 13 is formed of the base substrate 5 and the sealing cap 11.
The inside of the cavity hermetically sealed with is filled with the gas used in the sealing step in the assembly process.
【００３３】図２(図１に示す半導体装置の要部拡大断
面図)に示すように、前記半導体ペレット１の外部端子
２のうち、外部端子２Ａは、バンプ電極１０、ベース基
板５の電極６の夫々を介在してベース基板５の多層配線
構造の配線８Ａの一方に電気的に接続される。配線８Ａ
の他方はベース基板５の電極９に接続される。この電極
９には電源が印加され、配線８Ａ、電極６、バンプ電極
１０及び外部端子２Ａを通して半導体ペレット１の論理
回路システムに供給される。As shown in FIG. 2 (enlarged sectional view of the main part of the semiconductor device shown in FIG. 1), the external terminals 2A of the external terminals 2 of the semiconductor pellet 1 are bump electrodes 10 and electrodes 6 of the base substrate 5. Are electrically connected to one of the wirings 8A of the multi-layered wiring structure of the base substrate 5 via each of the above. Wiring 8A
The other of is connected to the electrode 9 of the base substrate 5. Power is applied to the electrode 9 and is supplied to the logic circuit system of the semiconductor pellet 1 through the wiring 8A, the electrode 6, the bump electrode 10 and the external terminal 2A.
【００３４】前記外部端子２のうち、外部端子２Ｂ１は
隣接する外部端子２Ｂ２と一体に構成される。この外部
端子２Ｂ１、外部端子２Ｂ２の夫々は、半導体ペレット
１の論理回路システムに接続されない所謂ダミーパッド
として構成される。外部端子２Ｂ２は、バンプ電極１０
を介在して半導体ペレット３の外部端子４に電気的に接
続される。外部端子２Ｂ１は、バンプ電極１０、ベース
基板５の電極６の夫々を介在してベース基板５の多層配
線構造の配線８Ｂの一方に接続される。配線８Ｂの他方
はベース基板５の電極９に接続される。この電極９には
電源が印加され、配線８Ｂ、電極６、バンプ電極１０、
外部端子２Ｂ１、２Ｂ２、バンプ電極１０及び外部端子
４を通して半導体ペレット３の記憶回路システムに供給
される。つまり、半導体ペレット１、半導体ペレット２
の夫々にはベース基板５の配線８Ａ、配線８Ｂの夫々で
独立に電源が供給され、半導体ペレット１の論理回路シ
ステム、半導体ペレット３の記憶回路システムの夫々の
動作時に生じる電源ノイズを吸収し易いように構成され
る。Of the external terminals 2, the external terminal 2B1 is formed integrally with the adjacent external terminal 2B2. Each of the external terminal 2B1 and the external terminal 2B2 is configured as a so-called dummy pad that is not connected to the logic circuit system of the semiconductor pellet 1. The external terminal 2B2 is the bump electrode 10
Is electrically connected to the external terminal 4 of the semiconductor pellet 3. The external terminal 2B1 is connected to one of the wirings 8B of the multilayer wiring structure of the base substrate 5 via the bump electrode 10 and the electrode 6 of the base substrate 5, respectively. The other side of the wiring 8B is connected to the electrode 9 of the base substrate 5. Power is applied to the electrode 9, and the wiring 8B, the electrode 6, the bump electrode 10,
The semiconductor pellets 3 are supplied to the storage circuit system through the external terminals 2B1 and 2B2, the bump electrodes 10 and the external terminals 4. That is, the semiconductor pellet 1 and the semiconductor pellet 2
Power is independently supplied to each of the wiring 8A and the wiring 8B of the base substrate 5, and it is easy to absorb the power supply noise generated during the operation of each of the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3. Is configured as follows.
【００３５】このように構成される半導体装置は、図３
(システム構成図)に示すように、フェースダウン方式で
冷却システム２０の実装基板（モジュール基板又はＰＣ
Ｂ基板）２３の実装面上に１個或は複数個実装される。
つまり、半導体装置は、そのベース基板５の電極９にバ
ンプ電極２５を介在して実装基板２３の電極２４に電気
的及び機械的に接続することにより実装基板２３に実装
される。この半導体装置は、実装基板２３及び封止用キ
ャップ２２で形成されるキャビティ内部に封止される。
封止用キャップ２２は封止材２７により実装基板２３に
接着される。冷却システム２０の実装基板２３は、前記
半導体装置のベース基板５と同様に多層配線構造で構成
される。The semiconductor device having such a structure is shown in FIG.
As shown in (system configuration diagram), the mounting board (module board or PC) of the cooling system 20 is face down type.
One or more are mounted on the mounting surface of the B board) 23.
That is, the semiconductor device is mounted on the mounting substrate 23 by electrically and mechanically connecting the electrodes 9 of the base substrate 5 to the electrodes 24 of the mounting substrate 23 with the bump electrodes 25 interposed therebetween. The semiconductor device is sealed inside the cavity formed by the mounting substrate 23 and the sealing cap 22.
The sealing cap 22 is adhered to the mounting substrate 23 with a sealing material 27. The mounting board 23 of the cooling system 20 has a multi-layered wiring structure like the base board 5 of the semiconductor device.
【００３６】前記半導体装置の封止用キャップ１１の上
側表面上にはクシ歯形状で形成される放熱フィン２１が
構成される。この放熱フィン２１は熱伝導用充填材１
２、封止用キャップ１１の夫々を通して伝導される、半
導体ペレット１に塔載された論理回路システムの動作で
発生する熱を冷却システム２０側に放熱する目的で構成
される。On the upper surface of the sealing cap 11 of the semiconductor device, a radiation fin 21 formed in a comb tooth shape is formed. This radiation fin 21 is a filler 1 for heat conduction.
2. The heat is generated through the operation of the logic circuit system mounted on the semiconductor pellet 1 and is conducted through the sealing cap 11 to radiate to the cooling system 20 side.
【００３７】前記封止用キャップ２２は例えば窒化アル
ミニウムで構成される。この封止用キャップ２２は、前
記放熱フィン２１と接触するクシ歯２２Ａが構成され、
放熱フィン２１を通して伝導される熱を上部に配置され
た水冷ジャケット２６に放出する。この水冷ジャケット
２６には複数個の冷却用水管２６Ａが構成され、この冷
却用水管２６Ａ内には冷却水が循環する。前述の放熱フ
ィン２１から封止用キャップ２２に伝導される熱は、こ
の水冷ジャケット２６の冷却用水管２６Ａ内を循環する
冷却水に伝達され、冷却システム２０の外部に放出され
る。The sealing cap 22 is made of, for example, aluminum nitride. The sealing cap 22 has comb teeth 22A that come into contact with the heat radiation fins 21.
The heat conducted through the radiating fins 21 is radiated to the water cooling jacket 26 arranged above. The water cooling jacket 26 is provided with a plurality of cooling water pipes 26A, and cooling water circulates in the cooling water pipes 26A. The heat conducted from the radiating fin 21 to the sealing cap 22 is transferred to the cooling water circulating in the cooling water pipe 26A of the water cooling jacket 26, and is radiated to the outside of the cooling system 20.
【００３８】前記半導体装置は、冷却システム２０側に
半導体ペレット１を配置している。この半導体ペレット
１は、相補型ＭＩＳＦＥＴに比べて消費電力が高い、つ
まり発熱量が大きいバイポーラトランジスタで構成され
た論理回路システムを塔載している。この論理回路シス
テムの動作で発生する熱は、半導体ペレット１の裏面か
ら熱伝導用充填材１２を通して封止型キャップ１１に効
率的に伝導され、封止用キャップ１１に伝導された熱
は、放熱フィン２１を通して効率的に冷却システム２０
に伝導される。In the semiconductor device, the semiconductor pellet 1 is arranged on the cooling system 20 side. This semiconductor pellet 1 is mounted with a logic circuit system composed of a bipolar transistor that consumes more power than a complementary MISFET, that is, generates a large amount of heat. The heat generated by the operation of the logic circuit system is efficiently conducted from the back surface of the semiconductor pellet 1 to the sealing cap 11 through the heat conducting filler 12, and the heat conducted to the sealing cap 11 is radiated. Cooling system 20 efficiently through fins 21
Is transmitted to.
【００３９】このように、ベース基板５のペレット塔載
面(実装面)上に半導体ペレットが実装される半導体装置
において、前記ベース基板５のペレット塔載面上にバイ
ポーラトランジスタ(単一能動素子)を主体に構成される
論理回路システムを有する半導体ペレット１を塔載し、
この半導体ペレット１の論理回路システム上に、この論
理回路システムのバイポーラトランジスタと異なる相補
型ＭＩＳＦＥＴ（単一能動素子）を主体に構成される記
憶回路システムを有する半導体ペレット３を、その記憶
回路システムと半導体ペレット１の論理回路システムと
が対向する状態で塔載し、前記半導体ペレット１の論理
回路システム、半導体ペレット３の記憶回路システムの
夫々をバンプ電極１０を介在して電気的に接続する。こ
の構成により、半導体ペレット１の占有面積内に半導体
ペレット３を配置したので、この半導体ペレット３の占
有面積に相当する分、半導体装置の実装密度を向上する
ことができる。As described above, in the semiconductor device in which the semiconductor pellets are mounted on the pellet tower mounting surface (mounting surface) of the base substrate 5, the bipolar transistor (single active element) is mounted on the pellet tower mounting surface of the base substrate 5. The semiconductor pellet 1 having a logic circuit system mainly composed of
A semiconductor pellet 3 having a memory circuit system mainly composed of a complementary MISFET (single active element) different from the bipolar transistor of the logic circuit system on the logic circuit system of the semiconductor pellet 1, The semiconductor pellet 1 is mounted in a state where it faces the logic circuit system, and the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3 are electrically connected to each other through the bump electrodes 10. With this configuration, since the semiconductor pellets 3 are arranged within the area occupied by the semiconductor pellets 1, the packaging density of the semiconductor devices can be improved by the amount corresponding to the area occupied by the semiconductor pellets 3.
【００４０】また、半導体ペレット１の論理回路システ
ム、半導体ペレット３の記憶回路システムの夫々をバン
プ電極１０を介在して最短距離で電気的に接続したの
で、ワイヤボンディング方式でボンディングされたワイ
ヤを介在する場合に比べて信号伝達経路を短くでき、半
導体装置の動作速度の高速化を図ることができる。Further, since the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3 are electrically connected at the shortest distance via the bump electrodes 10, the wires bonded by the wire bonding method are interposed. The signal transmission path can be shortened as compared to the case where the semiconductor device is operated, and the operation speed of the semiconductor device can be increased.
【００４１】また、半導体ペレット１の論理回路システ
ムを構成するバイポーラトランジスタ、半導体ペレット
３の記憶回路システムを構成する相補型ＭＩＳＦＥＴの
夫々を相互に異なる最適かつ独立な製造プロセスで形成
でき、多種類の能動素子（バイポーラトランジスタ、相
補型ＭＩＳＦＥＴ）を１つの半導体ペレットに混在して
形成する場合に比べて、半導体ペレット１、半導体ペレ
ット３の夫々の製造プロセス数を低減できるので、夫々
の製造プロセスでの歩留まりを向上でき、結果的に最終
的な半導体装置の歩留まりを向上できる。Further, each of the bipolar transistor forming the logic circuit system of the semiconductor pellet 1 and the complementary MISFET forming the storage circuit system of the semiconductor pellet 3 can be formed by different optimum and independent manufacturing processes, and various types can be formed. Compared to the case where active elements (bipolar transistors, complementary MISFETs) are formed in a mixed manner in one semiconductor pellet, the number of manufacturing steps for each of the semiconductor pellet 1 and the semiconductor pellet 3 can be reduced. The yield can be improved, and as a result, the final yield of the semiconductor device can be improved.
【００４２】また、前記半導体ペレット１の論理回路シ
ステム、半導体ペレット３の記憶回路システムの夫々
は、前記ベース基板５の配線８Ａ、配線８Ｂの夫々から
独立に電源が供給される。この構成により、半導体ペレ
ット１の論理回路システム、半導体ペレット３の記憶回
路システムの夫々の動作時に生じる電源ノイズを吸収で
きるので、夫々の回路の動作速度を速め、半導体装置の
動作速度の高速化をより図ることができる。Further, the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3 are independently supplied with power from the wiring 8A and the wiring 8B of the base substrate 5, respectively. With this configuration, power supply noise generated during the operation of each of the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3 can be absorbed, so that the operation speed of each circuit can be increased and the operation speed of the semiconductor device can be increased. It can be better.
【００４３】また、前記半導体ペレット１の論理回路シ
ステム、半導体ペレット３の記憶回路システムのうち、
高い駆動能力が得られる(発熱量が大きい)バイポーラト
ランジスタで構成された論理回路システムを有する半導
体ペレット１を、低消費電力化が得られる(発熱量が小
さい)相補型ＭＩＳＦＥＴで構成された記憶回路システ
ムを有する半導体ペレット３に比ベて、冷却システム２
０に近づけてベース基板５のペレット塔載面上に塔載す
る。この構成により、回路動作で発生する熱量の大きい
半導体ペレット１を冷却システム２０で冷却でき、この
半導体ペレット１の放熱効率を高められるので、半導体
ペレット１の誤動作を防止し、半導体装置の信頼性を向
上できる。Of the logic circuit system of the semiconductor pellet 1 and the storage circuit system of the semiconductor pellet 3,
A semiconductor pellet 1 having a logic circuit system composed of bipolar transistors capable of obtaining high driving capability (large heat generation amount), and a memory circuit constituted of complementary MISFETs capable of low power consumption (small heat generation amount) Cooling system 2 compared to semiconductor pellet 3 which has a system
It is mounted on the pellet mounting surface of the base substrate 5 so as to approach 0. With this configuration, the semiconductor pellet 1 having a large amount of heat generated by the circuit operation can be cooled by the cooling system 20, and the heat dissipation efficiency of the semiconductor pellet 1 can be improved, so that the malfunction of the semiconductor pellet 1 can be prevented and the reliability of the semiconductor device can be improved. Can be improved.
【００４４】なお、本実施例では、半導体ペレット１、
半導体ペレット３の夫々を単晶珪素基板で構成したが、
このどちらか一方を例えばＧａＡｓ(ガリウム・砒素)か
らなる半絶縁性基板で構成し、多機能化を高めてもよ
い。In this embodiment, the semiconductor pellets 1,
Although each of the semiconductor pellets 3 is composed of a single crystal silicon substrate,
Either one of them may be composed of a semi-insulating substrate made of, for example, GaAs (gallium arsenide) to enhance multifunctionality.
【００４５】また、半導体ペレット１、半導体ペレット
２のうちどちらか一方の半導体ペレットを他方の半導体
ペレットの補修用として構成してもよい。Further, either one of the semiconductor pellets 1 and the semiconductor pellets 2 may be used for repairing the other semiconductor pellet.
【００４６】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.
【００４７】[0047]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.
【００４８】ベース基板の実装面上に半導体ペレットが
実装される半導体装置において、実装密度を向上でき
る。In the semiconductor device in which the semiconductor pellets are mounted on the mounting surface of the base substrate, the mounting density can be improved.
【００４９】また、前記半導体装置の動作速度の高速化
を図ることができる。Further, the operating speed of the semiconductor device can be increased.
【００５０】また、前記半導体装置の歩留まりを向上で
きる。Further, the yield of the semiconductor device can be improved.
【００５１】また、前記半導体装置の動作速度の高速化
をより図ることができる。Further, the operating speed of the semiconductor device can be further increased.
【００５２】また、前記半導体装置の誤動作を防止でき
る。Further, malfunction of the semiconductor device can be prevented.
【図１】 本発明の一実施例である半導体装置の断面
図。FIG. 1 is a cross-sectional view of a semiconductor device that is an embodiment of the present invention.
【図２】 前記半導体装置の要部拡大断面図。FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor device.
【図３】 前記半導体装置を冷却システムに組込んだシ
ステム構成図。FIG. 3 is a system configuration diagram in which the semiconductor device is incorporated into a cooling system.
１…半導体ペレット、２…外部端子、３…半導体ペッ
ト、４…外部端子、５…ベース基板、６…電極、７…凹
部、８Ａ，８Ｂ…配線、９…電極、１０…バンプ電極、
１１…封止用キャップ、１２…熱伝導用充填材、１３…
封止材、２０…冷却システム、２１…放熱フィン、２２
…封止用キャップ、２３…実装基板。DESCRIPTION OF SYMBOLS 1 ... Semiconductor pellet, 2 ... External terminal, 3 ... Semiconductor pet, 4 ... External terminal, 5 ... Base substrate, 6 ... Electrode, 7 ... Recess, 8A, 8B ... Wiring, 9 ... Electrode, 10 ... Bump electrode,
11 ... Sealing cap, 12 ... Heat conduction filler, 13 ...
Sealing material, 20 ... Cooling system, 21 ... Radiating fin, 22
... sealing cap, 23 ... mounting substrate.
Claims (4)
が実装される半導体装置において、前記ベース基板の実
装面上に単一能動素子を主体に構成される第１回路を有
する第１半導体ペレットを塔載し、この第１半導体ペレ
ットの第１回路上に、この第１回路の能動素子と異なる
他の単一能動素子を主体に構成される第２回路を有する
第２半導体ペレットを、その第２回路と第１半導体ペレ
ットの第１回路とが対向する状態で塔載し、前記第１半
導体ペレットの第１回路、第２半導体ペレットの第２回
路の夫々をバンプ電極を介在して電気的に接続したこと
を特徴とする半導体装置。1. A semiconductor device in which a semiconductor pellet is mounted on a mounting surface of a base substrate, wherein a first semiconductor pellet having a first circuit mainly composed of a single active element is mounted on the mounting surface of the base substrate. A second semiconductor pellet having a second circuit mainly composed of another single active element different from the active element of the first circuit is mounted on the first circuit of the first semiconductor pellet. The two circuits and the first circuit of the first semiconductor pellet are mounted in a state of being opposed to each other, and the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet are electrically connected via bump electrodes. A semiconductor device characterized by being connected to.
２半導体ペレットの第２回路のうち、一方はバイポーラ
トランジスタを主体に構成され、他方はＭＩＳＦＥＴを
主体に構成されることを特徴する請求項１に記載の半導
体装置。2. Of the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet, one is mainly composed of a bipolar transistor and the other is mainly composed of a MISFET. Item 2. The semiconductor device according to item 1.
２半導体ペレットの第２回路の夫々は、前記ベース基板
側から夫々独立に電源が供給されることを特徴とする請
求項１又は請求項２に記載の半導体装置。3. The first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet are each independently supplied with power from the base substrate side. Item 2. The semiconductor device according to item 2.
２半導体ペレットの第２回路のうち、回路動作で発生す
る熱量が大きい一方を、発生する熱量が小さい他方に比
べて、冷却システムに近づけてベース基板の実装面上に
塔載したことを特徴とする請求項１乃至請求項３に記載
のいずれかの半導体装置。4. One of the first circuit of the first semiconductor pellet and the second circuit of the second semiconductor pellet, which has a larger amount of heat generated by circuit operation, is used in a cooling system than the other which has a smaller amount of heat generated. 4. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on a mounting surface of the base substrate so as to be close to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3287635A JPH05129516A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3287635A JPH05129516A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129516A true JPH05129516A (en) | 1993-05-25 |
Family
ID=17719783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3287635A Pending JPH05129516A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129516A (en) |
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