JPH05275611A - Multichip module - Google Patents

Multichip module

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Publication number
JPH05275611A
JPH05275611A JP4074085A JP7408592A JPH05275611A JP H05275611 A JPH05275611 A JP H05275611A JP 4074085 A JP4074085 A JP 4074085A JP 7408592 A JP7408592 A JP 7408592A JP H05275611 A JPH05275611 A JP H05275611A
Authority
JP
Japan
Prior art keywords
semiconductor chip
multi
chip
formed
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4074085A
Other languages
Japanese (ja)
Other versions
JP2823029B2 (en
Inventor
Hiromori Tobase
浩守 鳥羽瀬
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP4074085A priority Critical patent/JP2823029B2/en
Publication of JPH05275611A publication Critical patent/JPH05275611A/en
Application granted granted Critical
Publication of JP2823029B2 publication Critical patent/JP2823029B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156Side view

Abstract

PURPOSE: To improve mounting density, to shorten the line length of an electric wiring, to cut down the period of propagation of a signal, and to accomplish high-speed operation of a multichip.
CONSTITUTION: In a multichip module which is formed by housing a plurality of semiconductor chips 4 and electrically connected to an electrically insulated substrate 1 having prescribed electric wiring pattern 2, a multistage-formed recessed part is formed on the electrically insulted a substrate 1, and each semiconductor chip 4 are housed in the recessed part in such a manner that they are separated with each other in vertical direction.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置に関し、特に複数の半導体チップが、収納されるマルチチップモジュールの構造に関する。 The present invention relates to relates to a semiconductor device, in particular a plurality of semiconductor chips, to a structure of a multi-chip module to be housed.

【0002】 [0002]

【従来の技術】従来のマルチチップモジュールは第5図の断面図に示すように、複数の半導体チップ4が電気配線パターン(図示せず)を有する電気絶縁基板の同一面上に収納されており、前記電気絶縁基板1と前記半導体チップ4とは、金属細線10によって電気的に接続され、前記電気絶縁基板1の電気配線パターンは、外部リード6によって電気的に接続されている。 As the Conventional multi-chip module shown in the sectional view of FIG. 5, a plurality of semiconductor chips 4 is accommodated in the electric wiring pattern on the same surface of the electrically insulating substrate having a (not shown) the the electrically insulating substrate 1 and the semiconductor chip 4 are electrically connected by fine metal wires 10, the electric wiring pattern of the electrically insulating substrate 1 is electrically connected to an external lead 6.

【0003】この従来構造で例えば、CPU(Cent [0003] With this conventional structure, for example, CPU (Cent
ral Processing Unit)1個, FP ral Processing Unit) 1 single, FP
U(Floting Processing Uni U (Floting Processing Uni
t)1個, BIU(Buth Interface U t) 1 single, BIU (Buth Interface U
nit)1個, キャッシュメモリ6個の合計9個の半導体チップで構成されるマルチチップモジュールであれば、電気絶縁基板の大きさは、約85mm角となる。 nit) 1 piece, if multichip module made up of the cache memory 6 total of nine semiconductor chips, the size of the electrically insulating substrate is approximately 85mm square.

【0004】 [0004]

【発明が解決しようとする課題】ところで、この従来のマルチチップモジュールでは、半導体チップ4が電気絶縁基板1の同一面のみに収納されているため、半導体チップの収納数が増えると電気絶縁基板の大きさも大きくならざるを得ない。 [SUMMARY OF THE INVENTION Incidentally, in this conventional multi-chip module, since the semiconductor chip 4 is housed only in the same surface of the electrically insulating substrate 1, a semiconductor chip storing number is increased when the electrically insulating substrate inevitably be size large. 従って電気配線の線路長が長くなる。 Thus the line length of the electrical wiring becomes long.

【0005】このように、電気配線の線路長が長くなると、配線の持つキャパシタンスが大きくなり、信号の伝播遅延時間が大きくなる。 [0005] Thus, the line length of the electrical wiring becomes longer, the capacitance possessed by the wiring is increased, the propagation delay time of the signal increases. このため、マルチチップモジュールを高速動作させようとした場合、1つのクロックの時間内に信号が戻らなくなり、マルチチップモジュールが高速動作しなくなるといった問題があった。 Therefore, when the multi-chip module attempts to high speed operation, the signal is no longer return within one clock time, multi-chip module is a problem no longer high-speed operation.

【0006】この問題は、非常に大きな問題であり、高速動作すればするほど信号の処理スピードが上がるのに対し、高速動作ができないという問題があった。 [0006] This problem is a very big problem, while the signal of the processing speed more you high-speed operation is increased, there is a problem that can not be high-speed operation.

【0007】この発明はこのような従来技術の課題に鑑みて提案されたもので、フリップチップ接続等のマルチチップモジュールにおいて、実装密度の向上および電気配線の線路長を短くし、上記従来技術の欠点を除去することを目的とする。 [0007] The present invention has been proposed in view of the problems of the prior art, in multi-chip modules, such as flip-chip connection, to shorten the line length of the enhancement and electrical wiring mounting density, the prior art an object of the present invention is to eliminate the drawbacks.

【0008】 [0008]

【課題を解決するための手段】本発明によれば、複数の半導体チップを収納し、前記半導体チップがバンプにより所定の電気配線パターンを有する電気絶縁基板に電気的に接続されてなるマルチチップモジュールにおいて、 According to the present invention, in order to solve the problems], a plurality of semiconductor chips accommodated, the multi-chip module semiconductor chip is electrically connected to the electrically insulating substrate having a predetermined electrical interconnect pattern by a bump in,
前記電気絶縁基板には多段式凹部が形成されており、かつ、前記各半導体チップが該凹部に上下方向に相互に離間して収容されていることを特徴とするマルチチップモジュールが得られる。 Wherein the electrical insulating substrate are multistage recess formed, and a multi-chip module is obtained, characterized in that each of said semiconductor chip is accommodated apart from each other in the vertical direction in the recess.

【0009】 [0009]

【実施例】まず、本発明の第1実施例のマルチチップモジュールについて説明する。 EXAMPLES First, a description will be given of a multi-chip module according to the first embodiment of the present invention. 図1に示すように、半導体チップ4は、電気配線パターン2を有する電気絶縁基板1に設けられた多段の凹部にそれぞれ離間並行に上下方向多段式に収容されている。 1, the semiconductor chip 4 is accommodated vertically multistage each spaced parallel multistage recess provided in the electrically insulating substrate 1 having an electrical wiring pattern 2. そして半導体チップ4を載置する段部にはバンプ3が形成されている。 The bump 3 is formed on the stepped portion for mounting the semiconductor chip 4. 各半導体チップ4はこのバンプ3上に載置されており、電気配線パターン2にて、任意の半導体チップ同士、あるいは、外部リード6と接続されている。 Each semiconductor chip 4 is placed on the bumps 3, in an electric wiring pattern 2, together any semiconductor chip or are connected to the external lead 6.

【0010】この場合、半導体チップ4として、チップコンデンサ等の搭載も可能である。 [0010] In this case, as the semiconductor chip 4, it is also possible mounting such as a chip capacitor. なお、図中5はキャップ、7は封止材である。 In the drawing, 5 is the cap 7 is a sealing material.

【0011】次に、本発明の第2実施例のマルチチップモジュールについて説明する。 [0011] Next, a description for the multi-chip module of the second embodiment of the present invention. 第2実施例のマルチチップモジュールは図2に示すように、水平方向にも半導体チップ4を並列させるように凹部の半導体チップ載置部を形成しておくものである。 Multi-chip module of the second embodiment as shown in FIG. 2, in which previously formed a semiconductor chip mounting portion of the concave portion so as to parallel the semiconductor chip 4 in the horizontal direction. なお、このような縦方向のみではなく横方向への半導体チップ4の配置や数は図示のものに限定されるものでないことはいうまでもない。 The arrangement and number of the semiconductor chips 4 in the lateral direction not only such longitudinally of course not limited to the illustrated.

【0012】第1実施例の半導体チップ4の配置によれば、上方に行くにしたがって半導体チップの大きさが大きくならざるを得ず、同じ大きさの半導体チップ4を同一基板に配置することができなかったが、この第2実施例の配置にすることにより、搭載される半導体チップ4 According to the arrangement of the semiconductor chips 4 of the first embodiment, be placed inevitably size of the semiconductor chip is large, a semiconductor chip 4 of the same size on the same substrate as it goes upward could not be, by the arrangement of the second embodiment, the semiconductor chip 4 to be mounted
の大きさ多種多様であっても対応させることが可能となる。 Even the size of a wide variety and it is possible to correspond.

【0013】次に、本発明のマルチチップモジュールにヒートシンクを取り付ける場合について説明する。 [0013] Next, the case where the multi-chip module of the present invention mounting a heat sink. 図3 Figure 3
は第1実施例のマルチチップモジュールにヒートシンク9を取り付けた場合の断面図である。 Is a sectional view when mounting the heat sink 9 to the multi-chip module of the first embodiment. ヒートシンク9を発熱性の高い半導体チップを最上部に接続し、前記半導体チップとヒートシンク9を高熱伝導性接着材8を介して接着したものである。 The heat sink 9 highly exothermic semiconductor chip connected to the top, the semiconductor chip and the heat sink 9 is obtained by bonding via a highly thermal conductive adhesive 8.

【0014】図4は、本発明の第2実施例のマルチチップモジュールにヒートシンク9を取り付けた場合の断面図である。 [0014] Figure 4 is a cross-sectional view of the case of attaching a heat sink 9 in the multi-chip module of the second embodiment of the present invention. 発熱性の高い半導体チップを複数収納する場合、本実施例のように電気絶縁基板の凹部の最上部に前記複数の半導体チップを接続することで、複数の半導体チップにヒートシンクを接着可能となる。 When a plurality receiving highly exothermic semiconductor chip, by connecting a plurality of semiconductor chips to the top of the concave portion of the electrically insulating substrate as in the present embodiment, it is possible bonding the heat sink to the plurality of semiconductor chips.

【0015】なお、上記電気絶縁基板1の材料としては、アルミナ基板及びガラスエポキシ基板等が従来より用いられているが、フリップチップ実装の信頼性から考えると半導体チップと熱膨張率の整合のとれたイビデン(株)より市販されているセラコム基板という商品名の基板を用いるのが適切である。 [0015] As a material of the electrically insulating substrate 1, but an alumina substrate and a glass epoxy substrate or the like have conventionally been used, take the matching of the semiconductor chip and the thermal expansion coefficient Considering the reliability of the flip chip mounting and it is appropriate to use a substrate trade name Serakomu substrate commercially available from Ibiden Corporation.

【0016】セラコム基板においてのフリップチップ実装評価実績として、125℃〜−65℃の温度サイクル試験にて1000サイクルで断線の発生なしという結果が得られている。 [0016] as a flip-chip mounting evaluation results of the Serakomu substrate, 125 ℃ ~-65 ℃ result that no occurrence of disconnection at 1,000 cycles at a temperature cycle test is obtained.

【0017】上記本発明の各実施例によれば、従来技術で電気絶縁基板の大きさが約85mm角必要であるものを、約50mm角程度まで小さくすることが可能である。 According to the embodiments of the present invention, those magnitude of the electrical insulating substrate in the prior art it is needed about 85mm square, it can be reduced to about 50mm square.

【0018】 [0018]

【発明の効果】以上説明したように本発明は、電気配線パターンを有する電気絶縁基板に設けられた多段の凹部に半導体チップを離間並行して縦方向に収容して接続することで、搭載される半導体チップの大きさや数による制限を受けることなく、電気絶縁基板を小さくすることができ、実装密度の向上および電気配線の線路長を短くして信号伝播遅延時間を短くでき、マルチチップモジュールの高速動作を可能ならしめるという効果がある。 The present invention described above, according to the present invention, by connecting a semiconductor chip in multiple stages of recesses provided on the electrically insulating substrate having an electrical wiring pattern spaced parallel housed longitudinally, mounted that the semiconductor chip size and without being restricted by the number, an electrical insulating substrate can be reduced, it can shorten the signal propagation delay time by shortening the line length of the enhancement and electrical wiring mounting density, the multichip module there is an effect that makes it possible for high-speed operation.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1実施例を示す断面図である。 1 is a cross-sectional view showing a first embodiment of the present invention.

【図2】本発明の第2実施例を示す断面図である。 It is a sectional view showing a second embodiment of the present invention; FIG.

【図3】本発明の第1実施例にヒートシンクを取り付けた場合の断面図である。 3 is a cross-sectional view of the case of attaching the heat sink to the first embodiment of the present invention.

【図4】本発明の第2実施例にヒートシンクを取り付けた場合の断面図である。 It is a cross-sectional view of a case of attaching the heat sink to the second embodiment of the present invention; FIG.

【図5】従来のヒートシンク付マルチチップモジュールを示す断面図である。 5 is a cross-sectional view showing a multi-chip module with a conventional heat sink.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 電気絶縁基板 2 電気配線パターン 3 バンプ 4 半導体チップ 5 キャップ 6 外部リード 7 封止材 8 高熱伝導性接着材 9 ヒートシンク 10 金属細線 1 electrically insulating substrate 2 electric wiring patterns 3 bumps 4 semiconductor chip 5 Cap 6 external lead 7 encapsulant 8 high thermal conductive adhesive 9 sink 10 thin metal wire

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 複数の半導体チップを収納し、前記半導体チップがバンプにより所定の電気配線パターンを有する電気絶縁基板に電気的に接続されてなるマルチチップモジュールにおいて、前記電気絶縁基板には多段式凹部が形成されており、かつ、前記各半導体チップが該凹部に上下方向に相互に離間して収容されていることを特徴とするマルチチップモジュール。 1. A housing a plurality of semiconductor chips, the semiconductor chip multichip module comprising electrically connected to the electrically insulating substrate having a predetermined electrical wiring pattern by bumps, the electrically insulating substrate is a multi-stage a recessed portion is formed, and a multi-chip module, characterized in that each of said semiconductor chip is accommodated apart from each other in the vertical direction in the recess.
  2. 【請求項2】 前記電気絶縁基板に形成された凹部内において、水平方向に単段および・または復段の凹部が複数形成されて多段式凹部を形成し、これらの凹部に前記半導体チップが収容されていることを特徴とする請求項1に記載のマルチチップモジュール。 2. A the electrically insulating substrate formed in the recess, the recess of the single-stage and-or Fukudan horizontally formed in plurality to form a multistage recess, said semiconductor chip is accommodated in these recesses multi-chip module according to claim 1, characterized in that it is.
JP4074085A 1992-03-30 1992-03-30 Multi-chip module Expired - Fee Related JP2823029B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4074085A JP2823029B2 (en) 1992-03-30 1992-03-30 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4074085A JP2823029B2 (en) 1992-03-30 1992-03-30 Multi-chip module

Publications (2)

Publication Number Publication Date
JPH05275611A true JPH05275611A (en) 1993-10-22
JP2823029B2 JP2823029B2 (en) 1998-11-11

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5728972A (en) * 1996-04-22 1998-03-17 United Microelectronics Corporation Multiple chip module for packaging integrated circuits
US6031279A (en) * 1996-09-02 2000-02-29 Siemens Aktiengesellschaft Power semiconductor component
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US6469395B1 (en) 1999-11-25 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6717251B2 (en) 2000-09-28 2004-04-06 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
JP2008521213A (en) * 2004-11-16 2008-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Devices and methods for making two-sided soi wafer scale package having through vias connected
JP2008211126A (en) * 2007-02-28 2008-09-11 Matsushita Electric Ind Co Ltd Semiconductor module and card type information device
JP2010238923A (en) * 2009-03-31 2010-10-21 Tdk Corp Module with built-in electronic component
JP2014209091A (en) * 2013-03-25 2014-11-06 ローム株式会社 Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US5728972A (en) * 1996-04-22 1998-03-17 United Microelectronics Corporation Multiple chip module for packaging integrated circuits
US6031279A (en) * 1996-09-02 2000-02-29 Siemens Aktiengesellschaft Power semiconductor component
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
US6469395B1 (en) 1999-11-25 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6717251B2 (en) 2000-09-28 2004-04-06 Kabushiki Kaisha Toshiba Stacked type semiconductor device
JP2008521213A (en) * 2004-11-16 2008-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Devices and methods for making two-sided soi wafer scale package having through vias connected
JP2008211126A (en) * 2007-02-28 2008-09-11 Matsushita Electric Ind Co Ltd Semiconductor module and card type information device
JP2010238923A (en) * 2009-03-31 2010-10-21 Tdk Corp Module with built-in electronic component
JP2014209091A (en) * 2013-03-25 2014-11-06 ローム株式会社 Semiconductor device
US10112824B2 (en) 2013-03-25 2018-10-30 Rohm Co., Ltd. Semiconductor device

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