JP2007042848A - Wiring board, electric element device and compound board - Google Patents

Wiring board, electric element device and compound board Download PDF

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JP2007042848A
JP2007042848A JP2005225060A JP2005225060A JP2007042848A JP 2007042848 A JP2007042848 A JP 2007042848A JP 2005225060 A JP2005225060 A JP 2005225060A JP 2005225060 A JP2005225060 A JP 2005225060A JP 2007042848 A JP2007042848 A JP 2007042848A
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conductor pattern
wiring board
external
electric element
board
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JP4667154B2 (en
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Tomoko Tajiri
智子 田尻
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board excellent in high heat dissipation and in connection reliability with an external circuit board, and also capable of achieving high accuracy of position, and to provide an electric element device and a compound board using the wiring board. <P>SOLUTION: The wiring board includes: an insulating board 1, a wiring layer 3 formed at least on one surface of the insulating board 1 and its inside; an electric element mounting part 5 formed in one main surface 1a of the insulating board 1; a convex shaped protrusion 9 having a flat surface 9a in the top arranged inside an edge 7 of another main surface 1b of the insulating board 1; an external terminal 11 formed in the edge 7; and a conductive pattern 15 formed in the flat surface 9a of the protrusion 9. Thus, the gross area of the conductive pattern 15 is made larger than that of the external terminal 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、配線基板、電気素子装置並びに複合基板に関し、より詳細には、半導体素子等の電気素子を搭載するための特定形状の配線基板と、それを用いて形成される電気素子装置並びに複合基板に関する。   The present invention relates to a wiring board, an electric element device, and a composite substrate, and more specifically, a wiring board having a specific shape for mounting an electric element such as a semiconductor element, and an electric element device and a composite formed using the wiring board. Regarding the substrate.

近年、高度情報化時代を迎え、情報通信技術が急速に発展し、それに伴い、半導体素子等の各種電気素子の高速化、高度集積化が図られている。   In recent years, with the advent of advanced information technology, information communication technology has rapidly developed, and accordingly, various electric elements such as semiconductor elements have been increased in speed and highly integrated.

これに対応して、電気素子を搭載する配線基板に外部回路を接続した複合配線基板も高性能化及び高実装密度化の傾向が顕著となっている。   Correspondingly, the trend of higher performance and higher mounting density is also noticeable in a composite wiring board in which an external circuit is connected to a wiring board on which an electric element is mounted.

また、電気素子の作動周波数の向上に伴い、素子実装配線基板、外部回路基板等を薄型化して基板内の配線をより短くすることも強く求められるようになってきている。   Further, as the operating frequency of electric elements is improved, it has been strongly demanded that the element mounting wiring board, the external circuit board, etc. be made thinner to shorten the wiring in the board.

このように高実装密度化、高性能化のため導体パターンの配線間隙やランド間隙がより狭く密になり、基板厚さがより薄くなると、僅かの外力や温度差で部材間に撓みや熱歪みが生じ、しかも、僅かの撓みや熱歪みで基板の接続不良等の不都合を招来しがちとなり、このため、特に、配線基板への素子実装工程や配線基板と外部回路基板との接続工程時に於ける対応端子間接合の信頼性維持向上は、近年、極めて重要な技術課題となっている。   In this way, when the wiring gap and land gap of the conductor pattern become narrower and denser for higher mounting density and higher performance, and the board thickness becomes thinner, bending and thermal distortion between members due to slight external force and temperature difference. In addition, a slight bending or thermal strain tends to cause inconveniences such as poor connection of the board.For this reason, particularly during the element mounting process on the wiring board and the connection process between the wiring board and the external circuit board. In recent years, maintaining and improving the reliability of joints between corresponding terminals has become an extremely important technical issue.

複合配線基板の一例として、外部回路基板に、ＬＣＣ（リードレス チップ キャリア）が実装された従来のリードレス部品表面実装基板構造を図６（ａ）に示す。   As an example of the composite wiring board, FIG. 6A shows a conventional leadless component surface mounting board structure in which an LCC (leadless chip carrier) is mounted on an external circuit board.

図６（ａ）に於いて、半導体素子５０を収納した上述のＬＣＣ（以下、単に配線基板という）５１は外観が偏平矩形に形成されており、側面から底面に連続して延びた複数の外部接続端子５３を有している。   In FIG. 6A, the above-described LCC (hereinafter simply referred to as a wiring board) 51 containing the semiconductor element 50 is formed in a flat rectangular shape, and has a plurality of external parts extending continuously from the side surface to the bottom surface. A connection terminal 53 is provided.

一方、外部回路基板５５は配線基板５１の取り付け位置に、配線基板５１の外部接続端子５３に対応して複数のランド（図示せず）を配設している。   On the other hand, the external circuit board 55 is provided with a plurality of lands (not shown) corresponding to the external connection terminals 53 of the wiring board 51 at the mounting position of the wiring board 51.

その外部回路基板５５に配線基板５１を実装するには、外部回路基板５５のランド上にペースト状のはんだ５７を塗布した後、外部接続端子５３を夫々ランドに対応させながら外部回路基板５５上に配線基板を載置する。   In order to mount the wiring board 51 on the external circuit board 55, paste-like solder 57 is applied on the lands of the external circuit board 55, and then the external connection terminals 53 are made to correspond to the lands on the external circuit board 55. Place the wiring board.

その後、これを例えばエアーリフロー装置内で加熱し、はんだ５７をリフロー処理してランドに外部接続端子５３をはんだ付けする。   Then, this is heated, for example in an air reflow apparatus, the solder 57 is reflow-processed, and the external connection terminal 53 is soldered to a land.

このように配線基板５１を外部回路基板５５にはんだ付けした際には、配線基板５１と外部回路基板５５の隙間が狭く、その間のはんだ接合部の高さｂが低いため、配線基板５１と外部回路基板５５との熱膨張係数差等により生じる局所的熱応力歪みをはんだ接合部５７で吸収しきれず、これが原因で接合部５７の破壊を起こしやすいという欠点がある。   When the wiring board 51 is soldered to the external circuit board 55 in this way, the gap between the wiring board 51 and the external circuit board 55 is narrow, and the height b of the solder joint therebetween is low. There is a drawback that the local thermal stress distortion caused by the difference in thermal expansion coefficient from the circuit board 55 cannot be absorbed by the solder joint portion 57, and this causes the joint portion 57 to be easily broken.

また、前記熱応力歪みがそれ程大きく無く、それによる損傷が殆どみられないような場合でも、これが多数回繰返し加えられると、はんだ接合部５７に疲労破壊を生じ、接続不良等の不都合が発生することもある。   Even when the thermal stress strain is not so great and damage is hardly observed, if it is repeatedly applied many times, fatigue failure occurs in the solder joint portion 57, resulting in inconvenience such as poor connection. Sometimes.

特に、配線基板５１の主構成材である絶縁基板５９が、セラミックスからなる場合には、該絶縁基板５９に用いられる通常のセラミックス材の熱膨張係数は、４〜７×１０−６／℃程度であるのに対し、外部回路基板５５は一般にガラス繊維入りエポキシ樹脂等の樹脂系基板からなり、これら樹脂系材の熱膨張係数は１５〜２０×１０−６／℃程度のものが多いため、両者の間の熱膨張係数差は大きく、このため絶縁基板５９がガラスセラミックス材等の比較的強度の低い材質からなる場合、特に上記接続部５７の破壊、損傷を招きやすい。 In particular, when the insulating substrate 59 which is the main constituent material of the wiring substrate 51 is made of ceramics, the thermal expansion coefficient of a normal ceramic material used for the insulating substrate 59 is about 4 to 7 × 10 −6 / ° C. On the other hand, the external circuit board 55 is generally made of a resin-based substrate such as an epoxy resin containing glass fiber, and the thermal expansion coefficient of these resin-based materials is often about 15 to 20 × 10 −6 / ° C. The difference in thermal expansion coefficient between the two is large, and therefore, when the insulating substrate 59 is made of a material having a relatively low strength such as a glass ceramic material, the connection portion 57 is particularly likely to be broken or damaged.

このような不都合を回避するための対策として、例えば図６（ｂ）に示すように、実装部品５１の底面５１ａ、或いは、底面に重ねる外部回路基板５５の取付面５５ａの内どちらか一方の面に、上記実装部品５１と外部回路基板５５との間に隙間を形成する突出部６１を複数設けたリードレス表面実装部品の配線基板への実装構造の発明が開示されている（例えば、特許文献１参照）。   As a measure for avoiding such inconvenience, for example, as shown in FIG. 6B, either one of the bottom surface 51a of the mounting component 51 or the mounting surface 55a of the external circuit board 55 superimposed on the bottom surface. Further, an invention of a structure for mounting a leadless surface mounting component on a wiring board provided with a plurality of protrusions 61 forming a gap between the mounting component 51 and the external circuit board 55 is disclosed (for example, Patent Documents). 1).

即ち、図６（ｂ）の実装構造は、突出部６１を複数設けることで従来のＬＣＣにおけるはんだ接合部の高さｂよりも高いはんだ接合部の高さｃを得、これによりはんだ接合部にかかる熱応力歪みの集中を緩和しようとするものである。   That is, in the mounting structure of FIG. 6B, by providing a plurality of protrusions 61, the height c of the solder joint is higher than the height b of the solder joint in the conventional LCC. It is intended to alleviate the concentration of such thermal stress strain.

また、図７に示すように電気素子７０搭載用の配線基板７１において、その底表面を平坦水平な突起部７２が周縁部７３に対し段差を有して凸状下方に突き出した形状に形成することで、前記配線基板７１の周縁部７３に設けられた端子７５と、凸状突起部底面の下側に位置する外部配線回路７７のランド７９との間隙が従来の配線基板のそれに比較して著しく大きく取れ、はんだ等の接続部材８１の高さｄを大きく取れるため、ここで熱応力歪みを充分に吸収することができ、高いはんだ接合信頼性を具備し、且つ、繰り返し熱応力による疲労耐性に優れた複合配線基板も報告されている（例えば、特許文献２参照）。   Further, as shown in FIG. 7, in the wiring board 71 for mounting the electric element 70, the bottom surface is formed in a shape in which a flat horizontal projection 72 has a step with respect to the peripheral edge 73 and protrudes downward in a convex shape. As a result, the gap between the terminal 75 provided on the peripheral edge 73 of the wiring board 71 and the land 79 of the external wiring circuit 77 located on the lower side of the bottom surface of the convex protrusion is larger than that of the conventional wiring board. Since it can be made extremely large and the height d of the connecting member 81 such as solder can be made large, the thermal stress strain can be sufficiently absorbed here, it has high solder joint reliability, and fatigue resistance due to repeated thermal stress. An excellent composite wiring board has also been reported (see, for example, Patent Document 2).

また、図８に示すように、放熱板９０に接合された半導体素子９１を覆うように基板９２が配設され、この基板９２の半導体素子９１に重なる部分が、基板９２の半導体素子９１に重ならない部分に対して突出するように形成された半導体装置９３が報告されている（例えば、特許文献３参照）。
特開平１０−１４５０２５号公報 特願２００４−０２１２４１ 特開平１１−２６０９６３号公報 Also, as shown in FIG. 8, a substrate 92 is disposed so as to cover the semiconductor element 91 joined to the heat sink 90, and a portion of the substrate 92 overlapping the semiconductor element 91 overlaps the semiconductor element 91 of the substrate 92. There has been reported a semiconductor device 93 formed so as to protrude from a portion that should not be formed (see, for example, Patent Document 3).
Japanese Patent Application Laid-Open No. 10-145025 Japanese Patent Application No. 2004-021241 Japanese Patent Laid-Open No. 11-260963

しかしながら、上述した図６（ｂ）の構造の実装部品５１や、図７の構造の配線基板７１では、突出部６１と配線基板５１、配線基板７１と外部回路基板７７との間で摩擦が起こり、はんだなどで形成されたはんだ接合部５７、接合部材８１のセルフアライメント効果が十分に発現し得ず、位置精度が悪くなるという問題がある。   However, in the mounting component 51 having the structure shown in FIG. 6B and the wiring board 71 having the structure shown in FIG. 7, friction occurs between the protruding portion 61 and the wiring board 51, and between the wiring board 71 and the external circuit board 77. There is a problem that the self-alignment effect of the solder joint portion 57 and the joining member 81 formed of solder or the like cannot be sufficiently exhibited, and the positional accuracy is deteriorated.

また、両者ともに配線基板の放熱性が低くなることが懸念される。   Moreover, both are concerned that the heat dissipation of a wiring board will become low.

また、図８に示した実装構造では、周囲に形成された外部接続端子９４ａよりも高いセルフアライメント効果を有する突起部に形成された外部接続端子９４ｂの断面積の総和が周囲に形成された外部接続端子９４ａの断面積の総和よりも小さいため、突起部に形成された外部接続端子９４ｂによるセルフアライメント効果は十分に発現せず、位置精度の大幅な向上は望めない。   Further, in the mounting structure shown in FIG. 8, the sum of the cross-sectional areas of the external connection terminals 94b formed on the protrusions having a self-alignment effect higher than that of the external connection terminals 94a formed on the periphery is formed on the periphery. Since it is smaller than the sum of the cross-sectional areas of the connection terminals 94a, the self-alignment effect due to the external connection terminals 94b formed on the protrusions is not sufficiently exhibited, and a significant improvement in position accuracy cannot be expected.

また、突出部の外部接続端子の面積が小さいことから放熱性の向上も見込めない。   Further, since the area of the external connection terminal of the protruding portion is small, improvement in heat dissipation cannot be expected.

従って、本発明の目的は、高放熱性と外部回路基板との接続信頼性に優れる配線基板、ならびにそれを用いた電気素子装置並びに複合基板を提供することである。また、本発明の目的は、高い位置精度を実現することができる配線基板、ならびにそれを用いた電気素子装置並びに複合基板を提供することである。   Accordingly, an object of the present invention is to provide a wiring board excellent in high heat dissipation and connection reliability with an external circuit board, and an electric element device and a composite board using the wiring board. Moreover, the objective of this invention is providing the wiring board which can implement | achieve high positional accuracy, an electric element apparatus using the same, and a composite substrate.

本発明の配線基板は、絶縁基板と、該絶縁基板の表面または内部のうち少なくとも一方に形成された配線層と、前記絶縁基板の一方の主面に形成された電気素子搭載部と、前記絶縁基板の他方の主面の周縁部よりも内側に配置された頂部に平坦面を有する凸状の突起部と、前記周縁部に形成された外部端子と、前記突起部の平坦面に形成された導体パターンとを具備してなり、前記外部端子の総面積よりも前記導体パターンの総面積が大きいことを特徴とする。   The wiring board of the present invention includes an insulating substrate, a wiring layer formed on at least one of the surface and the inside of the insulating substrate, an electric element mounting portion formed on one main surface of the insulating substrate, and the insulation Protruding protrusions having a flat surface at the top disposed on the inner side of the peripheral edge of the other main surface of the substrate, external terminals formed on the peripheral edge, and formed on the flat surface of the protrusion And a conductor pattern, wherein the total area of the conductor pattern is larger than the total area of the external terminals.

また、本発明の配線基板は、前記導体パターンが、複数形成されていることが望ましい。   In the wiring board of the present invention, it is preferable that a plurality of the conductor patterns are formed.

また、本発明の配線基板は、一つの前記導体パターンの面積が、一つの前記外部端子の面積よりも大きいことが望ましい。   In the wiring board of the present invention, it is desirable that the area of one conductor pattern is larger than the area of one external terminal.

また、本発明の配線基板は、前記突起部の平坦面のうち前記導体パターンが形成された面積が、残りの面積よりも大きいことが望ましい。   In the wiring board of the present invention, it is desirable that the area where the conductor pattern is formed on the flat surface of the protrusion is larger than the remaining area.

本発明の電気素子装置は、以上説明した配線基板の前記電気素子搭載部に、電気素子を搭載したことを特徴とする。   The electric element device of the present invention is characterized in that an electric element is mounted on the electric element mounting portion of the wiring board described above.

本発明の複合基板は、以上説明した電気素子装置が、前記外部端子に対応する回路端子を有する外部回路基板に搭載されるとともに、前記外部端子と前記回路端子とが接続部材を介して接続されていることを特徴とする。   In the composite substrate of the present invention, the electric element device described above is mounted on an external circuit substrate having circuit terminals corresponding to the external terminals, and the external terminals and the circuit terminals are connected via a connecting member. It is characterized by.

また、本発明の複合基板は、前記外部回路基板が、前記導体パターンに対応する接続パターンを有するとともに、前記導体パターンと前記接続パターンとが接着部材を介して接着されていることが望ましい。   In the composite substrate of the present invention, it is desirable that the external circuit board has a connection pattern corresponding to the conductor pattern, and the conductor pattern and the connection pattern are bonded via an adhesive member.

また、本発明の複合基板は、前記導体パターンと前記接続パターンとの距離が０．１〜０．５ｍｍであることが望ましい。   Moreover, as for the composite substrate of this invention, it is desirable for the distance of the said conductor pattern and the said connection pattern to be 0.1-0.5 mm.

本発明の配線基板によれば、絶縁基板の周縁部よりも段差をつけて形成された突起部の平坦面に周縁部に形成された外部端子の総面積よりも、総面積が大きい導体パターンを設けることで、外部端子と外部回路基板との距離を容易に大きくすることができるため、外部回路基板との接続信頼性に優れ、しかも導体パターンにより格段に放熱性の高い配線基板を提供することができる。また、この導体パターンをはんだなどを介して外部回路基板に接続した場合には、はんだの溶解時に生じるセルフアライメント効果によって配線基板を正しい位置に容易に実装することができる。この効果は導体パターンの総面積を絶縁基板の周縁部に形成された外部端子の総面積よりも大きくすることで特に顕著になるものである。   According to the wiring board of the present invention, the conductor pattern having a larger total area than the total area of the external terminals formed on the peripheral edge on the flat surface of the protrusion formed with a step from the peripheral edge of the insulating substrate. Providing a wiring board that is excellent in connection reliability with the external circuit board and that has an extremely high heat dissipation property due to the conductor pattern because the distance between the external terminal and the external circuit board can be easily increased by providing Can do. Further, when this conductor pattern is connected to an external circuit board via solder or the like, the wiring board can be easily mounted at the correct position by the self-alignment effect that occurs when the solder is melted. This effect becomes particularly remarkable by making the total area of the conductor pattern larger than the total area of the external terminals formed on the peripheral edge of the insulating substrate.

また、本発明の配線基板によれば、複数の導体パターンを形成し、各導体パターン間に間隙を形成することで、導体パターンが突起部の主面から突出している場合には、配線基板の表面積を増加させることができ、配線基板の放熱性をさらに向上させることができる。   Further, according to the wiring board of the present invention, by forming a plurality of conductor patterns and forming gaps between the conductor patterns, when the conductor pattern protrudes from the main surface of the protrusion, The surface area can be increased, and the heat dissipation of the wiring board can be further improved.

また、導体パターンが突起部の主面から突出していない場合でも、導体パターンの表面に金属からなる部材を形成した場合には同様の効果が得られる。   Even when the conductor pattern does not protrude from the main surface of the protrusion, the same effect can be obtained when a member made of metal is formed on the surface of the conductor pattern.

また、独立した導体パターンのうち少なくとも１つの面積を、一つの外部端子の面積よりも大きくすることで、導体パターンと外部回路基板とを接着部材を用いて接続した場合に接着部材によるセルフアライメント効果ならびに導体パターンと外部回路基板との間の距離を大きくする効果を向上させることができる。   Also, by making at least one area of the independent conductor patterns larger than the area of one external terminal, the self-alignment effect by the adhesive member when the conductor pattern and the external circuit board are connected using the adhesive member In addition, the effect of increasing the distance between the conductor pattern and the external circuit board can be improved.

また、突起部の平坦面のうち導体パターンの面積を、残りの面積よりも大きくすることが、放熱性の点からも、セルフアライメント効果ならびに導体パターンと外部回路基板との間の距離を大きくする点からも望ましい。   Also, making the conductor pattern area larger than the remaining area of the flat surface of the protrusion increases the self-alignment effect and the distance between the conductor pattern and the external circuit board from the viewpoint of heat dissipation. It is desirable also from a point.

本発明の電気素子装置は、以上説明した配線基板の電気素子搭載部に電気素子を搭載したことを特徴とするもので、これにより外部回路基板との接続信頼性、放熱性に優れた電気素子装置を提供できる。   The electric element device of the present invention is characterized in that an electric element is mounted on the electric element mounting portion of the wiring board described above, whereby an electric element excellent in connection reliability and heat dissipation with an external circuit board is provided. Equipment can be provided.

そして、この電気素子装置の外部端子と外部回路基板の回路端子とを接続部材を用いて接続することで放熱性に優れ、電気素子装置と外部回路基板との接続信頼性に優れた複合基板となる。   And, by connecting the external terminal of this electrical element device and the circuit terminal of the external circuit board using a connecting member, a composite substrate excellent in heat dissipation and excellent in connection reliability between the electrical element device and the external circuit board, Become.

特に、配線基板の導体パターンと外部回路基板の接続パターンとを接着部材を介して接続することで、電気素子装置の位置決めが容易となり、位置精度を向上させることができる。また、接着部材の表面張力により導体パターンと外部回路基板との距離を容易に大きくすることができる。   In particular, by connecting the conductor pattern of the wiring board and the connection pattern of the external circuit board via an adhesive member, the electric element device can be easily positioned and the position accuracy can be improved. Further, the distance between the conductor pattern and the external circuit board can be easily increased by the surface tension of the adhesive member.

また、前記導体パターンと接続パターンとの距離を０．１ｍｍ以上とすることで、セルフアライメント効果を高くすることができる。また、０．５ｍｍ以下とすることで、複合基板の低背化を図ることができる。   Moreover, the self-alignment effect can be enhanced by setting the distance between the conductor pattern and the connection pattern to be 0.1 mm or more. Moreover, the height reduction of the composite substrate can be achieved by setting the thickness to 0.5 mm or less.

本発明の配線基板は、例えば図１に示すように、絶縁基板１と、絶縁基板の表面に形成された配線層３とを備えており、絶縁基板１の一方の主面１ａ（絶縁基板１の表面）には電気素子を搭載する搭載部５が形成され、絶縁基板１の他方の主面１ｂ（絶縁基板１の裏面）には、周縁部７と、この周縁部７に比べ凸状に突出し、平坦面９ａを備えた突起部９が形成されている。   For example, as shown in FIG. 1, the wiring board of the present invention includes an insulating substrate 1 and a wiring layer 3 formed on the surface of the insulating substrate, and one main surface 1 a (insulating substrate 1) of the insulating substrate 1. A mounting portion 5 for mounting an electric element is formed on the other surface of the insulating substrate 1, and a peripheral portion 7 is more convex than the peripheral portion 7 on the other main surface 1 b of the insulating substrate 1 (the back surface of the insulating substrate 1). A protruding portion 9 that protrudes and has a flat surface 9a is formed.

また、周縁部７の絶縁基板１の裏面１ｂ側には外部端子１１が形成され、突起部９の平坦面９ａには導体パターン１５が形成されている。また、絶縁基板１の少なくとも一部を厚み方向に貫通して形成された貫通導体１６によって、絶縁基板１の一方の主面１ａに形成された配線層３と周縁部７に形成された外部端子１１とは電気的に接続されており、電気回路を形成している。   An external terminal 11 is formed on the rear surface 1 b side of the insulating substrate 1 in the peripheral portion 7, and a conductor pattern 15 is formed on the flat surface 9 a of the protruding portion 9. In addition, the wiring layer 3 formed on one main surface 1a of the insulating substrate 1 and the external terminal formed on the peripheral portion 7 by the through conductor 16 formed so as to penetrate at least a part of the insulating substrate 1 in the thickness direction. 11 is electrically connected to form an electric circuit.

また、突起部９の平坦面９ａに形成されている導体パターン１５は、図１（ａ）に示すように突起部９の平坦面９ａの大部分を覆うように形成された形態や、図１（ｂ）に示すように、突起部９の平坦面９ａの一部を覆うように形成して、突起部９の平坦面９ａの一部が露出するようにした形態が挙げられる。また、突起部９は複数設けられていてもよい。   Further, the conductor pattern 15 formed on the flat surface 9a of the protruding portion 9 is formed so as to cover most of the flat surface 9a of the protruding portion 9 as shown in FIG. As shown to (b), the form which formed so that a part of flat surface 9a of the projection part 9 might be covered and a part of the flat surface 9a of the projection part 9 was exposed is mentioned. A plurality of protrusions 9 may be provided.

また、本発明の配線基板２１の他の形態として、例えば、図２（ａ）、（ｂ）に示すように絶縁基板１の表面１ａ側にキャビティ１７が形成され、このキャビティ１７の中に電気素子を搭載する搭載部５が形成されている形態が挙げられる。   As another form of the wiring board 21 of the present invention, for example, a cavity 17 is formed on the surface 1a side of the insulating substrate 1 as shown in FIGS. The form in which the mounting portion 5 on which the element is mounted is formed.

このようなキャビティ１７を備えた配線基板２１は低背化することが容易であるという利点がある。   The wiring board 21 provided with such a cavity 17 has an advantage that it is easy to reduce the height.

以上説明したように、本発明の配線基板２１は種々の形態を有するのであるが、その特徴は周縁部７に外部端子１１を設け、この周縁部７と段差ができるように形成された突起部９を具備し、その突起部９の平坦面９ａに導体パターン１５が形成されるとともに、この導体パターン１５の総面積が外部端子１１の総面積よりも大きいことである。   As described above, the wiring board 21 of the present invention has various forms, but the feature thereof is that the peripheral terminal 7 is provided with the external terminal 11, and the protrusion formed so as to have a step with the peripheral edge 7. 9, the conductor pattern 15 is formed on the flat surface 9 a of the protrusion 9, and the total area of the conductor pattern 15 is larger than the total area of the external terminals 11.

この突起部９により、配線基板２１を搭載する外部回路基板と、外部端子１１との距離を容易に大きくすることができる。また、外部端子１１の総面積よりも導体パターン１５の総面積を大きくすることによって配線基板２１の放熱性を格段に向上させることができる。   By this protrusion 9, the distance between the external circuit board on which the wiring board 21 is mounted and the external terminal 11 can be easily increased. Further, by increasing the total area of the conductor pattern 15 compared to the total area of the external terminals 11, the heat dissipation of the wiring board 21 can be significantly improved.

以上説明した本発明の配線基板２１の搭載部５に、図３（ａ）、（ｂ）に示すように電気素子２３を搭載することで、本発明の電気素子装置２５となる。   By mounting the electric element 23 on the mounting portion 5 of the wiring board 21 of the present invention described above as shown in FIGS. 3A and 3B, the electric element device 25 of the present invention is obtained.

なお、電気素子２３は、例えば、図３（ａ）に示すように、接着剤２７を介して配線基板２１に接続された形態や、図３（ｂ）に示すように、バンプ２９などによりフリップチップ接続された形態であってもよい。図３（ａ）のような形態では、ワイヤ３１によって電気素子２３と配線基板２１とは電気的に接続されている。そして、封止樹脂３３によって電気素子２３は覆われ保護されている。   For example, the electric element 23 is flipped by a form connected to the wiring board 21 via an adhesive 27 as shown in FIG. 3A, or by a bump 29 as shown in FIG. 3B. It may be a chip-connected form. In the configuration as shown in FIG. 3A, the electric element 23 and the wiring board 21 are electrically connected by the wire 31. The electrical element 23 is covered and protected by the sealing resin 33.

そして、図４、５に示すように、このような本発明の電気素子装置２５を外部回路基板３５に実装することで、本発明の複合基板３７となる。   4 and 5, by mounting the electric element device 25 of the present invention on the external circuit board 35, a composite substrate 37 of the present invention is obtained.

本発明の複合基板３７においては、電気素子装置２５と外部回路基板３５とは、配線基板１の周縁部７に設けられた外部端子１１と、外部回路基板３５の電気素子装置２５と向かい合う側の主面３５ａに設けられ、外部端子１１に対応するように配置された回路端子３５ｂとの間に設けられた接続部材３９によって電気的に接続されている。   In the composite substrate 37 of the present invention, the electric element device 25 and the external circuit board 35 are provided on the side facing the electric element device 25 of the external terminal 11 provided on the peripheral edge portion 7 of the wiring board 1. It is electrically connected by a connecting member 39 provided between the circuit surface 35 b provided on the main surface 35 a and corresponding to the external terminal 11.

また、電気素子装置２５と外部回路基板３５とは、絶縁基板１の突起部９の平坦面９ａに形成された導体パターン１５と、外部回路基板３５の電気素子装置２５と向かい合う側の主面３５ａに導体パターン１５と対応するように設けられた接続パターン３５ｃとの間に設けられた接着部材４１によって接着されていることが望ましい。   In addition, the electric element device 25 and the external circuit board 35 include the conductor pattern 15 formed on the flat surface 9 a of the protrusion 9 of the insulating substrate 1 and the main surface 35 a on the side of the external circuit board 35 facing the electric element device 25. It is desirable that the bonding pattern 41 is bonded to the connection pattern 35 c provided so as to correspond to the conductor pattern 15.

このように突起部９を備えた配線基板１を用いて形成された電気素子装置２５を外部回路基板３５に実装する場合には、突起部９によって外部端子１１と外部回路基板３５の回路端子３５ｂとの距離を大きくすることができる。   When the electric element device 25 formed using the wiring board 1 having the protrusions 9 is mounted on the external circuit board 35, the external terminals 11 and the circuit terminals 35 b of the external circuit board 35 are formed by the protrusions 9. And the distance can be increased.

さらに、突起部９の平坦面９ａに導体パターン１５を設けることで配線基板１、電気素子装置２５の放熱性を向上させることができる。なお、この効果は導体パターン１５が接着部材４１によって外部回路基板３５と接続されていない場合でも発現することは言うまでもない。   Furthermore, by providing the conductor pattern 15 on the flat surface 9a of the protrusion 9, the heat dissipation of the wiring board 1 and the electric element device 25 can be improved. Needless to say, this effect appears even when the conductor pattern 15 is not connected to the external circuit board 35 by the adhesive member 41.

この導体パターン１５の厚みは、接着部材４１を用いない場合でも放熱性を向上させるために厚く形成することが望ましく、５０μｍ以上、さらに１００μｍ以上、特に２００μｍ以上とすることが望ましい。   Even when the adhesive member 41 is not used, the conductor pattern 15 is preferably formed thick in order to improve heat dissipation, and is preferably 50 μm or more, more preferably 100 μm or more, and particularly preferably 200 μm or more.

また、図４、５に示すように、導体パターン１５と接続パターン３５ｃとを接着部材４１によって接続することで、接着部材４１によるセルフアライメント効果により、配線基板１、電気素子装置２５を外部回路基板３５に実装する際の位置精度が格段に向上する。   4 and 5, by connecting the conductor pattern 15 and the connection pattern 35c with the adhesive member 41, the wiring substrate 1 and the electric element device 25 are connected to the external circuit board by the self-alignment effect by the adhesive member 41. The position accuracy when mounting on 35 is significantly improved.

これは接続部材３９よりも接着部材４１の高さが小さいために、接着部材４１によるセルフアライメント効果が接続部材３９によるセルフアライメント効果よりも大きくなることに起因するものである。なお、セルフアライメント効果が顕著に発揮される導体パターン１５と接続パターン３５ｃのと間の距離は０．１〜０．５ｍｍの範囲である。   This is because the self-alignment effect by the bonding member 41 is larger than the self-alignment effect by the connecting member 39 because the height of the bonding member 41 is smaller than the connection member 39. In addition, the distance between the conductor pattern 15 and the connection pattern 35c where the self-alignment effect is remarkably exhibited is in the range of 0.1 to 0.5 mm.

この接着部材４１は、樹脂系の接着剤を用いてもよいが、例えば、樹脂よりも熱伝導率に優れたはんだなどを用いることで、位置精度の向上に加えて放熱性をも向上させることができる。特に、変形能の高いはんだペーストを用いた場合には優れたセルフアライメント効果が得られる。   The adhesive member 41 may use a resin-based adhesive. For example, by using solder having a thermal conductivity higher than that of the resin, it is possible to improve heat dissipation in addition to improving the positional accuracy. Can do. In particular, when a solder paste having a high deformability is used, an excellent self-alignment effect can be obtained.

導体パターン１５は、図４（ａ）に示すように突起部９の平坦面９ａのほとんどを覆うように形成されていてもよく、あるいは突起部９の平坦面９ａの全面を覆っていてもよい。   The conductor pattern 15 may be formed so as to cover most of the flat surface 9a of the protruding portion 9 as shown in FIG. 4A, or may cover the entire flat surface 9a of the protruding portion 9. .

また、図４（ｂ）に示すように、導体パターン１５を突起部９の平坦面９ａに分割して形成した場合には、接着部材４１の表面積が増加するため、複合基板３７の表面積が増加し、複合基板３７の放熱性が向上する。   As shown in FIG. 4B, when the conductor pattern 15 is divided and formed on the flat surface 9a of the protrusion 9, the surface area of the adhesive member 41 increases, so the surface area of the composite substrate 37 increases. In addition, the heat dissipation of the composite substrate 37 is improved.

導体パターン１５の総面積は、セルフアライメント効果を向上させるために外部端子１１の総面積の１．２倍以上とすることが望ましく、さらに１．８倍以上、特に３倍以上とすることが望ましい。なお、この導体パターン１５の総面積とは導体パターン１５の主面の総面積を意味し、導体パターン１５の側面を除いた面積を指すものである。   In order to improve the self-alignment effect, the total area of the conductor pattern 15 is desirably 1.2 times or more of the total area of the external terminals 11, more preferably 1.8 times or more, and particularly preferably 3 times or more. . The total area of the conductor pattern 15 means the total area of the main surface of the conductor pattern 15 and refers to the area excluding the side surface of the conductor pattern 15.

この導体パターン１５の面積は、絶縁基板１の熱を放散するという観点から、絶縁基板突起部９の平坦面９ａのうち、４０％以上とすることが望ましく、特に５０％を越えることが望ましい。さらに、６０％以上とすることが望ましい。   The area of the conductor pattern 15 is preferably 40% or more of the flat surface 9a of the insulating substrate protrusion 9 from the viewpoint of dissipating heat of the insulating substrate 1, and more preferably exceeds 50%. Furthermore, it is desirable to set it as 60% or more.

また、導体パターン１５から接着部材４１へ伝わった熱が大気中に放散しやすいように、接着部材４１の表面積を大きくすることが望ましく、導体パターン同士の間には隙間があることが望ましい。導体パターン１５主面の面積は、絶縁基板突起部９の平坦面９ａのうち、９０％以下とすることが望ましく、さらに、８０％以下が望ましい。   Further, it is desirable to increase the surface area of the adhesive member 41 so that heat transferred from the conductor pattern 15 to the adhesive member 41 is easily dissipated into the atmosphere, and it is desirable that there is a gap between the conductor patterns. The area of the main surface of the conductor pattern 15 is preferably 90% or less of the flat surface 9a of the insulating substrate protrusion 9, and more preferably 80% or less.

また、一つの導体パターン１５と一つの外部端子１１の面積を個別に比較したとき、セルフアライメント効果を増大させる観点から導体パターン１５の面積を外部端子１１の面積よりも大きくすることが望ましく、１．２倍以上、さらに２倍以上、特に６倍以上とすることが望ましい。   Further, when the areas of one conductor pattern 15 and one external terminal 11 are individually compared, it is desirable to make the area of the conductor pattern 15 larger than the area of the external terminal 11 from the viewpoint of increasing the self-alignment effect. .2 times or more, more preferably 2 times or more, and particularly preferably 6 times or more.

また、周縁部７の厚みは、電気素子２３から外部端子１１までの距離を小さくして電気素子２３が発生する熱の放散を容易にするために、絶縁基板１の突起部の厚みよりも０．２ｍｍ以上小さいことが望ましく、さらに０．４ｍｍ以上小さいことが望ましい。また、周縁部７の厚みを薄くして、熱を放散することで、絶縁基板１と絶縁基板１を実装する外部回路基板との熱膨張差を緩和でき、且つ周縁部７に形成した配線層３から外部端子１１をつなぐ貫通導体１６をより短くすることができる。   Further, the thickness of the peripheral edge portion 7 is smaller than the thickness of the protruding portion of the insulating substrate 1 in order to reduce the distance from the electric element 23 to the external terminal 11 and facilitate the dissipation of heat generated by the electric element 23. Desirably smaller than 2 mm, further desirably smaller than 0.4 mm. Further, by reducing the thickness of the peripheral portion 7 to dissipate heat, the thermal expansion difference between the insulating substrate 1 and the external circuit board on which the insulating substrate 1 is mounted can be reduced, and the wiring layer formed on the peripheral portion 7 The through conductor 16 that connects the external terminal 11 to 3 can be made shorter.

上述した特徴を備えた本発明の配線基板２１を用いた複合基板３７では、放熱性を向上させることができるとともに、導体パターン１５と、絶縁基板１と接続する側の外部回路基板３５の主面３５ａに形成した接続端子３５ｃとをはんだなどの接着部材４１により接続することで、接着部材４１の溶融に伴うセルフアライメント効果により絶縁基板１の位置決めが容易になり、しかも位置精度が非常に高くなる。   In the composite substrate 37 using the wiring substrate 21 of the present invention having the above-described features, heat dissipation can be improved, and the main surface of the external circuit substrate 35 on the side connected to the conductor pattern 15 and the insulating substrate 1. By connecting the connection terminal 35c formed on 35a with an adhesive member 41 such as solder, the self-alignment effect accompanying melting of the adhesive member 41 facilitates positioning of the insulating substrate 1, and the positional accuracy is very high. .

また、絶縁基板１と外部回路基板３５とをはんだなどの金属で接続することができるので絶縁基板１の熱を効率よく伝達することも可能となる。   In addition, since the insulating substrate 1 and the external circuit substrate 35 can be connected by a metal such as solder, it is possible to efficiently transfer the heat of the insulating substrate 1.

また、絶縁基板１と外部回路基板３５との間にはんだなどの接着部材４１を置くことで、周縁部７に形成された外部端子１１と、外部回路基板３５に形成した接続端子３５ｃと、を接続する接着部材４１の高さをより高くすることができ、絶縁基板１と外部回路基板３５との熱膨張係数差により生じる局所的な熱応力歪みを接合部材３９で吸収することができる。   Also, by placing an adhesive member 41 such as solder between the insulating substrate 1 and the external circuit board 35, the external terminals 11 formed on the peripheral edge portion 7 and the connection terminals 35c formed on the external circuit board 35 are provided. The height of the bonding member 41 to be connected can be made higher, and the local thermal stress distortion caused by the difference in thermal expansion coefficient between the insulating substrate 1 and the external circuit substrate 35 can be absorbed by the bonding member 39.

この際、接着部材４１を置くことによって、絶縁基板１の突起部９の平坦面９ａに形成された導体パターン１５と接続パターン３５ｃとの距離は、セルフアライメント効果を高める点から、０．１ｍｍ以上であることが望ましく、さらに０．２ｍｍ以上が望ましい。また、複合基板全体の低背化と接合部材２３の高さの限界の観点から、０．５ｍｍ以下であることが複合基板３７の小型化の観点から好ましい。   At this time, by placing the adhesive member 41, the distance between the conductor pattern 15 formed on the flat surface 9a of the protrusion 9 of the insulating substrate 1 and the connection pattern 35c is 0.1 mm or more from the viewpoint of enhancing the self-alignment effect. It is desirable to be 0.2 mm or more. Further, from the viewpoint of reducing the overall height of the composite substrate and the limit of the height of the bonding member 23, the thickness is preferably 0.5 mm or less from the viewpoint of downsizing the composite substrate 37.

本発明においては、絶縁基板１として、例えば、ホウケイ酸ガラスセラミックス等のガラスセラミックス、石英ガラス、アルミナ、ムライト、窒化アルミニウム、窒化珪素、炭化珪素、窒化ホウ素等一般にセラミック配線基板用の絶縁基板材として用いられるセラミックスが好適に用いられる。   In the present invention, as the insulating substrate 1, for example, glass ceramics such as borosilicate glass ceramics, quartz glass, alumina, mullite, aluminum nitride, silicon nitride, silicon carbide, boron nitride, etc. The ceramic used is preferably used.

この絶縁基板１上に搭載する電気素子が、シリコン半導体チップ等である場合、熱膨張係数がシリコン（熱膨張係数４×１０−６／℃程度）のそれに近似し、高周波領域での誘電損失が小さく、更にパターン導体層の構成材である銅、銀、金等の高電気伝導率金属からなる導体層との同時焼成が可能な点からガラスセラミックスの使用が好ましく、その内でも特に、熱膨張係数が３〜６×１０−６／℃、比誘電率が７以下のものが好ましい。 When the electrical element mounted on the insulating substrate 1 is a silicon semiconductor chip or the like, the thermal expansion coefficient approximates that of silicon (thermal expansion coefficient of about 4 × 10 −6 / ° C.), and the dielectric loss in the high frequency region is low. It is preferable to use glass ceramics because it is small and can be co-fired with a conductor layer made of a metal having a high electrical conductivity such as copper, silver, or gold, which is a constituent material of the patterned conductor layer. Those having a coefficient of 3 to 6 × 10 −6 / ° C. and a relative dielectric constant of 7 or less are preferable.

接着部材４１としては、熱伝導性が高いものを使うことが望ましく、はんだが好適に用いられる。また、接着部材４１の形状は、柱状であればどのような形状でもよく、例えば半円状や円柱状のものが考えられる。   As the adhesive member 41, it is desirable to use a material having high thermal conductivity, and solder is preferably used. Further, the shape of the adhesive member 41 may be any shape as long as it is a columnar shape. For example, a semicircular shape or a cylindrical shape is conceivable.

外部回路基板３５の構成材としては、一般にガラス繊維強化樹脂基板、アラミド繊維強化エポキシ樹脂基板、アラミド繊維強化ポリイミド樹脂基板、紙・フェノール樹脂基板、ポリエステル樹脂基板などが用いられる。   As a constituent material of the external circuit board 35, a glass fiber reinforced resin substrate, an aramid fiber reinforced epoxy resin substrate, an aramid fiber reinforced polyimide resin substrate, a paper / phenol resin substrate, a polyester resin substrate, or the like is generally used.

これらの樹脂基板３５の熱膨張係数は、通常８〜１８×１０−６／℃の範囲である。 The thermal expansion coefficients of these resin substrates 35 are usually in the range of 8 to 18 × 10 −6 / ° C.

この外部回路基板３５の導体層構成材としては銅、銀、金などの他、アルミニウム、チタニウムの金属も用いることができる。 As the conductor layer constituting material of the external circuit board 35, aluminum, titanium, or the like can be used in addition to copper, silver, gold and the like.

接続部材３９としては、はんだなどが用いられ、比較的高融点のスズ−鉛系合金はんだが好適に使用される。   As the connection member 39, solder or the like is used, and a tin-lead alloy solder having a relatively high melting point is preferably used.

また、電気素子２３としては、例えば、シリコン単結晶薄片等よりなる集積回路チップ、ハイブリッドＩＣチップ、デスクリートチップ等或いはＳＡＷ（表面弾性波フィルター）素子等のデバイス素子が搭載される。   Further, as the electric element 23, for example, a device element such as an integrated circuit chip made of silicon single crystal flakes, a hybrid IC chip, a discrete chip, or a SAW (surface acoustic wave filter) element is mounted.

アルミナ粉末を主成分とするグリーンシートとＷ粉末を主成分とする金属ペーストとを用いて作製した成形体を１６００℃で焼成して、配線基板の外形寸法を１３ｍｍ×１３ｍｍ、突起部の外形寸法を９ｍｍ×９ｍｍ、周縁部の高さを０．６ｍｍとし、周縁部の厚みを表１のように変化させて図１に示すような平板の一方の側の主面に突起部が形成された配線基板を作製した。従って、これらの配線基板の厚みは、周縁部の高さ０．６ｍｍに表１に示す周縁部の厚みを加えた値となる。   A molded body produced using a green sheet mainly composed of alumina powder and a metal paste mainly composed of W powder is fired at 1600 ° C., so that the external dimensions of the wiring board are 13 mm × 13 mm, and the external dimensions of the protrusions. Is 9 mm × 9 mm, the height of the peripheral portion is 0.6 mm, and the thickness of the peripheral portion is changed as shown in Table 1 to form a protrusion on the main surface on one side of the flat plate as shown in FIG. A wiring board was produced. Therefore, the thickness of these wiring boards is a value obtained by adding the peripheral edge thickness shown in Table 1 to the peripheral edge height of 0.6 mm.

この配線基板の周縁部には０．８ｍｍ経の外部端子を等間隔に３２個形成した。   Thirty-two external terminals with a length of 0.8 mm were formed at equal intervals on the periphery of the wiring board.

また、突起部の主面には表１に示す形状の厚みが５０、１００、２００μｍの導体パターンを形成した。   In addition, conductor patterns having thicknesses of 50, 100, and 200 μm shown in Table 1 were formed on the main surface of the protrusions.

これらの外部端子、導体パターンはそれぞれＷ粉末を主成分とする金属ペーストをグリーンシートに印刷塗布して形成した。   These external terminals and conductor patterns were formed by printing and applying a metal paste mainly composed of W powder on a green sheet.

なお、比較例として作製した表１の試料Ｎｏ．１には、導体パターンを設けなかった。   In addition, sample No. of Table 1 produced as a comparative example. 1 was not provided with a conductor pattern.

次に、これらの配線基板に試験用の半導体素子を実装し、配線基板の配線層と半導体素子の電極とを金ワイヤを用いて電気的に接続した。さらに、配線層、金ワイヤならびに半導体素子を覆うように、エポキシ樹脂を主成分とするポッティング樹脂で被覆し、１５０℃の温度でポッティング樹脂を硬化させた。   Next, test semiconductor elements were mounted on these wiring boards, and the wiring layers of the wiring boards and the electrodes of the semiconductor elements were electrically connected using gold wires. Furthermore, the wiring layer, the gold wire and the semiconductor element were covered with a potting resin mainly composed of an epoxy resin, and the potting resin was cured at a temperature of 150 ° C.

次に、外部端子の表面にはんだペーストをディスペンサーを用いて塗布し、さらに、このはんだペーストに直径が０．９ｍｍのはんだボールを配置し、２５０℃でリフローして外部端子に接続端子を形成した。   Next, a solder paste was applied to the surface of the external terminal using a dispenser, and a solder ball having a diameter of 0.9 mm was placed on the solder paste and reflowed at 250 ° C. to form a connection terminal on the external terminal. .

このようにして作製した電気素子装置を外部回路基板に実装した。   The electrical element device thus fabricated was mounted on an external circuit board.

これらの電気素子装置のうち、試料Ｎｏ．１〜１５には導体パターンと外部回路基板との間には接着部材を設けなかった。   Among these electric element devices, sample No. In Nos. 1 to 15, no adhesive member was provided between the conductor pattern and the external circuit board.

接着部材を用いていない試料Ｎｏ．１〜１５の場合には、外部回路基板とはんだボールとの間にはんだペーストを配設した後、２５０℃でリフローして電気素子装置と外部回路基板とを接合して複合基板を作製した。   Sample No. using no adhesive member In the case of 1 to 15, a solder paste was disposed between the external circuit board and the solder balls, and then reflowed at 250 ° C. to join the electric element device and the external circuit board to produce a composite substrate.

一方、試料Ｎｏ．１６〜１３には導体パターンと外部回路基板との間に接着部材を配置した。   On the other hand, sample No. In 16 to 13, an adhesive member was disposed between the conductor pattern and the external circuit board.

接着部材を用いた試料Ｎｏ．１６〜１３の場合には、外部回路基板とはんだボールとの間にはんだペーストを配設するとともに、導体パターンと外部回路基板との間の距離が表１に示す値となるようにはんだペーストの塗布量を調節して配設した後、２５０℃でリフローして電気素子装置と外部回路基板とを接合して複合基板を作製した。   Sample No. using an adhesive member In the case of 16 to 13, the solder paste is disposed between the external circuit board and the solder ball, and the distance between the conductor pattern and the external circuit board is set to the value shown in Table 1 After the coating amount was adjusted and disposed, reflowing was performed at 250 ° C., and the electric element device and the external circuit substrate were joined to produce a composite substrate.

なお、セルフアライメント効果を確認するため、電気素子装置と外部回路基板とは、リフロー前の段階では予め電気素子装置の対角方向に４００μｍずれるように配設した後、リフローを行った。   In order to confirm the self-alignment effect, the electrical element device and the external circuit board were preliminarily disposed so as to be shifted by 400 μm in the diagonal direction of the electrical element device, and then reflowed.

以上の複合基板の作製過程において、放熱性を測定するための試料には試験用半導体素子の表面に０．２ｍｍ厚みのアルミナ基板を挟んで熱電対を配置しポッティング樹脂で固定した。   In the above-described composite substrate manufacturing process, a thermocouple was placed on the surface of the test semiconductor element with a 0.2 mm-thick alumina substrate sandwiched between the samples for measuring heat dissipation and fixed with a potting resin.

このようにして作製した複合基板を用いて、−４０℃〜１２５℃の温度サイクル試験を行った。なお、この温度サイクル試験は昇温、降温がそれぞれ５分、保持時間がそれぞれ２５分の条件で行った。   A temperature cycle test of −40 ° C. to 125 ° C. was performed using the composite substrate thus manufactured. This temperature cycle test was conducted under conditions where the temperature rise and fall were 5 minutes each and the holding time was 25 minutes each.

また、作製した複合基板は配線基板の対角線に沿って複合基板を切断し、その断面を研磨して、外部端子と、この外部端子に対向して設けられた外部回路基板の回路端子との位置ずれを測定して位置精度を確認した。   The prepared composite board is cut along the diagonal of the wiring board, the cross section is polished, and the positions of the external terminals and the circuit terminals of the external circuit board provided facing the external terminals are determined. The positional accuracy was confirmed by measuring the displacement.

また、放熱性については、２５℃の大気中で試験用の半導体素子に１０Ｗの電流を１時間通電した後の半導体素子表面の温度を熱電対を用いて測定して評価した。   The heat dissipation was evaluated by measuring the temperature of the surface of the semiconductor element after applying a current of 10 W to the test semiconductor element for 1 hour in the air at 25 ° C. using a thermocouple.

なお、いずれの試験もそれぞれ５個の試料を用いて測定し、その平均値を表１に記載したものである。   In addition, each test measured using 5 samples, respectively, and the average value is described in Table 1.

試験結果を表１に示す。   The test results are shown in Table 1.

なお、表１に記載した導体パターンの総面積とは絶縁基板の主面と略平行に形成された導体パターンの主面にあたる部分の総面積であって、導体パターンの側面にあたる部分の面積は考慮していない。また、外部端子の総面積についても同様の値を用いている。   The total area of the conductor pattern described in Table 1 is the total area of the portion corresponding to the main surface of the conductor pattern formed substantially parallel to the main surface of the insulating substrate, and the area corresponding to the side surface of the conductor pattern is considered. Not done. The same value is used for the total area of the external terminals.

また、導体パターン、外部端子の一つあたりの面積もそれぞれの主面のみについて求めた値である。   Further, the area per one of the conductor pattern and the external terminal is also a value obtained only for each main surface.

また、表１中の位置精度とは、外部端子と、この外部端子に対向して設けられた外部回路基板の回路端子との位置ずれに想到する値であり、１０μｍ単位で測定値を丸めている。

Figure 2007042848
In addition, the positional accuracy in Table 1 is a value conceived of a positional deviation between the external terminal and the circuit terminal of the external circuit board provided opposite to the external terminal, and the measured value is rounded to the nearest 10 μm. Yes.
Figure 2007042848

表１に示すように突起部の表面に導体パターンのない試料Ｎｏ．１では、半導体素子の冷却能力が低く、信頼性試験結果は２６００回に留まった。   As shown in Table 1, a sample No. with no conductor pattern on the surface of the protrusion was used. In 1, the cooling capacity of the semiconductor element was low, and the reliability test result was only 2600 times.

また、導体パターンを有するものの、導体パターンの総面積が外部端子の総面積よりも小さい試料Ｎｏ．２においても、半導体素子の冷却能力は若干向上するものの、信頼性試験結果は３０００回に留まった。   In addition, although the conductor pattern is included, the total area of the conductor pattern is smaller than the total area of the external terminals. In 2 as well, although the cooling capacity of the semiconductor element was slightly improved, the reliability test result was only 3000 times.

一方、導体パターンの総面積が外部端子の総面積よりも大きい本願発明の試料Ｎｏ．３〜１５では、半導体素子の温度が低くなり、冷却効率が優れていることがわかる。   On the other hand, Sample No. of the present invention in which the total area of the conductor pattern is larger than the total area of the external terminals. In 3-15, it turns out that the temperature of a semiconductor element becomes low and cooling efficiency is excellent.

また、その結果、絶縁基板と外部回路基板との間に発生する応力が小さくなり、信頼性試験結果は３６００回以上となり、高い信頼性を有することが判る。   As a result, the stress generated between the insulating substrate and the external circuit substrate is reduced, and the reliability test result is 3600 times or more, indicating that the device has high reliability.

また、接着部材を設けた試料Ｎｏ．１６〜３３のうち、導体パターンの総面積が外部端子の総面積よりも小さい試料Ｎｏ．１６と、導体パターンの総面積が外部端子の総面積よりも大きい本願発明の試料Ｎｏ．１７〜３３とを比較すると、本願発明の試料はいずれも試料Ｎｏ．１６よりも、冷却能力が高く、また、信頼性も優れていることがわかる。   Sample No. provided with an adhesive member. 16 to 33, sample No. 16 in which the total area of the conductor pattern is smaller than the total area of the external terminals. 16, and the total area of the conductor pattern is larger than the total area of the external terminals. 17 to 33, all the samples of the present invention are sample Nos. It can be seen that the cooling capacity is higher than 16, and the reliability is excellent.

本発明の配線基板の一形態を示す断面図。Sectional drawing which shows one form of the wiring board of this invention. 本発明の配線基板の一形態を示す断面図。Sectional drawing which shows one form of the wiring board of this invention. 本発明の電気素子装置の一形態を示す断面図。Sectional drawing which shows one form of the electric element apparatus of this invention. 本発明の複合基板の一形態を示す断面図。Sectional drawing which shows one form of the composite substrate of this invention. 本発明の複合基板の他の形態を示す断面図。Sectional drawing which shows the other form of the composite substrate of this invention. 従来の配線基板を示す断面図。Sectional drawing which shows the conventional wiring board. 従来の配線基板を示す断面図。Sectional drawing which shows the conventional wiring board. 従来の配線基板を示す断面図。Sectional drawing which shows the conventional wiring board.

符号の説明Explanation of symbols

１・・・絶縁基板
１ａ・・・絶縁基板の一方の主面
１ｂ・・・絶縁基板の他方の主面
３・・・配線層
５・・・搭載部
７・・・周縁部
９・・・突起部
９ａ・・・突起部の主面
１１・・・外部端子
１５・・・導体パターン
１６・・・貫通導体
１７・・・キャビティ
２１・・・配線基板
２３・・・電気素子
２５・・・電気素子装置
３５・・・外部回路基板
３５ｂ・・・回路端子
３５ｃ・・・接続パターン
３７・・・複合基板
３９・・・接続部材
４１・・・接着部材 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 1a ... One main surface 1b of an insulating substrate ... The other main surface 3 of an insulating substrate ... Wiring layer 5 ... Mounting part 7 ... Peripheral part 9 ... Protrusion 9a ... Projection main surface 11 ... External terminal 15 ... Conductor pattern 16 ... Through conductor 17 ... Cavity 21 ... Wiring board 23 ... Electrical element 25 ... Electrical element device 35 ... external circuit board 35b ... circuit terminal 35c ... connection pattern 37 ... composite board 39 ... connecting member 41 ... adhesive member

Claims (8)

絶縁基板と、該絶縁基板の表面または内部のうち少なくとも一方に形成された配線層と、前記絶縁基板の一方の主面に形成された電気素子搭載部と、前記絶縁基板の他方の主面の周縁部よりも内側に配置された頂部に平坦面を有する凸状の突起部と、前記周縁部に形成された外部端子と、前記突起部の平坦面に形成された導体パターンとを具備してなり、前記外部端子の総面積よりも前記導体パターンの総面積が大きいことを特徴とする配線基板。 An insulating substrate, a wiring layer formed on at least one of the surface or the inside of the insulating substrate, an electric element mounting portion formed on one main surface of the insulating substrate, and the other main surface of the insulating substrate Convex protrusions having a flat surface on the top disposed inside the peripheral edge, external terminals formed on the peripheral edge, and a conductor pattern formed on the flat surface of the protrusion. And the total area of the conductor pattern is larger than the total area of the external terminals. 前記導体パターンが、複数形成されていることを特徴とする請求項１記載の配線基板。 The wiring board according to claim 1, wherein a plurality of the conductor patterns are formed. 一つの前記導体パターンの面積が、一つの前記外部端子の面積よりも大きいことを特徴とする請求項２に記載の配線基板。 The wiring board according to claim 2, wherein an area of one conductor pattern is larger than an area of one external terminal. 前記突起部の平坦面のうち前記導体パターンが形成された面積が、残りの面積よりも大きいことを特徴とする請求項１乃至３のうちいずれかに記載の配線基板。 4. The wiring board according to claim 1, wherein an area of the flat surface of the protruding portion where the conductor pattern is formed is larger than a remaining area. 5. 請求項１乃至４のうちいずれかに記載の配線基板の前記電気素子搭載部に、電気素子を搭載したことを特徴とする電気素子装置。 An electric element device, wherein an electric element is mounted on the electric element mounting portion of the wiring board according to claim 1. 請求項５に記載の電気素子装置が、前記外部端子に対応する回路端子を有する外部回路基板に搭載されるとともに、前記外部端子と前記回路端子とが接続部材を介して接続されていることを特徴とする複合基板。 The electrical element device according to claim 5 is mounted on an external circuit board having a circuit terminal corresponding to the external terminal, and the external terminal and the circuit terminal are connected via a connection member. Characteristic composite substrate. 前記外部回路基板が、前記導体パターンに対応する接続パターンを有するとともに、前記導体パターンと前記接続パターンとが接着部材を介して接着されていることを特徴とする請求項６に記載の複合基板。 The composite substrate according to claim 6, wherein the external circuit board has a connection pattern corresponding to the conductor pattern, and the conductor pattern and the connection pattern are bonded via an adhesive member. 前記導体パターンと前記接続パターンとの距離が０．１〜０．５ｍｍであることを特徴とする請求項７に記載の複合基板。

The composite substrate according to claim 7, wherein a distance between the conductor pattern and the connection pattern is 0.1 to 0.5 mm.

JP2005225060A 2005-08-03 2005-08-03 Wiring board, electrical element device and composite board Expired - Fee Related JP4667154B2 (en)

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