JPH0992726A - Wiring method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress delay of signals by enlarging the interval between a clock wiring or a critical wiring and other wiring automatically when the wiring pattern of a gate array or a standard cell is determined, based on a net list. SOLUTION: A net of a clock signal or a critical path is searched for based on a net list (Step 105), a flag is affixed to a net thus obtained (Step 106), a flagged net is wired with a large width and the unflagged net is wired with normal width (Step 109) and then the wiring (wide wiring) of the flagged net is made thin (Step 112).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a logic integrated circuit such as a gate array or standard cell,
In particular, the present invention relates to a wiring method of a semiconductor device for determining a wiring pattern of each net from a given net list.

[0002]

2. Description of the Related Art In a so-called semi-custom type semiconductor logic integrated circuit such as a master slice type integrated circuit such as a gate array or a standard cell, an automatic placement and routing tool should be used based on a netlist output from a logic synthesis simulator or the like. Thus, the wiring pattern between the cells is determined. In recent years, the number of gates and cells in a gate array and standard cells has increased, and wiring patterns have become finer. As the wiring patterns become finer, parasitic capacitance (stray capacitance) between wirings also increases. The resulting signal delay cannot be ignored when operating at high speed.

Japanese Laid-Open Patent Publication No. 4-207071 discloses an improved gate array type integrated circuit in which a plurality of signal wiring patterns having the same width are arranged at substantially equal intervals, and the clock signal wiring and the adjacent clock signal wiring are provided. A technique for reducing the capacitance between the clock signal wiring and the adjacent wiring to reduce the wiring capacitance by suppressing the delay of the clock signal by making the wiring interval between the wiring and the signal wiring to be twice or more that of the other portion. Is disclosed. According to this technique, the variation in signal transmission time caused by the position of the clock signal wiring is suppressed, and the timing design is facilitated.

FIG. 7 is a plan view showing an example of a wiring layout determined by the automatic wiring technique disclosed in JP-A-4-207071. There are two layers of wiring here,
The wiring pattern extending in the horizontal direction in the drawing is the first layer, and the wiring pattern extending in the vertical direction in the drawing is the second layer. The first-layer wiring 31 and the second-layer wirings 41 and 42 are connected through the through holes 51 and 52 to form a series of clock signal wirings. Wirings 32 to 34 are provided in the first layer for general signals other than clocks,
Wirings 43 to 47 are provided on the second layer. Of these, the wiring 32 and the wiring 44 are connected via a through hole 53. 3A to 3E are channels for the automatic wiring program to arrange the signal wiring of the first layer in consideration of the clock signal wiring, and FIGS. 4A to 4H are the second layer in the same manner in consideration of the clock signal wiring. This is a channel for arranging the signal wiring of. In the first layer, general signal wirings 33 and 34 are arranged on both sides of the clock signal wiring 31, and the wiring distance d4 between the wirings 31 and 33 and the wiring 31
And the distance d5 between the wirings 34 are equal to each other. Further, the wiring distances d4 and d5 are twice the wiring distance d6 between two adjacent wirings (for example, the wirings 32 and 33) for general signals. Similarly, in the second layer, the clock signal wiring 41 and the normal signal wiring 4 on both sides thereof are provided.
Wiring intervals L4 and L5 with 3,44, and clock signal wiring 4
The wiring distances L6 and L7 between the wiring 2 and the normal signal wirings 45 and 46 on both sides thereof are each twice the wiring distance L8 between the normal signal wirings.

As described above, in the technique disclosed in Japanese Patent Laid-Open No. 207071/1992, the width and interval of the normal signal wiring are the minimum wiring width and the minimum wiring interval determined by the fine processing technique, respectively, The clock signal wirings are arranged so as to satisfy a wiring distance (larger than the minimum wiring distance) designated in advance with respect to the adjacent wirings. In this way, the capacitance between adjacent wirings associated with the clock signal wiring is reduced, and the delay of the clock signal and the blunting of the waveform are prevented.

[0006]

However, the above-mentioned Japanese Patent Application Laid-Open No. 4-207071 discloses the idea of increasing the wiring interval between the clock signal wiring and the other wirings to at least twice the normal spacing. No mention is made of how to increase the wiring interval in the actual automatic wiring. The automatic layout technology that has been conventionally applied to gate arrays and standard cells provides wiring grids at wiring intervals that are predetermined from the viewpoint of microfabrication technology, and uses this wiring grid to perform wiring indiscriminately. Therefore, it is not possible to easily realize the automatic generation of the layout in which the wiring interval is widened as it is.

In the above example, the wiring space is widened only for the clock signal wiring to reduce the parasitic capacitance.
Since there is a so-called critical path in which the conditions for signal delay are severe even in normal signal wiring, it is desirable to be able to automatically widen the wiring interval even for the critical path.

An object of the present invention is to provide a specific wiring method capable of widening a wiring interval between adjacent wirings with respect to clock wirings and critical paths during automatic layout of wiring patterns.

[0009]

A method of manufacturing a semiconductor device according to the present invention is a method of wiring a semiconductor device, which determines a wiring pattern of each net based on a net list of a circuit.
A first step of searching for a net carrying a signal which the user does not want to delay signal transmission based on the net list;
The second step of adding a flag to the net searched in the first step, and the wiring distance between the wiring of the net to which the flag is added and the wiring adjacent to the net is smaller than the wiring distance between normal wirings. The third step of laying out the wiring of each net so that

As the third step, specifically,
The layout of the wiring of each net is performed with the wiring of the flag added net as a thick width, and the layout of the thick width is performed at least when the layout of the wiring around the net of the flag is completed. Using the step of thinning to an arbitrary width, or laying out the wiring of the flag-added net in parallel with dummy wiring so as to sandwich the wiring of the flag-added net,
After laying out the wiring of other nets and finishing the layout of at least the wiring of the net to which the flag is added and the wiring of the dummy wiring, the step of removing the dummy wiring is used, or the net to which the flag is added is used. Using the step of laying out the wiring of the net to which the flag is added while giving priority to the wiring of other nets while automatically generating the adjoining prohibited area around the wiring of each net, and completing the layout of the wiring of each net. You can

In the present invention, a signal which is not desired to delay the signal transmission is, for example, a clock signal. In this case, the clock tree method is used in the first step to search for a net through which the clock signal is transmitted. be able to. Alternatively, the critical path may be searched for as a net of signals that the signal transmission is not desired to be delayed.

According to the present invention, when a signal net whose signal transmission is not desired to be delayed is searched for, for example, a clock wiring or a critical path net is added with a flag and the wiring of each net is laid out, the flag is set. Since the wiring interval between the added net (flagged net) and other wiring is set to be wider than the normal wiring mutual wiring, the wiring between clock wiring and critical path wiring and adjacent wiring The parasitic capacitance is reduced, and the delay of the signal passing through the clock and the critical path is reduced. Further, this layout process is automatically performed by an automatic placement and routing tool or the like.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >> FIG. 1 shows a first embodiment of the present invention.
5 is a flowchart showing the procedure of the wiring method of the semiconductor device in the embodiment. Here, the net of the clock wiring is searched from the net list, and the wiring interval between the clock wiring and the adjacent wiring is widened to execute the automatic layout. Of course, it can be applied not only to the clock wiring but also to widening the wiring interval between the critical path and the adjacent wiring.

First, a circuit design and a timing design are performed by a top-down method using a logic synthesis simulator,
Generate a circuit netlist. Then, the netlist is analyzed (step 101), and the transistor element portion is arranged using the automatic placement and routing tool (step 102). Subsequently, a cluster of flip-flops is formed using the clock tree method (step 103),
Insert a clock tree buffer for optimal clock distribution (step 104). At this time, since the buffer is inserted, the net list is updated, and the buffer name for the clock tree and the new net name are added.
Then, the net through which the clock is transmitted (clock wiring) is searched from the updated net list (step 105), and a flag is added to the searched net (step 106).
Pass these wiring information to the automatic place and route tool. If the layout is performed after the back annotation, the critical path is extracted based on the back annotation result in step 105, and step 106 is executed.
In the above, a flag may be added to the extracted critical path. A flag may be added to both the clock wiring and the critical path. The critical path is extracted, for example, by searching for a path that does not satisfy the given delay time condition.

In the automatic placement and routing tool, first, a flagged net is detected from the delivered wiring information (step 107). Then, the wiring width is input to lay out the detected net with a wide width (step 10).
8) The flagged nets are laid out in this wide width, and the non-flagged nets are laid out in the normal width (step 109). Then, it is determined whether the layout of all wirings is completed (step 110). If not completed, step 109 is repeatedly executed. If completed, the wirings laid out with a wide width are finely divided. Input the narrowing width to narrow it to the desired width within the constraints of the processing technology (Step 1
11) After that, the wiring (clock wiring or the like) laid out with a thick width is thinned to a thin width (step 112).

FIG. 2 shows an example of the layout when wiring is performed in this way. Here, two layers of wiring are provided, the wiring pattern extending in the horizontal direction in the drawing is the first layer, and the wiring pattern extending in the vertical direction in the drawing is the second layer. The wirings 10 to 14 are arranged on the first layer, and the wirings 20 to 29 are arranged on the second layer. Of these wirings, the wiring 21, the wiring 11, and the wiring 29 are connected to form a clock wiring, and the other wirings are used for general signal transmission. The square “□” in the drawing indicates that the wiring of the first layer of the hole and the wiring of the second layer are connected therethrough through. 1A to 1D are channels for the automatic wiring program to arrange the signal wiring of the first layer in consideration of the clock signal wiring, and 2A to 2H in the drawings.
Is a channel for similarly arranging the second-layer signal wiring in consideration of the clock signal wiring.

In the present embodiment, the wirings 21, 11, 29 correspond to the flagged net, and the other wirings 10, 12-
14, 20, 22 to 28 correspond to nets without flags.
Therefore, first, the automatic net placement and routing tool recognizes the flagged net as a thick wiring A (dotted line in the figure) that extends over three grids, and in this state the wiring of each net is laid out. Therefore, the wide wiring A and the wirings 10, 12 to 14, 20, 22 to 28 having the normal width are mixed. At this time, in the first layer, the wiring interval d1 between the normal-width wirings and the wiring interval d2 between the normal-width wirings and the wide-width wiring A become equal, and in the second layer, the wiring interval L3 between the normal-width wirings. And normal width wiring and thick wiring A
The wiring interval L2 is equal to. These wiring intervals d
All 1, d2, L2, and L3 are intervals that are uniformly determined from the conditions in the microfabrication technology. Then, when the thick wiring A is thinned to a normal wiring width, as shown in the drawing, the continuous wirings 21, 11, and 29 are removed in the normal wiring state with one wiring on both sides thereof removed. Arranged according to the wiring width. In the first layer, the wiring distance d3 between the wiring 11 of the flagged net and the general signal wiring 14 is the wiring distance d between the normal wirings.
1 or more, and the wiring distance L1 between the wiring 21 of the flagged net and the general signal wiring 20 in the second layer is twice or more than the wiring distance L3 between the normal wirings. ing. This allows clock wiring (wiring 2
The delay of the clock transmitted through (1, 11, 29) is suppressed.

<< Second Embodiment >> FIG. 3 shows a second embodiment of the present invention.
5 is a flowchart showing the procedure of the wiring method of the semiconductor device in the embodiment. In this embodiment, the layout is performed so that the dummy wirings are provided on both sides of the clock wiring or the critical path, and the dummy wirings are removed after the layout is completed, so that the distance between the clock wiring or the critical path and the normal wiring is widened. The obtained wiring layout is obtained.

First, steps 201 and 202 are performed by the same procedure as steps 101 to 107 of the above-described first embodiment.
07 is executed and detection of a flagged net is performed. Then, the number of dummy wirings to be arranged on both sides of the flagged net is input (step 208). Subsequently, the flagged net, the dummy wiring, and the non-flagged net are laid out in the normal width (step 209). At this time, for each layer in which the flagged nets are arranged, the flagged nets are always sandwiched by dummy wirings from both sides, and no wiring other than the dummy wirings is interposed between the flagged nets and the dummy wirings. Place flagged nets and dummy wiring. The number of dummy wirings arranged on each side of the flagged wiring is the number input in step 208. The wiring distance between the dummy wiring and the wiring of the flagged net, and the wiring distance between the dummy wiring and the normal wiring adjacent thereto are the same as the wiring distance between the normal wirings. And
It is judged whether the layout of all wiring is completed (Step 2
10) If not completed, step 209 is repeated, and if completed, only dummy wiring is deleted (step 211).

FIG. 4 shows an example of a layout in which wiring is performed in this manner. Here, two layers of wiring are provided as in the case of FIG. The number of dummy wirings arranged on each side of the wiring of the flagged net is one. The difference from the example shown in FIG. 2 is that a bundle of three wirings consisting of wirings 21, 11 and 29 of a flagged net and a pair of dummy wirings B and C provided in parallel so as to sandwich the wirings are provided. The point is that the automatic placement and routing tool recognizes and lays out in this state to place a bundle of three wirings in place of the wide area, and then the dummy wirings B and C are removed. The wiring distance d2 between the dummy wiring and the normal wiring in the first layer is equal to the wiring distance d1 between the normal wirings. Therefore, the wiring distance d3 between the wiring of the flagged net and the normal wiring after the dummy wiring is removed is the normal wiring distance d3. Wiring interval d1
It is more than twice that. Similarly, the wiring distance L2 between the dummy wiring and the normal wiring in the second layer is equal to the wiring distance L3 between the normal wirings, and the wiring distance L1 between the flagged net wiring after the dummy wiring is removed and the normal wiring is the normal wiring distance L1. It is more than twice the wiring interval L3. After all, as shown in FIG. 4, the wiring layout similar to that of the first embodiment (see FIG. 2) is obtained by the second embodiment.

<< Third Embodiment >> FIG. 5 shows a third embodiment of the present invention.
5 is a flowchart showing the procedure of the wiring method of the semiconductor device in the embodiment. In this embodiment, when laying out the clock wiring and the wiring of the critical path, these wirings are laid out with priority over other wirings while automatically generating the adjoining prohibited area around these wirings. As a result, a wiring layout in which the distance between the clock wiring or the critical path and the normal wiring is widened can be obtained.

First, steps 301 to 301 are performed by the same procedure as steps 101 to 107 of the above-described first embodiment.
07, the detection of the flagged net is performed, and the width of the adjoining prohibited area is input (step 30).
8). Then, the wiring of the flagged net is preferentially arranged one by one while automatically generating the adjacent prohibition area in the layer corresponding to the wiring (step 30).
9). The width of the adjacent prohibition area is the width that has been input previously. When the wiring layout of all the flagged nets is completed, the unflagged nets are wired next (step 310).

FIG. 6 shows an example of a layout in which wiring is carried out in this way, and here two layers of wiring are carried out as in the case of FIG. Flagged net wiring 2
By laying out 1, 11, 29 preferentially, and further generating the wiring prohibited area (adjacent prohibited area) D on the same layer around the wires 21, 11, 29 of these flagged nets,
The spacing between the flagged net wiring and the normal signal wiring is widened, and as a result, a layout equivalent to that shown in FIG. 2 is realized. In FIG. 6, the wiring prohibited area D is an area surrounded by a shaded frame. As shown in the figure, the wiring distance d3 between the wiring of the flagged net and the normal wiring in each layer,
L3 is 2 of the wiring interval d1 and L1 of the normal wiring, respectively.
More than doubled.

[0025]

As described above, according to the present invention, a clock signal wiring or a net of a critical path is searched for and a flag is added to the flagged net. By accommodating wiring or setting a wiring prohibited area in the vicinity to perform layout, then by thinning, removing dummy wiring, etc.,
Only the wiring interval around the clock signal wiring and the critical path can be automatically widened, and the delay of the clock signal and the signal propagating through the critical path can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart showing a process of automatic placement and routing according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a layout example according to the first embodiment.

FIG. 3 is a flowchart showing processing of automatic placement and routing in the second embodiment.

FIG. 4 is a plan view showing a layout example according to the second embodiment.

FIG. 5 is a flowchart showing a process of automatic placement and routing in the third embodiment.

FIG. 6 is a plan view showing a layout example according to a third embodiment.

FIG. 7 is a plan view showing a layout example according to a conventional automatic wiring technique.

[Explanation of symbols]

10-14, 20-29 wiring 1A-1D, 2A-2H wiring channel A thick wiring B, C dummy wiring D wiring prohibited area 101-112, 201-211, 301-310
Steps

Claims (6)

[Claims] 1. A wiring method of a semiconductor device for determining a wiring pattern of each net based on a net list of a circuit, wherein a net through which a signal is desired to be delayed is transmitted based on the net list. A first step; a second step of adding a flag to the net searched in the first step; and a normal wire spacing between the wire of the flagged net and an adjacent wire. And a third step of laying out the wiring of each of the nets so that the wiring spacing is larger than the mutual wiring spacing. 2. A wiring method for a semiconductor device, which determines a wiring pattern of each net based on a net list of a circuit, wherein a net through which a signal is desired to be delayed is transmitted based on the net list. A first step; a second step of adding a flag to the net searched in the first step; and a layout of each net with the wiring of the net to which the flag is added being a wide width, The wiring of the semiconductor device, which comprises a third step of thinning the wiring laid out in the thick width into an arbitrary width at least when the layout of the wiring around the wiring of the net to which the flag is added is completed. Method. 3. A wiring method for a semiconductor device, wherein a wiring pattern of each net is determined based on a net list of a circuit, wherein a net through which a signal is desired to be delayed is searched based on the net list. A first step, a second step of adding a flag to the net searched in the first step, and a state in which dummy wiring is provided in parallel so as to sandwich the wiring of the net to which the flag is added. At this point, the wiring of the net to which the flag is added is laid out, the wiring of other nets is laid out, and at least when the layout of the wiring of the net to which the flag is added and the wiring around at least the dummy wiring is completed, A third step of removing the dummy wiring, and a wiring method for a semiconductor device. 4. A wiring method of a semiconductor device for determining a wiring pattern of each net based on a net list of a circuit, wherein a net carrying a signal which is not desired to be delayed is searched for based on the net list. A first step; a second step of adding a flag to the net searched for in the first step; and a step of automatically generating an adjacency prohibited area around the wiring of the net to which the flag is added. The wiring of the net to which the flag is added is laid out with priority over the wiring of other nets, and the layout of the wiring of each net is completed.
And a wiring method for a semiconductor device. 5. The wiring method for a semiconductor device according to claim 1, wherein the signal that is not desired to delay the signal transmission is a clock signal. 6. The wiring method for a semiconductor device according to claim 5, wherein a net through which the clock signal is transmitted is searched by using a clock tree method in the first step.