JP2004240838A - Method for designing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for quickly controlling crosstalk by extracting a parasitic element generated between wires in accordance with request accuracy and bypassing the parasitic element while considering an arrangement area or a wiring route at automatic arrangement/wiring and to provide a method for designing the semiconductor device. <P>SOLUTION: After temporarily wiring all networks by a temporary wiring process 100, a parasitic element generated between wires is extracted in accordance with wiring density by a wiring density extraction process 101, and in determining a wiring route in a wiring route determination process 104 by dividing the whole target wires like a grating and setting a coefficient calculated on the basis of a previously prepared parasitic element table 103 in a parasitic element coefficient setting process 102, a layout reducing the influence of crosstalk can be quickly obtained at necessary and sufficient accuracy by wiring networks while considering complicated crosstalk causality (e.g. strength of crosstalk received from another network or applied to another network). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for automatically arranging and wiring a semiconductor integrated circuit (hereinafter abbreviated as LSI), and more particularly to a technique effective for suppressing crosstalk generated between wiring signals.
[0002]
[Prior art]
In recent years, with the progress of manufacturing technology, with the advancement of the manufacturing technology, the circuit width has become smaller, the wiring size has been increased, and the operation speed has been increased. The parasitic capacitance generated between the upper and lower layers increases due to the thinning between the wirings and the interlayer insulating film, and the mutual connection between the signal lines via the parasitic element generated between the signal lines arranged in parallel or in close proximity during automatic placement and wiring. There is a problem that interference (hereinafter abbreviated as crosstalk) causes a malfunction and causes deterioration in reliability and quality of the LSI.
[0003]
In the prior art, parasitic elements with the same accuracy are extracted by the same method for the chip or the lock as a target at the time of automatic placement and routing (for example, see Patent Document 1). In addition, in order to verify a particularly important signal line, for example, a clock signal or a data bus signal line, with high accuracy, a parasitic element of a layout is extracted (hereinafter abbreviated as LPE) and only a net of interest is extracted from a net list (circuit connection information file). The operation is verified using simulation or the like, and the process of feeding back the problematic part to the automatic placement and routing is repeated until the normal operation is confirmed. For this reason, when the circuit becomes large-scale and complicated, one verification time of the entire process is long and it is necessary to repeat the verification many times.
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. Hei 9-147009 (page 20, FIG. 23)
[0005]
[Problems to be solved by the invention]
In the prior art, processing time becomes extremely enormous when crosstalk generated between wirings is considered with high precision, and a target signal line (here, length L) is considered in a realistic processing time as shown in FIG. If only possible multilayer capacitances 900 shown in FIG. 12, for example, are narrowed down, a sufficient result cannot be obtained in confirming waveform distortion and minute fluctuation.
[0006]
Further, verifying the mutual interference between digital signal lines having different phases, between digital and analog signals, and between different types of analog signal lines requires checking the digital signal level ('H', 'L', 'Z') and the signal level. Considering only the propagation time is not sufficient, and it is necessary to verify waveform distortion and minute fluctuations (on the order of 0.1 mV). For this reason, LPE is performed with high accuracy and the waveform after layout is verified using a SPICE simulator in order to confirm that it operates correctly. However, a simulation time of two digits or more is required as compared with a digital simulator. Since the repetition between the layout process or the circuit design process for feeding back the result is performed over a long period of time and involves fine adjustment, it is required to be performed many times, which requires enormous man-hours and time.
[0007]
In order to shorten the development period of LSI and improve the reliability and quality, it is necessary to consider only the difference in the frequency of signal change between wirings and the influence of the parasitic capacitance generated between signals having different phases and signal lines maintaining a constant potential. Highly accurate avoidance of crosstalk by taking into account thinning of the interlayer insulating film and wiring film at the stepped portion generated in the manufacturing process, differences in the depth of focus in lithography, and changes in the wiring width due to light reflection from nearby wiring. It needs to be controlled.
[0008]
As described above, in the conventional technology, there is a technology designed to consider a part of the parasitic capacitance. However, there is a problem that a processing speed is reduced when the accuracy is increased. However, a phenomenon in which the waveform is disturbed by the influence of noise such as a signal change waveform being shifted back and forth or distorted due to crosstalk generated between signal lines which are arranged in parallel or in parallel in an analog manner, or a manufacturing process. In the layout process, there is no technique to consider the effect on crosstalk due to the thinning of the interlayer insulating film or wiring film at the stepped portion caused by the step, the difference in the depth of focus in lithography, and the change in the wiring width due to the proximity effect of light in the layout process. Was.
[0009]
The present invention has been made in view of the above circumstances, and has as its object to provide a highly accurate and highly reliable semiconductor device.
[0010]
[Means for Solving the Problems]
The method of designing a semiconductor device according to the present invention includes a step of temporarily wiring, a step of extracting a wiring density from a wiring result, a parasitic element coefficient setting step of setting a weight of a parasitic element as a coefficient for each region, and a wiring path. A search step; and a correction step based on the coefficient of the parasitic element during actual wiring.
[0011]
For example, based on the netlist information, all the nets are provisionally routed at the shortest distance, and from the result, the distribution of parasitic elements and the wiring density generated between the wirings of the multilayer pattern which is parallel to each other or overlapped in the upper layer or lower layer are calculated. Then, for example, oversizing a logical product (AND) portion between wiring layers by a certain amount and then performing a logical sum (OR) to form one wiring density figure is repeated for each wiring layer.
[0012]
Next, based on the parasitic element table previously set by the wiring shape, the wiring density, and the parallel or multi-layer pattern of the wiring alone or in combination, the wiring density graphic is compared with the wiring density graphic or the wiring density graphic matches the parasitic element table. And subdivide it.
[0013]
After that, the parasitic element table is checked and the weight of the parasitic element is determined as a coefficient. The chip or block to be wired is further divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is set as a coefficient in each grid.
[0014]
Next, while referring to the parasitic element coefficient in a wiring order set in advance between pins for each net or for the entire net, a plurality of wiring paths are searched, and an optimum path is selected and wired.
[0015]
In addition, when the weight of the parasitic element is set as a coefficient, the wiring film thickness and the interlayer insulating film with the lower layer are thinned at the step due to the influence of the lower layer, for example, a polysilicon wiring layer or a diffusion layer (diffusion), and the parasitic thickness is reduced. Since the capacitance value changes (parasitic capacitance with the lower layer increases due to a decrease in interlayer insulation film thickness, and coupling capacitance between lines decreases due to a decrease in wiring film thickness), steps are extracted and set for each lattice. Correcting (increase / decrease) the coefficient of the parasitic element. The step portion is extracted by, for example, obtaining the logical product of the wiring and the lower layer and oversizing.
[0016]
Further, when the weight of the parasitic element is set as a coefficient, a portion where the wiring width changes due to the proximity effect of light at the time of lithography but the wiring is close is extracted in the wiring thinning portion extracting step due to the density of the wiring interval. At the time of this extraction, for example, a method is employed in which each wiring is oversized and then obtained by a logical product. Then, the coefficient of the parasitic element set in each lattice is increased or decreased and corrected.
[0017]
In addition, based on the netlist, a search is performed using a clock pin of a cell that has been made into a cell in advance as a base, and a clock system is automatically analyzed. Is automatically analyzed and extracted as a circuit group, and an arrangement area is set and arranged for each circuit group.
[0018]
Next, while determining the wiring group for each circuit group, the order of the wiring group is determined, and the extraction accuracy of the parasitic element is switched for each net group.
[0019]
Further, based on the attributes of the net, for example, a group of nets is extracted based on the level of sensitivity to receive crosstalk and the frequency and strength of giving crosstalk (noise source), and a layout area is set and arranged for each net group. .
Furthermore, when searching for a plurality of wiring paths, another net group existing in a wiring path of a net that straddles the net group is taken into consideration, and a route that minimizes the influence of crosstalk is bypassed.
[0020]
In addition, by changing the size of the lattice so as to satisfy the required extraction accuracy of the parasitic element, and extracting the portion where the accuracy is not required with low accuracy, high-precision and high-speed extraction can be performed as required.
[0021]
By the above alone or in combination, high-speed wiring can be performed with the extraction accuracy of the parasitic element according to the requirement of the crosstalk control set for each net.
[0022]
Further, the semiconductor device formed by the above design method has reduced crosstalk and high reliability.
[0023]
Furthermore, according to a program for causing a computer to execute a semiconductor device design method based on the above design method, the amount of calculation is reduced, and a design with high accuracy and low crosstalk can be performed.
[0024]
In addition, according to a computer-readable recording medium on which a program for causing a computer to execute the above-described design method is recorded, a design with high accuracy and little crosstalk can be performed at high speed.
[0025]
It is to be noted that division into regions can be appropriately adopted, such as a method of dividing into a lattice region or a method of dividing a frame region and a central portion around a chip.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the operation of an example of the embodiment will be described with reference to the drawings.
[0027]
(Embodiment 1)
As shown in FIG. 1, the semiconductor device design method according to the present invention includes a step 100 of temporarily laying out wiring from netlist information, a step 101 of extracting a wiring density from the wiring result, and A parasitic element coefficient setting step 102 for setting the weight of the parasitic element as a coefficient from the parasitic element table 103 with reference to the parasitic element table 103 based on the defeat density of the Correcting 105 based on the coefficient of the element and wiring.
[0028]
That is, in the tentative wiring step 100, all nets are tentatively wired with the shortest distance from the net list information, and the distribution of the parasitic elements and the wiring density generated between the wirings which are parallel or overlapped for each wiring layer are determined from the result. Calculated at 101. Here, for example, as shown in FIGS. 2A to 2C, a region obtained by performing a logical sum (OR) after oversizing a logical product (AND) part between wiring layers by a certain amount is defined as one wiring density figure. Is repeated for each wiring layer.
[0029]
Here, the regions 200 and 201 are considered, and the first-layer wiring 204 and the second-layer wiring 203 formed on the first-layer wiring 204 are arranged in these regions. The connection between the first layer wiring 204 and the second layer wiring 203 is made via a contact hole (FIG. 2A).
[0030]
Then, as shown in FIG. 2B, a logical product (AND) portion between the wiring layers is obtained between the plane direction and the vertical direction (other layers).
Then, as shown in FIG. 2C, a logical sum (OR) is obtained after oversizing by a certain amount. Here, 206 is a region having the largest wiring density and the largest parasitic capacitance, 208 is a region having the smallest wiring density and the smallest parasitic capacitance, and 207 and 209 are intermediate regions.
[0031]
Next, in the parasitic element coefficient setting step 102, the wiring density graphic is compared with the wiring density graphic or the wiring density graphic based on the parasitic element table 103 which is previously set individually or in combination of the wiring shape, the wiring density, and the parallel or multilayer pattern of the wiring. Is subdivided so as to match the parasitic element table and then collated.
[0032]
Then, the weight of the parasitic element is determined as a coefficient. For example, a block (chip or block) to be wired as shown in FIG. 2D is divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is assigned to each grid. Set as a coefficient.
[0033]
Next, a plurality of wiring paths are searched in a wiring path searching step (104) as shown in FIG. 2E while referring to the parasitic element coefficients in a wiring order set between pins for each net or in the entire net in advance. Then, by selecting an optimum route according to the degree of necessity and wiring (wiring step 105), high-speed wiring can be performed with necessary and sufficient accuracy.
[0034]
Here, it is clear that it is desirable to take the path 263 rather than the path 262 to reach the point 261 from the point 260.
[0035]
(Embodiment 2)
In this embodiment, as shown in FIG. 3, after the parasitic element coefficient is set in the parasitic element coefficient setting step in the same manner as in the first embodiment, the weight coefficient of the parasitic element is determined in consideration of the influence of the parasitic capacitance due to the lower layer of the wiring. It is characterized in that it is corrected.
[0036]
That is, a step 311 of extracting the state of the lower layer in the wiring step extracting step 310, extracting the position of the step and the size of the step, and correcting the parasitic element coefficient based on the extracted value is provided.
[0037]
Here, as in the first embodiment, as shown in FIG. 3, as shown in FIG. 3, all the nets are provisionally wired with the shortest distance in the provisional wiring step 100. The distribution and the wiring density are calculated in a wiring density extraction step (101).
Similarly, as shown in FIGS. 2A to 2C, a region obtained by oversizing a logical product (AND) portion between wiring layers by a certain amount and then performing a logical sum (OR) is one wiring density pattern. Is repeated for each wiring layer.
[0038]
Next, in the parasitic element coefficient setting step (102), the wiring density, the wiring density, and the wiring density are collated with the wiring density figure based on the parasitic element table set individually or in combination of each of the wirings in parallel or in a multilayer pattern. The figure is subdivided so as to match the parasitic element table and then collated to determine the weight of the parasitic element as a coefficient (103).
[0039]
For example, as shown in FIG. 2D, a chip or a block to be wired is divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is used as a coefficient for each grid. Set.
[0040]
Here, as shown in FIG. 4A, the wiring film thickness 300 and the interlayer insulating film with the lower layer are reduced in thickness at the step portion 302 due to the influence of the lower layer (for example, the polysilicon 301 or the diffusion layer in FIG. 4). Consideration is given to the fact that the parasitic capacitance value changes (parasitic capacitance with the lower layer increases as the interlayer insulating film thickness decreases, and coupling capacitance between lines decreases as the wiring film thickness decreases).
[0041]
Here, as shown in FIG. 3, in the wiring step extracting step 310, a step 303 caused by the intersection between these steps is extracted from 203 and 204 in FIG. 4B (for example, by logical AND of 203 and 204 and oversizing). Is calculated), and the coefficient of the parasitic element set in each lattice in the parasitic element coefficient correction step 311 is increased or decreased.
[0042]
Next, a plurality of wiring paths are searched for in the wiring path search step 104 as shown in FIG. By selecting a proper path according to the necessity and wiring in the wiring step 105, wiring can be performed at high speed with necessary and sufficient accuracy.
[0043]
(Embodiment 3)
The design method of the present embodiment is characterized in that, in the parasitic element coefficient setting step, a step of correcting a weight coefficient of the parasitic element in consideration of a change in wiring width during lithography is included.
[0044]
In this method, as shown in FIG. 5, in a tentative wiring step 100, all nets are tentatively routed with the shortest distance, and from the result, the distribution of the parasitic elements and the wiring density generated between the parallel or overlapping wirings for each wiring layer are determined. An area calculated by the extraction process 101 and obtained by over-sizing a logical product (AND) portion between wiring layers by a certain amount as shown in FIGS. The process of forming a wiring density figure is repeated for each wiring layer.
[0045]
Next, as shown in FIG. 5, in the parasitic element coefficient setting step 102, the wiring density, the wiring density, and the wiring density pattern are set based on the parasitic element table 103, which is set individually or in combination with each of the parallel or multilayer patterns of the wiring. Or the wiring density figure is subdivided so as to match the parasitic element table and then collated to determine the weight of the parasitic element as a coefficient.
[0046]
For example, a chip or a block to be wired as shown in FIG. 2D is divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is set as a coefficient for each grid. I do.
[0047]
Next, the wiring width changes due to the proximity effect of light at the time of lithography due to the density of the wiring intervals. As shown in FIG. 6, a portion 400 where wirings are close to each other is extracted in the wiring thinning portion extraction step 410 in FIG. After oversizing each of the 203, the logical product is obtained), and the parasitic element coefficient set in each lattice in the parasitic element coefficient correction step 411 is increased or decreased. Normally, the wiring width is reduced due to the thinning of the wiring, so that the parasitic capacitance is also reduced. Therefore, the coefficient of the parasitic element is also reduced.
[0048]
Next, referring to the parasitic element coefficient in the wiring order set in advance between the pins for each net or for the entire net, the wiring path as shown in FIG. 2E and the wiring path searching step as shown in FIG. A plurality of routes are searched at 104 and an optimum route is selected according to the necessity, and wiring is performed at a wiring step 105.
[0049]
In this way, high-speed wiring can be performed with necessary and sufficient accuracy.
[0050]
Further, a semiconductor device is formed according to the designed values designed in this manner.
[0051]
(Embodiment 4)
The method according to the present embodiment is characterized in that a net group is extracted from connection information of a net list, an arrangement area is set and arranged for each group, and a wiring route is searched and wired for each group. It is.
[0052]
That is, as shown in FIG. 7, in the circuit group extraction step 511, a search is performed based on the clock pin of a cell previously formed in the circuit group extraction step 511 based on the netlist 510, the clock system is automatically analyzed, and the search is performed based on the external terminal. The flow of signals and the direction of signal flow are automatically analyzed and extracted as circuit groups, and placement areas 500 and 501 are set for each circuit group in a placement area setting step 512 as shown in FIG. I do.
[0053]
Next, the order of groups to be wired is determined in a wiring group determination step 514 for each circuit group.
[0054]
Next, all the nets are provisionally wired with the shortest distance in the provisional wiring step 100 for each wiring group. From the result, the distribution of the parasitic elements and the wiring density generated between the wirings which are parallel or stacked for each wiring layer are determined in the wiring density extraction step 101. calculate.
[0055]
Here, as shown in FIGS. 2A to 2C, for example, a region obtained by performing a logical sum (OR) after oversizing a logical product (AND) portion between wiring layers by a certain amount is defined as one wiring density figure. Is repeated for each wiring layer.
[0056]
Next, as shown in FIG. 7, in the parasitic element coefficient setting step 102, the wiring density figure and the wiring density are determined based on the parasitic element table previously set individually or in combination of each of the wiring shape, the wiring density, and the wiring parallel or multilayer pattern. After collation or the wiring density figure is subdivided so as to match the parasitic element table 103, collation is performed and the weight of the parasitic element is determined as a coefficient.
[0057]
For example, a chip or a block to be wired as shown in FIG. 2D is divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is set as a coefficient in each grid. I do.
[0058]
Next, referring to the parasitic element coefficient in a wiring order set in advance between pins for each net or for the entire net, a plurality of wiring paths are searched as shown in FIG. In step 104, a plurality of routes are searched, and an optimum route is selected according to the necessity, and wiring is performed in a wiring step 105.
[0059]
Next, the completion of the wiring of the circuit group is determined in the wiring group end determination 515, and the extraction accuracy of the parasitic element is switched in the wiring density extraction step 101 repeatedly for each net group until the wiring in the same group is completed. High-speed wiring with the required accuracy.
[0060]
(Embodiment 5)
The method of designing a semiconductor device according to the present embodiment extracts a net group from connection information of a net list based on a net attribute, sets and arranges an arrangement area for each group, and searches and routes a wiring route for each group. It is characterized by having done.
[0061]
That is, as shown in FIG. 9, a search is performed using a clock pin of a cell that has been made into a cell in advance in a net group extraction step 612 based on a net list 611, a clock system is automatically analyzed, and an external terminal is used as a base. And automatically analyzes the signal flow, the signal flow direction, etc., and extracts it as a circuit group.
[0062]
Here, a group of nets is further extracted from the net attributes 610 based on the level of sensitivity to receive crosstalk and the frequency and intensity of crosstalk (noise source), for example, and the area to be arranged in the net area setting step 613. Set.
[0063]
Then, in an arrangement step 513, circuits belonging to the net group are arranged in the net area.
[0064]
After that, the order of groups to be wired is determined in the wiring group determination step 514 for each net group, and all nets are provisionally wired with the shortest distance in the temporary wiring step 100.
[0065]
Then, from the result, the distribution of parasitic elements and the wiring density generated between the wirings which are parallel or overlapped for each wiring layer are calculated in a wiring density extracting step 101.
[0066]
Here, as shown in FIGS. 2A to 2C, for example, a region obtained by performing a logical sum (OR) after oversizing a logical product (AND) portion between wiring layers by a certain amount is defined as one wiring density figure. Is repeated for each wiring layer.
[0067]
Next, in the parasitic element coefficient setting step 102, the wiring density graphic is compared with the wiring density graphic or the wiring density graphic based on the parasitic element table 103 which is previously set individually or in combination of the wiring shape, the wiring density, and the parallel or multilayer pattern of the wiring. Is subdivided so as to match the parasitic element table, and then collated to determine the weight of the parasitic element as a coefficient.
[0068]
Here, for example, as shown in FIG. 2D, a chip or a block to be wired is divided into a grid while determining the size with reference to the wiring density figure, and the weight of the parasitic element is assigned to each grid. Set as a coefficient.
[0069]
Next, a plurality of wiring paths are searched in a wiring path search step 104 as shown in FIG. 2E while referring to the parasitic element coefficient in a wiring order set between pins for each net or in the entire net in advance.
[0070]
In this way, an optimal path is selected according to the necessity, and wiring is performed in the wiring step 105.
[0071]
Further, the completion of the wiring of the circuit group is determined in the wiring group end determination 515, and the wiring is repeated until the wiring in the same group is completed, thereby enabling high-speed wiring with necessary and sufficient accuracy.
[0072]
(Embodiment 6)
The present embodiment is characterized in that the signal strength is set from the net attribute 610 in addition to the net list in the above-described embodiment. As shown in FIG. In the net group extraction step 612, a search is performed based on the clock pin of a cell that has been made into a cell in advance and a clock system is automatically analyzed, and a search is performed based on an external terminal to automatically analyze a signal flow and a signal flow direction. Extract as a circuit group.
[0073]
Then, from the net attribute 610, a net group is extracted based on, for example, the level of sensitivity to receive crosstalk or the frequency and level of crosstalk (noise source).
[0074]
Thereafter, an area to be arranged is set in a net area setting step 613, and a circuit belonging to a net group is arranged in the net area in an arrangement step 513.
[0075]
Then, the order of groups to be wired is determined in the wiring group determination step 514 for each net group.
[0076]
Thereafter, as in the above-described embodiment, in the tentative wiring step 100, all nets are tentatively wired with the shortest distance, and the distribution of the parasitic elements and the wiring density generated between the parallel or overlapping wirings are determined for each wiring layer. It is calculated in the extraction step 101.
[0077]
Here, for example, as shown in FIGS. 2A to 2C, a region obtained by oversizing a logical product (AND) portion between wiring layers by a certain amount and then performing a logical sum (OR) as one wiring density figure. Is repeated for each wiring layer.
[0078]
Next, in the parasitic element coefficient setting step 102, the wiring density, the wiring density, and the wiring density pattern are compared with the wiring density figure based on the parasitic element table 103 set individually or in combination of each of the parallel or multilayer patterns of the wiring or the wiring density. The figure is subdivided so as to match the parasitic element table and collated, and the weight of the parasitic element is determined as a coefficient.
[0079]
Here, for example, as shown in FIG. 2D, a chip or a block to be wired is divided into a grid shape while determining the size with reference to the wiring density figure, and the weight of the parasitic element is assigned to each grid. Set as a coefficient.
[0080]
Next, a plurality of wiring paths are searched in a wiring path search step 104 as shown in FIG. 10 by referring to the parasitic element coefficient in a wiring order set between pins for each net or in the entire net in advance.
[0081]
At this time, in consideration of another net group existing in the wiring route of the net extending over the net group, the route that minimizes the influence of crosstalk is bypassed, and the optimum route is selected according to its necessity. Wiring with. Then, the completion of the wiring of the circuit group is determined in the wiring group end determination 515, and the wiring is repeated until the wiring in the same group is completed, so that high-speed wiring can be performed with necessary and sufficient accuracy.
[0082]
(Embodiment 7)
The design method of the semiconductor device according to the present embodiment is characterized in that the size of the lattice region is changed according to the required extraction accuracy of the parasitic element.
[0083]
That is, in the tentative wiring step 100 of FIG. 1, all the nets are tentatively wired with the shortest distance, and from the result, the distribution of parasitic elements and the wiring density generated between the wirings which are parallel or overlapped for each wiring layer are calculated in the wiring density extraction step 101. For example, as shown in FIGS. 2A to 2C, a region obtained by performing a logical sum (OR) after oversizing a logical product (AND) portion between wiring layers by a certain amount is defined as one wiring density figure. This is repeated for each wiring layer.
[0084]
Next, in the parasitic element coefficient setting step 102, the wiring density figure is compared with the wiring density figure or the wiring density, based on the parasitic element table 103 which is set in advance by the wiring shape, the wiring density, and the wiring in parallel or in a multilayer pattern. The figure is subdivided so as to match the parasitic element table and collated, and the weight of the parasitic element is determined as a coefficient.
[0085]
Here, for example, a chip or a block to be wired as shown in FIG. 2 (d) is changed with reference to the wiring density figure while changing the size of the grid so as to satisfy the required extraction accuracy of the parasitic element. The weight of the parasitic element is set as a coefficient in the lattice.
[0086]
Next, a plurality of wiring paths are searched for as shown in FIG. 2 (e) while referring to the parasitic element coefficients in a wiring order preset between pins for each net or for the entire net, and an optimum path is determined as a wiring path. By performing a plurality of searches in the search step 104, selecting an optimum route according to the necessity, and wiring in the wiring step 105, wiring can be performed at high speed with necessary and sufficient accuracy.
[0087]
【The invention's effect】
As described above, according to the present invention, when a wiring path is determined by converting a parasitic element generated between wirings into a coefficient according to the wiring density, a causal relationship of complicated crosstalk (for example, when a wiring is received from another net). In addition, since the wiring can be performed while taking into account the strength of the crosstalk to be applied to another network or the other network), a layout that minimizes the influence of the crosstalk can be performed at high speed with a sufficient and sufficient accuracy.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a method according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a search for a wiring path in consideration of a parasitic element extraction unit and a parasitic element coefficient in the same method.
FIG. 3 is a flowchart illustrating a method according to a second embodiment of the present invention.
FIG. 4 is a diagram showing a method of correcting a parasitic element coefficient in consideration of a step in a wiring lower layer in the same method.
FIG. 5 is a flowchart illustrating a method according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a parasitic element correction method in which the proximity effect of light is considered in the method.
FIG. 7 is a flowchart illustrating a method according to a fourth embodiment of the present invention.
FIG. 8 is a diagram showing a method for automatically extracting and arranging circuit groups from a netlist in the same method.
FIG. 9 is a flowchart illustrating a method according to Embodiments 6 and 7 of the present invention.
FIG. 10 is a diagram illustrating a method of determining a wiring route that straddles a net group.
FIG. 11 is a diagram showing a parasitic element targeted at the time of automatic wiring according to the related art.
FIG. 12 is a diagram showing a parasitic element that should be considered at the time of automatic wiring.
[Explanation of symbols]
100 Temporary wiring process
101 Wiring density extraction process
102 Parasitic element table
103 Parasitic element coefficient setting process
104 Wiring route search process
105 Wiring process
200 Area with coarse wiring density
201 Area with dense wiring density
203 First wiring layer
204 Second wiring layer
205 Layered part of first-layer wiring and second-layer wiring
206-208 Extracted multilayer part and dense / dense area of wiring density
209 Area where extracted wiring density is high
250 Layout target area
251 to 252 Parasitic element coefficient setting areas divided in a grid
253 High parasitic element factor
254 Area with low parasitic element coefficient
260 Starting point of wiring
261 Wiring end point
262, 263 Wiring path
300 Wiring cross section
301 polysilicon
302 Step of wiring
303 extracted step
310 Wiring level difference extraction process
311 Parasitic element coefficient correction process
400 Area where wiring is thin due to proximity effect of light
410 Wiring thinning part extraction process
411 Parasitic element coefficient correction process
500, 501 circuit group
510 Netlist
511 Circuit group extraction process
512 Placement area setting process
513 Placement process
514 Wiring Group Determination Process
515 Wiring group end judgment
610 Net attribute
611 Netlist
612 Net Group Extraction Process
613 Net area setting process
701 Starting point of wiring
702 Wiring end point
703, 704 wiring route
900 Parasitic capacitance of multilayer part

Claims (13)

Tentatively wiring,
Extracting the wiring density from the wiring result;
A parasitic element coefficient setting step of setting a weight of the parasitic element as a coefficient for each region;
Searching for a wiring route;
Correcting at the time of actual wiring based on the coefficient of the parasitic element. 2. The method according to claim 1, wherein the tentative wiring step is a tentative wiring step based on netlist information. The said parasitic element coefficient setting process is a process which divides an element surface into a grid-like area | region, determines the weight of the parasitic element for every grid-like area | region, and sets it as a coefficient, The Claim 1 or 2 characterized by the above-mentioned. Semiconductor device design method. 4. The semiconductor device design according to claim 1, wherein the parasitic element coefficient setting step includes a step of correcting a weight coefficient of the parasitic element in consideration of an influence of a parasitic capacitance due to a wiring lower layer. 5. Method. 4. The semiconductor device according to claim 1, wherein the parasitic element coefficient setting step includes a step of correcting a weight coefficient of the parasitic element in consideration of a change in wiring width during lithography. Design method. 6. The method according to claim 5, wherein the parasitic element coefficient setting step includes a step of extracting a portion where a wiring width at the time of lithography is small, and a step of correcting and setting a weight coefficient of the extracted parasitic element. Semiconductor device design method. The step of temporarily wiring,
Extracting a circuit group from the connection information of the netlist;
Setting and arranging an arrangement area for each group;
7. The method for designing a semiconductor device according to claim 1, further comprising the steps of: searching for a wiring path for each group and performing wiring. The step of temporarily wiring,
Extracting a net group from the connection information of the net list by the net attribute;
8. The method according to claim 1, further comprising: setting and arranging an arrangement area for each group. 9. The method according to claim 1, wherein the correcting step includes a step of correcting the weight coefficient based on the strength of a signal passing through the wiring for each area based on a net attribute. Semiconductor device design method. 10. The method of designing a semiconductor device according to claim 1, wherein the size of the region is changed in accordance with required extraction accuracy of a parasitic element. 11. A semiconductor device comprising a wiring designed using the method for designing a semiconductor device according to claim 1. A program for causing a computer to execute the method of designing a semiconductor device according to claim 1. A computer-readable recording medium on which a program for causing a computer to execute the design method according to claim 1 is recorded.

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