JP3913180B2 - Semiconductor integrated circuit design method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for designing a layout of a semiconductor integrated circuit, and more particularly to a method for designing a layout of a clock wiring for transmitting a clock signal and a cell driven by the clock signal.
[0002]
[Prior art]
Conventionally, as a layout design method for a semiconductor integrated circuit (LSI), there are a gate array (or sea of gate) method, a standard cell method, and the like. In these systems, basic logic cells such as NAND and NOR and composite cells combining them are arranged on a semiconductor chip in an array, and an LSI is configured by wiring between terminals of these cells in accordance with a logic connection request. Is the method. These methods are advanced in design automation, and various systems have been developed.
[0003]
Furthermore, due to advances in LSI manufacturing technology, an embedded array cell type semiconductor integrated circuit in which a gate array type and a standard cell type are fused has been developed. In this method, a part or all of the circuits in a semiconductor integrated circuit are incorporated into a plurality of functional blocks, for example, a pre-designed macro block or a newly designed standard cell system block, and each functional block is incorporated. It is arranged on the semiconductor chip and the outside of each functional block is defined as a gate array region. Then, generation of circuits other than the circuits housed in the functional block and wiring outside the functional block are performed in the gate array region, and a semiconductor integrated circuit is to be built. Therefore, these systems have an advantage that a circuit can be arbitrarily generated in a region outside the functional block, so that the circuit can be added / modified relatively easily before the manufacturing wiring process.
[0004]
Incidentally, in recent years, semiconductor integrated circuits have been developed that are highly integrated so that the entire system necessary for performing a desired function can be mounted on one semiconductor chip. As the number of semiconductor integrated circuits increases, the number of man-hours for designing a semiconductor integrated circuit is increasing. The layout design of a semiconductor integrated circuit is no exception, and the man-hours and processing time are increasing exponentially, and enormous time and labor are consumed to lay out the entire semiconductor integrated circuit at once. Thus, as described above, a hierarchical design method is often used in which a semiconductor integrated circuit is divided into several functional blocks, each functional block is individually designed, and finally, the functional blocks are wired and assembled. .
[0005]
On the other hand, the frequency of the clock signal for driving each cell in the semiconductor integrated circuit synchronously has been increased. The operation speed of the semiconductor integrated circuit is restricted by a clock skew that is a phase difference between clock signals reaching each cell. Similarly, the operation speed of the entire system is restricted by the clock skew between the semiconductor integrated circuits. As the number of cells such as flip-flops driven by the clock signal increases due to the high integration of the semiconductor integrated circuit, the clock signal supplied to each functional block must be synchronized with each other. Wiring schemes for supplying to each cell are becoming increasingly important.
[0006]
Here, as a method for minimizing the clock skew described above, there is a method of generating a clock tree. As shown in FIG. 16, for each functional block, a wiring path from a clock signal input unit to a flip-flop group that must operate simultaneously is configured as a clock tree, and a clock signal corresponding to the root in the clock tree is defined. This is a method of suppressing a time difference (clock tree skew) until a signal arrives from a transmitting cell to each flip-flop within a certain size. Here, as shown in FIG. 16A, three functional blocks BL1, BL2, and BL3 are arranged in the semiconductor integrated circuit 1 surrounded by the pad 11, and in each functional block BL1, BL2, and BL3, Clock trees CT1, CT2 and CT3 are formed which indicate wiring structures (clock nets) for transmitting clock signals. FIG. 16b is an enlarged view of a part of the clock tree CT1 configured in the functional block BL1. A flip-flop 20 is disposed at a portion corresponding to the leaf of the clock tree CT1, and a clock buffer 21 is disposed (inserted) at a portion corresponding to an intermediate node between the tapping points 23 of the clock tree CT1. The clock buffers and clock buffers and flip-flops are connected by wiring. In the clock tree generated in this way, suppressing the clock skew increases the operation speed of all the circuits, so it is an important issue to bring the clock skew closer to “0”.
[0007]
As described above, Non-Patent Document 1 is a known example of a method for accurately setting the clock skew to “0” when generating a clock tree. When constructing a clock tree, this method is called zero skew merge so as to form a binary tree in a bottom-up order from the flip-flop. The tree is always skew = 0 (this state is called zero skew). ). Here, the above-described tapping point 23 is an important concept when creating one tree from two trees so as to achieve this zero skew (see FIG. 16). This is a point indicating which position is the root point (to which the clock buffer is connected) when merging two trees. If the delays from the tapping point 23 to the flip-flops 20 in the leaves of each tree are set to be equal, a zero skew clock tree can be realized. In the above-described known example, a method is described in which after flip-flops and buffers are once arranged, wiring is performed in a bottom-up manner so as to form a binary clock tree while always guaranteeing zero skew.
[0008]
By the way, since it is necessary to always guarantee zero skew when generating this clock tree, a clock tree having a long wiring length is generated unless wiring is performed well. That is, the delay time from the root of the clock tree to the leaves increases, resulting in a longer clock period and a slower operation circuit.
[0009]
Therefore, an efficient algorithm that has recently solved such a problem has been developed. For example, Non-Patent Document 2 is an example. This is an algorithm for minimizing the estimation function of the delay time of the clock signal as an objective function, and is a technique for simultaneously optimizing the wiring width.
[0010]
An example of the layout design procedure in the standard cell system (or gate array system) in which the above-described clock tree is used to partition the semiconductor integrated circuit into functional blocks is as follows.
[0011]
1. Basic logic cells are arranged in an array based on a circuit diagram representing a desired operation. At this time, the flip-flops are arranged so as to spread over the entire functional block.
[0012]
2. With respect to a net (clock net) of a wiring for transmitting a clock signal, the clock tree is determined from the flip-flop group in a bottom-up manner, and the clock buffer arrangement and the schematic wiring path of the clock tree are determined.
[0013]
3. A rough wiring route is determined for the remaining nets.
[0014]
4). For the clock net, detailed wiring is performed so as to achieve zero skew according to a schematic wiring route.
[0015]
5. For nets other than the clock net, detailed wiring is performed according to a schematic wiring path.
[0016]
On the other hand, as a method of generating a clock tree by a procedure different from the above-described procedure, for example, as disclosed in Patent Document 1, there is a method of generating a clock tree in a top-down manner while hierarchically dividing blocks. This method is the same as the procedure 1. And 2. In this method, the clock buffer is inserted, the basic logic cells are arranged, and the clock tree structure is generated at a time while performing hierarchical region division in a top-down manner. According to this method, there is an advantage that the arrangement of basic logic cells other than the flip-flop can be optimized while being aware of the clock tree structure.
[0017]
The above-described methods are often performed at the same time for the entire semiconductor chip or applied to each functional block.
[0018]
In addition, since semiconductor integrated circuits are often designed hierarchically, when applied to each functional block, it is important to synchronize clock signals between the functional blocks. As an example of a conventional layout method for synchronizing clock signals supplied to each functional block,
(A) The external clock wiring from the clock supply source to the functional block is not limited to the wiring channel outside each functional block, and the clock input unit (clock terminal) of each functional block from the clock supply source can be freely set. (B) A clock signal distribution unit is installed at the center of the semiconductor integrated circuit, and the clock supply source and the clock signal distribution unit are connected by a single clock wiring to distribute the clock. There is a method of laying out each clock wiring so as to have the same length between the block and the clock terminal of each functional block including the functional block. For example, the method disclosed in Patent Document 2 is an example.
[0019]
[Non-Patent Document 1]
Proc.IEEE International Conference on Computer Aided Design, 1991, pp.336-339
[Non-Patent Document 2]
Proc. IEEE International Conference on Computer Aided Design, 1993, pp.563-566
[Patent Document 1]
JP-A-6-282603 (abstract)
[Patent Document 2]
JP 5-198674 A (Abstract)
[0020]
[Problems to be solved by the invention]
However, in the methods of Non-Patent Documents 1 and 2, since the clock tree is generated after the basic logic cell including the flip-flop and the clock buffer is first arranged, the clock tree can be configured to have zero skew. There has been a problem that it is difficult to minimize the delay time of the clock tree and to keep the required delay time value. For this reason, there is a possibility that operation synchronization between functional blocks may not be obtained in a semiconductor integrated circuit, or when a system composed of a plurality of semiconductor integrated circuits is configured, operation synchronization between semiconductor integrated circuits is performed. There was a fear that it could not be obtained.
[0021]
In the method of Patent Document 1, since the flip-flop group is distributed hierarchically, it is difficult to minimize the delay time of the clock tree and adjust to the required delay time value. For this reason, as in Non-Patent Documents 1 and 2, there is a possibility that operation synchronization between the semiconductor integrated circuits cannot be obtained.
[0022]
Further, as the methods of Non-Patent Documents 1 and 2 and Patent Document 1 aim, when the clock skew actually becomes “0”, a large number of flip-flops are operated at the same time. Current (increase in peak current) flows. Therefore, depending on the power supply state, the flip-flop may not operate. That is, if the number of logic cells such as flip-flops incorporated in the semiconductor integrated circuit is not so large even if the clock skew for each logic cell is designed to be “0” as in the prior art, In this case, since the operation time is gradually shifted due to variations in the process, there is little possibility of malfunction due to the operation of many logic cells at one time. However, when the scale of the semiconductor integrated circuit or the entire system is increased as in recent years and the clock frequency is increased, the probability that the number of logic cells that are actually simultaneously operated increases. Therefore, there is a possibility of causing the above-described problems due to instantaneous generation of excessive current.
[0023]
In the methods of Non-Patent Documents 1, 2, and 3, the normal clock net is often wired at the same time as other nets for cells to which no clock signal is supplied (the same wiring layer can be used), which is large and complicated. In the case of a simple clock tree, there is a problem that a wiring with an unnecessarily long wiring length is likely to occur due to the occurrence of a detour in the wiring path of the clock net due to the relationship between the wiring paths with other nets.
[0024]
Further, in the method of Patent Document 2, when a clock tree is generated by arranging a functional block on a semiconductor chip and clock wiring is performed, the wiring must be equal in length from the clock supply source to the clock terminal of each functional block. It is necessary to use a dedicated clock wiring in order to avoid the failure of other nets in order to keep the restriction. For example, in the case of a semiconductor chip having three wiring layers, the first and second layer wirings are used for general signal lines and power supply wirings, and the third layer wiring is used for clock wirings. In this case, since the general signal line cannot be formed in the third layer wiring, the chip area becomes larger than the case where the third layer wiring is also used as the general signal line. On the other hand, in a semiconductor integrated circuit having two wiring layers, if clock nets and nets other than clock nets are mixed, it is difficult to accurately adjust clock skew. This is due to the following reason. In other words, since clock nets and nets other than clock nets are mixed in the same wiring layer, in order to avoid interference between clock nets and nets other than clock nets, clock input from the clock source to each functional block In many cases, it is difficult to make the wiring length to the terminal the same. Therefore, once the functional blocks are arranged and the clock nets are wired, the transistor size of the clock buffer may need to be changed in order to finally adjust the skew. In that case, if the transistor size of the clock buffer in the functional block is changed, it is necessary to redesign the layout in the functional block. However, this greatly increases the number of layout steps, and the significance of using such a method is diminished.
[0025]
The purpose of the present invention, by taking means capable of adjusting in a readily predetermined range the delay time in the semiconductor integrated circuit, also in the overall system incorporating a large number of circuits, in smooth operation between the circuits The purpose is to design a layout of a semiconductor integrated circuit that can be synchronized.
[0028]
[Means for Solving the Problems]
Design method of a semiconductor integrated circuit of the present invention is to partition the semiconductor integrated circuit including a plurality of elements into a plurality of cells of at least one element, the plurality of cells of a plurality of the clock signals are supplied classified into a plurality of second type cells comprising a first type cell and said one cell other than the cell, and to partition the plurality of cells into a plurality of functional blocks, a method of designing the semiconductor integrated circuits And using the temporarily arranged functional blocks and the external wiring, the delay time outside the block from the first clock input unit to the second clock input unit of the functional block and the functional block. A final delay time is calculated for each first type cell as the sum of the intra-block delay time from the second clock input unit to each first type cell, and the final delay in each first type cell is calculated. A first step of clock skew fits limits, and is calculated by the circuit simulator on Symbol block out wiring paths as the final delay time for each of the one cell is within a predetermined range is the difference between, And a second step of generating a wiring pattern according to each wiring route calculated in the first step.
[0029]
By this method, the delay time in each first type cell in the semiconductor integrated circuit is adjusted to a certain width. Therefore, elements constituting each cell operate in synchronization with a common clock signal between the functional blocks in the semiconductor integrated circuit. In addition, elements constituting each cell can operate in synchronization with a common clock signal between the semiconductor integrated circuits in a system constituted by a plurality of semiconductor integrated circuits.
[0032]
In the first step, by distributing the final delay time of each cell to a plurality of values different from each other within the predetermined range, even if the circuit scale of the semiconductor integrated circuit increases and the clock frequency increases, the semiconductor integrated circuit It is possible to avoid a situation in which many cells actually operate simultaneously in the circuit. Accordingly, it is possible to prevent malfunction of the flip-flop or the like due to an instantaneous increase in current.
[0033]
In the first step, a clock tree structure configured so that wiring derived from the second clock input unit to the functional block is sequentially divided into a plurality of directions and finally reaches each of the first type cells. Generating a template to be represented, and arranging each of the first type cells in a functional block based on the clock tree structure, and further, in the empty area other than the area where the first type cell is arranged, A step of arranging cells, a step of calculating a rough wiring path between the cells according to a logical connection request, and a delay time in each of the first type cells on the clock tree from the second clock input unit. Each function block by adjusting to a desired value and generating a wiring pattern in the functional block according to the wiring path obtained in the above step. Formation of clock nets using a clock tree structure in Tsu the click can be easily performed. In addition, since the structure of the clock net is determined in advance, it is possible to easily avoid the optimization of the arrangement of the second type cells and the interference of the wiring between the clock net and the net other than the clock net. Accordingly, the number of man-hours for layout design is greatly reduced.
[0034]
Generating the template, calculating a number of branches of the clock tree, calculating a size of the clock tree, calculating a position of a tapping point on the clock tree, and the clock By arranging the delay time adjusting cell in the tree, an area for placing the second type cell in the functional block is secured at the stage of generating the template, and the delay time and clock skew are reduced. Since it is set to a state close to a desired value to some extent, the progress of the subsequent steps becomes smooth. Therefore, the efficiency of layout design is greatly improved.
[0035]
The steps of adjusting the final delay time of each cell include changing the output drive capability of the cell located at the intermediate node on the clock tree, changing the width of the wiring in the clock tree, and tapping on the clock tree. This can be done by changing at least one of the points.
[0036]
By further comprising a step of arranging an out-of-block delay time adjusting cell in front of the second clock input unit and outside the functional block, it is possible to block only by changing the size of the out-of-block delay time adjusting cell such as a clock buffer. The external delay time and clock skew are adjusted, and there is no need to redesign the layout in each functional block. Therefore, an increase in layout man-hours associated with resizing can be avoided.
[0048]
1a-1d are diagrams illustrating the concept of clock structure design. As shown in FIG. 1a, the interior of the semiconductor integrated circuit 1 is partitioned into a plurality of functional blocks BL1, BL2,..., BLn, and the arrangement of the functional blocks BL1, BL2,. Then, a clock signal input from the clock generation source 2 through the first clock input unit 3 into the semiconductor integrated circuit 1 is transmitted to the second clock input unit 4 of each functional block BL1, BL2,. The out-of-block wiring path CNout (out-of-block clock net) can also be determined temporarily. However, the frame in which the inside of the semiconductor integrated circuit 1 shown in FIG. 1a is represented by blanks indicates the functional blocks BL1, BL2, and BLn shown in FIG. 1b. As shown in FIG. 1b, each functional block BL1, BL2,..., BLn in the semiconductor integrated circuit 1 is in a state where a large number of logic cells are accommodated.
[0049]
Here, as shown in FIG. 1c, since the wiring configuring the out-of-block clock net CNout is a set of delay elements in which resistance and capacitance are electrically coupled, the first clock input unit 3 to each functional block BL1. ,..., BLn−1, BLn out-of-block delay times T1out,..., Tn−1out, Tnout are temporarily determined (however, the wire diameter is set to a constant value). Each of the functional blocks BL1,..., BLn-1, BLn can be regarded as a buffer having delay times T1in,. Accordingly, the delay times T1, T2,..., Tn-1, Tn of the clock signals from the first clock input unit 3 to the respective logic cells of the functional blocks BL1, BL2,. be able to. At this stage, it is estimated whether or not the delay times T1, T2,..., Tn−1, Tn in each functional block fall within a predetermined range. At the same time, an idea is made as to whether the clock skew is within the limit range. Note that the clock skew being “0” means that T1 = T2 =... = Tn−1 = Tn. Then, if it is expected that the delay times T1, T2,..., Tn-1, Tn in each logic cell are all within a predetermined range, the arrangement of the functional blocks at the predetermined positions and the clock nets in the functional blocks Enter the design. On the other hand, at this stage, when there is no prospect of keeping the delay times T1, T2,..., Tn-1, Tn in the respective functional blocks within a predetermined time, the function blocks BL1, BL2,. The delay times T1, T2,..., Tn−1, Tn in each logic cell are estimated again by changing the arrangement, etc., and temporary arrangement is performed until the delay time is within a predetermined range and the clock skew is within the limit range. . When this temporary arrangement is finished, as shown in FIG. 1d, the delay time is calculated in detail using a circuit simulator (for example, SPICE) for the clock net at the stage where the temporary arrangement is finished.
[0050]
Next, details of the clock design method in the present embodiment will be described. First, as shown in FIG. 2a, an out-of-block clock net CNout is formed. At this time, each functional block BL1, BL2,... Is provisionally arranged in the semiconductor integrated circuit 1, and up to the final branch point up to each functional block BL1, BL2,. The part is determined, and the part from the final branch point 5 to each functional block BL1, BL2,. That is, there is left a room for slightly shifting the positions of the functional blocks BL1, BL2,. Then, out-block delay times T1out, T2out,..., Tnout of the clock signal from the first clock input unit 3 to the second clock input unit 4 of each functional block BL1, BL2,.
[0051]
Next, as shown in FIG. 2b, clock trees CT1, CT2,..., CTn, which are wiring paths for transmitting clock signals in the functional blocks BL1, BL2,. To do. This clock tree generation method will be described in the second embodiment. At this time, intra-block delay times T1in, T2in,..., Tnin in each functional block BL1, BL2,.
[0052]
Finally, as shown in FIG. 2c, the delay times T1 (= T1out + T1in) and T2 in the logic cells in each functional block in a state where the functional blocks BL1, BL2,..., BLn are incorporated in the semiconductor integrated circuit 1. (= T2out + T2in),..., Tn (= Tnout + Tnin) are calculated. At this time, the delay time T1, T2,..., Tn in each logic cell is controlled to be grouped into several different values within a certain range, and the wiring width of each clock net is changed. Alternatively, a clock buffer is arranged as necessary. In this case, the clock skew is not “0” and is grouped into several different values, but is set within a limited range that does not cause a synchronization failure of each logic cell.
[0053]
When the delay times are grouped in this way, the delay times of the clock signals to the respective logic cells are the same in a certain functional block if they are grouped into several types in units of functional blocks BL1, BL2,. Will be designed as follows. However, the delay time may be grouped for each logic cell. That is, the delay time of the clock signal may be designed to be different for each logic cell group in a certain functional block.
[0054]
In the layout design method as in this embodiment, the wiring path outside the functional block, that is, the outside clock net is generated first, and then the delay time T1, T2 of the clock signal from each first clock input unit 3 to each logic cell is generated. ,..., Tn are generated so as to make the predetermined range, so that the delay time T1, T2,..., Tn of the clock signal to each logic cell can be adjusted to a desired value. Therefore, between the functional blocks, each logic cell operates in synchronization with a common clock signal. Further, even when a large system is constituted by several semiconductor integrated circuits, operations between the semiconductor integrated circuits can be accurately synchronized.
[0055]
As in the present embodiment, at the beginning of the structural design of the clock net, it is not always necessary to stop until the final branch point 5 reaching the functional blocks BL1, BL2,..., BLn in the non-block clock net CNout. You may decide to each 2nd clock input part 4 of each functional block. However, as in this embodiment, at the beginning of the structural design of the clock net, the portion up to the final branch point 5 of the out-of-block clock net is first determined, and the delay time is adjusted in the step of performing the final wiring, etc. Therefore, by finely adjusting the position of the functional block, the delay time can be adjusted finely and accurately, and the adjustable width can be expanded.
[0056]
In this embodiment, the pseudo clock net is designed before starting the layout design of the actual clock net. However, the design of the real clock net is not necessarily performed without designing the pseudo clock net. You may start. However, at the design stage of the pseudo clock net, an appropriate arrangement location of each functional block BL1, BL2,..., BLn is roughly determined so that the delay times T1, T2,. By doing so, it is possible to avoid a situation in which later it becomes clear that the delay time and the clock skew cannot be adjusted to desired values at the original placement location, and the functional blocks have to be rearranged.
[0057]
Further, it is not always necessary to perform the grouping of the delay times as in the present embodiment, and the delay times of the logic cells may be the same, in other words, the clock skew may be “0”. However, by designing the delay time in the logic cell to be grouped into several different values at the design stage in this way, even when the scale of the semiconductor integrated circuit is increased and the clock frequency is increased. Therefore, it is possible to effectively prevent a malfunction due to a shortage of power caused by a large number of logic cells operating at a certain moment.
[0058]
Further, in this embodiment, the non-block clock net CNout is not designed using the clock tree, but the non-block clock net CNout may be designed using the clock tree.
[0059]
(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS.
[0060]
FIG. 3 is a flowchart showing an overall procedure of the layout design method according to the second embodiment.
[0061]
FIG. 4 shows the configuration of the semiconductor integrated circuit 1 according to the present embodiment. Three functional blocks BL1, BL2, and BL3 are arranged in a region surrounded by the pads 11 in the semiconductor integrated circuit 1 to supply a clock signal. A clock net CNout that transmits a clock signal supplied to each functional block BL1, BL2, BL3 from a clock generation source (not shown), and a clock to each basic logic cell in each functional block BL1, BL2, BL3. Clock trees CT1, CT2, and CT3 representing wiring paths for transmitting signals are generated.
[0062]
5 to 8 are diagrams showing changes in the structure in the case of performing placement and routing in the functional block BL1 shown in FIG. 4 according to the procedure shown in FIG.
[0063]
Hereinafter, only a schematic procedure will be described in accordance with the procedure shown in FIG. 3 with reference to FIGS.
[0064]
First, in step ST1, for example, as shown in FIG. 5a, a template representing the structure of the clock tree CT1 in the functional block BL1 in order to keep the delay of the clock tree (the arrival time from the root of the tree to each leaf) within the limit range. Is generated. In the present embodiment, a template of the clock tree CT1 is generated in order to determine the positions of the flip-flops and clock buffers, which are first-type cells arranged on the clock tree CT1, and the size of the clock tree CT1 itself. Here, what is important is not only the change in the transistor size of the clock buffer, but also the delay time from the root of the clock tree to the flip-flop located at the leaf (in this embodiment, the intra-block delay time Tin in accordance with the size of the clock tree). Can be changed). Using this property, the delay of the clock tree can be finely adjusted, and a free area can be secured as necessary. At that time, in step ST12, a delay time is calculated, and a template is generated based on the calculation result. For example, as shown in FIG. 5b, by shifting the tapping point 23 from the equidistant position of each logic cell, the delay time in each logic cell can be made different from each other, and the clock skew value can be adjusted.
[0065]
Next, in step ST2, all the logic cells are arranged. At this time, first, as shown in FIGS. 6a and 6b, the flip-flop 20 and the clock buffer 21, which are first-type logic cells, are first arranged on the clock tree CT1. Thereafter, as shown in FIG. 7a, the remaining second type logic cells 22 are arranged.
[0066]
Next, schematic wiring is performed at step ST3. The structure of the clock tree has already been generated in step ST1, but the outline wiring path related to the clock tree is determined in detail, that is, specifically to which part in the semiconductor integrated circuit is to be routed, and the clock network is further determined. A schematic wiring path is also obtained for other nets (that is, a wiring path for transmitting a signal other than the clock signal). At this time, in consideration of the structure of the clock tree, the wiring congestion degree is minimized to determine a schematic wiring route that minimizes the area of the wiring region.
[0067]
Next, in step ST4, the clock skew value is adjusted in detail based on the arrangement positions of the flip-flop 20 and the clock buffer 21. At that time, fine adjustment is performed by changing the transistor size of the clock buffer 21, changing the wiring width in the paths 30, 31, and 32 as shown in FIG. 7B, changing the tapping point, and the like. In step ST4, the delay of the clock tree is not adjusted. This is because it is impossible to change (adjust) a large delay at this stage. Instead of changing the transistor size of the clock buffer, a method of selecting a different clock buffer may be used.
[0068]
Finally, in step ST5, as shown in FIG. 8, detailed patterns of wiring of all nets are generated. Here, the following two methods (1) or (2)
(1) A method in which a dedicated wiring layer is wired to a clock net, and other nets are wired by using another wiring layer. (2) A method in which all nets are wired by using all wiring layers is selected. Can be selected.
[0069]
In the case of the above method (2), depending on the relationship between the clock net and a net other than the clock net, there may be a case where wiring different from the desired clock skew value occurs. Make changes.
[0070]
As described above, since the template is used to determine the clock tree structure, it is possible to determine the optimum arrangement of flip-flops and clock buffers, and to control the clock skew and clock tree delay flexibly and easily, and a semiconductor with a high clock frequency. Integrated circuit layout design is facilitated. In addition, since the clock tree structure is known in advance, the arrangement position of other logic cells can be optimized, and interference between the clock net and the general signal net can be avoided to easily reduce the degree of wiring congestion. it can.
[0071]
In this embodiment, a clock tree is generated by arranging buffers as clock buffers at the intermediate nodes of the clock tree. However, when the clock tree has an even number of stages from the root to the leaves, an inverter whose logic value is inverted. However, since the logical value of the input signal is maintained at the end, no problem occurs.
[0072]
Next, specific contents of steps ST1 to ST5 in the flowchart shown in FIG. 3 will be described.
[0073]
As shown in FIG. 3, step ST1 is roughly composed of four steps. First, in step ST6, the structure of the clock tree is determined. In this case, for example, there are a binary tree system shown in FIG. 9a and a triple tree system shown in FIG. 9b. In the case of the binary tree system shown in FIG. 9a, when the buffer insertion level of the clock tree is “3”, a maximum of eight flip-flops 20 can be arranged as shown in the upper diagram of FIG. Need to be inserted. Here, the buffer insertion level is the number of buffer stages required for tracing from the clock buffer 21 serving as a base for supplying a clock signal to each flip-flop 20. If the buffer insertion level is “3” and the clock tree is a ternary tree, up to nine flip-flops 20 can be arranged as shown in FIG. 9b, and four clock buffers 21 need to be inserted. . Therefore, as the number of branch trees increases, the number of buffer insertions decreases and the maximum number of flip-flops increases, but the wiring between the buffers and between the flip-flops and the buffers increases, so it is not always advantageous for the final chip area. Absent.
[0074]
Note that the number of branch trees in one clock tree may be limited to a single tree, such as a binary tree or a triple tree, but several branch trees may be mixed in one clock tree.
[0075]
In this embodiment, as shown in FIG. 5a, a clock tree CT1 having a binary tree structure is generated.
[0076]
Next, in step ST7, the template size, that is, the size of the clock tree CT1 generated in the functional block BL1 is determined. FIG. 10a shows template regions Ret1, Ret2, and Ret3 in each of the functional blocks BL1, BL2, and BL3, and the template regions Ret1, Ret2, and Ret3 are clock trees CT1, CT2, and CT2 generated by the functional blocks BL1, BL2, and BL3, respectively. The size of CT3 is shown respectively. For example, FIG. 10b shows a shape when the template size is set small, and FIG. 10c shows a shape when the template size is set large. The shapes of both are similar geometrically, but the lengths of the wiring between clock buffers and between flip-flops and buffers are different. If the wiring length is different, the wiring delay time changes. The shorter the wiring length, the smaller the delay time in the wiring. That is, the total delay time (maximum delay time from the root clock buffer to the flip-flop) is smaller in the clock tree having the template size shown in FIG. 10b. However, if the clock tree size is made too small, flip-flops concentrate in a narrow area, increasing the occupied area of the wiring due to the congestion of the wiring, resulting in an increase in the final functional block area and an increase in the chip area. So be careful.
[0077]
In the present embodiment, as shown in FIGS. 5a and 5b, the clock tree is generated to the full size of the functional block BL1.
[0078]
Next, in step ST8, the tapping point 23 is determined in order to adjust the magnitude of the clock skew. FIG. 11A shows a case where the tapping points 23 are set so that the clock trees are balanced, and the clock skew is “0”. On the other hand, FIG. 11b shows the tapping point 23 shifted slightly to the left in the figure to form an unbalanced shape as a clock tree. In this case, since the wiring lengths between the clock buffers 21 and between the clock buffers and the flip-flops are different, the clock skew is larger than “0”. In order to realize this, step ST8 is composed of two sub-steps ST8a and ST8b as shown in the flowchart of FIG. That is, after setting a clock skew value within a preset maximum allowable skew value in step ST8a, a tapping position that matches the set clock skew value is determined in step ST8b.
[0079]
At this time, the clock skew value is calculated using the calculation result of the delay time in step ST12. In the case of a binary tree, the clock skew value is the difference between the delay time generated on the left side of the tree and the delay time generated on the right side of the tree, and thus becomes the clock skew value set in the previous step ST8a. Thus, the position of the tapping point 23 is determined. This can be calculated in the same way for a tri-tree or more.
[0080]
Even if the size of the clock tree and the position of the tapping point 23 are determined by the above steps, the type of the clock buffer 21 inserted into the clock tree is not determined, so the delay time of the clock tree is not uniquely determined. In order to determine this, in step ST9, the type of the clock buffer 21 to be inserted is selected. In general, the clock buffer 21 operates fast when it has a large driving capability, and operates slowly when it is small. The type of each clock buffer 21 is selected based on the delay time calculation result obtained in step ST12 so that the delay time value requested in advance is obtained. Here, there may be a case where the combination of clock buffers does not match the required delay value of the clock tree regardless of the combination of clock buffers. In this case, the process returns to step ST7 and the type of the clock buffer 21 is fixed. Then, the size of the template is determined again.
[0081]
Through the above steps, the size of the template that matches the required clock skew value and the delay time value of the clock tree, the type of the clock buffer 21 inserted therein, and the position of the tapping point 23 are determined.
[0082]
FIG. 5b shows a state in which the position of the tapping point 23 of each part of the clock tree CT1 is determined in the functional block BL1.
[0083]
Next, in step ST2, a logic cell group in the circuit including the flip-flop and the clock buffer is arranged. At that time, first-type logic cells arranged in the clock tree are first arranged. That is, in step ST2a, as shown in FIG. 6a, the flip-flop 20 is arranged in the clock tree CT1 in the functional block BL1, while in step ST22b, the clock buffer 21 is arranged in the clock tree CT1 as shown in FIG. 6b. To do. However, the arrangement order of the flip-flop 20 and the clock buffer 21 may be either.
[0084]
Then, in step ST2c, the second type logic cell (remaining cell) 22 to which the clock signal is not directly input is arranged in a part other than the clock tree CT1 in the functional block BL1. FIG. 7a shows a state in which the second type logic cells are arranged. In this state, since the wiring width and the like are not yet determined, the wiring part is indicated by a broken line.
[0085]
At this time, since the flip-flop 20 and the clock buffer 21 are already arranged, the second-type logic cell 22 can be arranged in consideration of the structure of the clock tree CT1, that is, the clock net in the block. Therefore, it is possible to optimize the placement while evaluating the minimization of the virtual wiring length, the reduction in the degree of wiring congestion, and the like. However, the arrangement may not be good only with this step. In that case, the process returns to step ST2a or step ST2b, and the arrangement of the flip-flop 20 or the clock buffer 21 is improved in the state where the second type logic cell 22 is arranged, and then the second step ST2c again. The rearrangement of the seed logic cell 22 can be performed. At that time, until the placement state is optimized, for example, until the virtual wiring length is minimized or the wiring congestion is minimized, the entanglement between the conventional clock net and other nets is reduced, and as a result In addition, it is possible to generate a wiring pattern with less congestion.
[0086]
Next, in step ST3, the rough wiring paths of all nets are determined. Since the clock tree structure has already been determined, while maintaining the set clock skew and clock tree delay, it is possible to connect the nets other than the clock net. Can be determined.
[0087]
Since the rough wiring paths of all nets are determined by the above steps, in step ST4, the transistor size of the clock buffer 21 is changed, the wiring width is changed, and the tapping point 23 is used in order to accurately realize a desired clock skew value. Make changes. Since the delay time in the wiring is obtained from the capacitance and resistance of the wiring, the size of the clock skew can be adjusted by the wiring width, and the change in the wiring width can also be used as one means for adjusting the clock skew value. . For example, FIG. 12a shows a wiring state when the wirings having the same tapping point 23 and the same width are used. In this case, the clock skew value is clearly “0”. On the other hand, FIG. 12b shows a wiring state in the case of using wirings having two different widths although the tapping points 23 are balanced. In this case, since the resistance value decreases as the wiring width increases, the delay time in the path using thick wiring decreases. In a thick wiring, the capacitance increases conversely, but the ratio is lower than the resistance value. Therefore, the clock skew value is not “0” in the wiring state shown in FIG.
[0088]
This step ST4 is executed in conjunction with the calculation of the delay time in step ST12.
[0089]
Here, the transistor size of the clock buffer 21 is changed in sub-step ST4a of step ST4, the wiring width is changed in sub-step ST4b, and the position of the tapping point 23 is changed in sub-step ST4c. The position of the tapping point 23 is difficult to change drastically because the arrangement of each cell has already been completed. Therefore, when the delay time is largely adjusted, the transistor size of the clock buffer 21 is changed. The fine adjustment of the delay time is performed by changing the wiring width and changing the tapping position. By using these steps ST4a-4c, it is possible to accurately adjust the clock skew value. In FIG. 7 b, the path 30 has a minimum line width, the path 31 is slightly thicker, and the path 32 has a wiring width wider than the path 31.
[0090]
Next, all the nets are wired in step ST5. As described above, there are the above-described method (1) and method (2) as specific methods for executing step ST5.
[0091]
In method (1), in step ST10a, a clock net is mainly wired in one layer, and in step ST10b, a net other than the clock net is wired using a layer that is not mainly used in step ST10a. The reason why only the clock net is mainly wired in one layer in step ST10a is as follows. That is, in step ST4, the clock skew value is accurately calculated and the wiring width of the tapping point 23 and the paths 30, 31, and 32 is changed to configure the clock net, but the clock net is the same as the net other than the clock net. This is because if handled, it may be difficult to perform actual wiring as described above.
[0092]
In method (2), after all nets are once wired in step ST11a, the wiring width is changed again in step ST11b according to the clock skew value obtained in step ST8a for only the clock net.
[0093]
As shown in FIG. 8, in this embodiment, the wiring width is determined in accordance with the structure of each clock net determined in step ST4. For example, paths 30, 31, and 32 shown in FIG. 7b correspond to the wirings 33, 34, and 35 shown in FIG. 8, respectively.
[0094]
This completes the layout.
[0095]
According to the present embodiment, since the template is used for determining the clock tree structure, the optimum arrangement of the flip-flop and the clock buffer is determined, and the delay time in each type 1 logic cell arranged in the clock skew and the clock tree is adjusted. Can be performed flexibly and easily, and layout design of a semiconductor LSI chip having a high clock frequency is facilitated. Further, since the clock tree structure is known in advance, it is possible to facilitate the optimization of the arrangement position of other logic cells and the reduction of the degree of wiring congestion between the clock net and the general signal net.
[0096]
In the second embodiment, the non-block clock net may be designed using a clock tree, or each logic cell may be arranged in a semiconductor integrated circuit without being divided into functional blocks.
[0097]
(Third embodiment)
Next, a third embodiment will be described with reference to FIGS. FIG. 13 is a diagram showing a layout of the semiconductor integrated circuit 1 according to the third embodiment. As shown in FIG. 13, in the semiconductor integrated circuit 1, four functional blocks BL1-BL4 are arranged, and a region other than the region where the functional blocks BL1-BL4 are arranged is a gate array in which transistors are laid. Region 40 is formed. In order to generate a clock signal, a clock generation source 2 is provided on a part of the pad. The clock signal passes through the non-block clock wiring 41 and is supplied to each functional block BL1 to BL4 via each clock terminal 43. A clock buffer 44 is disposed between the out-of-block clock wiring 41 and each functional block BL1-BL4. The buffer 44 appears when the clock tree for configuring the out-of-block clock wiring 41 is formed, or is one that becomes the root of the clock trees CT1-CT4 in the functional blocks BL1-BL4. . When generating the out-of-block clock wiring 41, in order to synchronize the clock signals normally supplied to the functional blocks BL1 to BL4, the length from the clock source 2 to each clock buffer 44 is made as long as possible. Wiring is performed.
[0098]
Here, in this embodiment, since the clock buffer 44 is disposed outside the functional blocks BL1-BL4, the transistor size of the clock buffer 44 is changed (resizing) independently of the functional blocks BL1-BL4. Is possible. When the base clock buffer is arranged in the function blocks BL1 to BL4, the delay time is changed when the buffer size of the clock buffer, that is, the transistor size is changed after the layout of the function blocks BL1 to BL4 is finished due to some problem. In order to control the desired value, it is necessary to lay out the functional blocks BL1 to BL4 again, which increases the number of man-hours for layout. On the other hand, by arranging the clock buffer 44 outside the functional blocks BL1 to BL4 in this way, it is possible to adjust the delay time and clock skew of the clock chip of the entire chip in detail without executing the functional block relayout. Therefore, an increase in layout man-hours can be effectively prevented.
[0099]
As shown in the enlarged view of the portion of the clock buffer 44 in FIG. 13, in this embodiment, the clock buffer 44 having a transistor size three times the standard size is used.
[0100]
In the present embodiment, the clock buffer 44 is formed by using transistors laid out in the gate array region 40. However, a transistor provided in a part of the wiring region in the vicinity of the functional blocks BL1-BL4 is used. Thus, the gate region may be formed.
[0101]
Next, a layout design method according to this embodiment will be described with reference to FIGS. FIG. 14 is a flowchart showing a procedure for forming a clock wiring in the semiconductor integrated circuit 1 shown in FIG. FIG. 15 is an exploded view showing a change in the design state of the semiconductor integrated circuit along the flow shown in FIG.
[0102]
In the present embodiment, as shown in FIG. 15A, the clock generation source 2 is arranged on a part of the pad, and the functional blocks BL1 to BL4 that have not yet been laid out in the semiconductor integrated circuit 1 and the outside of the functional blocks A chip having a gate array region 40 as a wiring region (in this case, an embedded cell array type LSI) will be described as an example.
[0103]
First, in step ST21, as shown in FIG. 15B, the clock trees CT1-CT4 for forming the clock net are respectively generated in the four functional blocks BL1-BL4 that have not yet been laid out. Complete the layout with the net. At this time, when generating the clock trees CT1-CT4, the clock buffers corresponding to the roots of the clock trees are arranged in the gate array region 40 without being arranged in the functional blocks BL1-BL4.
[0104]
Next, in step ST22, as shown in FIG. 15c, the functional blocks BL1-BL4 are arranged in the semiconductor integrated circuit 1.
[0105]
Here, step ST21 may be performed after step ST22 is performed first. However, in this case, in step ST22, the unlayed functional blocks BL1 to BL4 are arranged, so that only the approximate positions thereof are determined.
[0106]
Next, in step ST23, as shown in FIG. 15d, the clock buffer 44 is arranged in the vicinity of the functional blocks BL1-BL4. The clock buffer 44 is arranged at a portion corresponding to the root of the clock tree CT1-CT4 in each functional block BL1-BL4 generated in step ST22. The transistor size of each clock buffer 44 is a size according to the required drive capability estimated when generating each clock tree CT1-CT4. In this example, since the area outside the functional block is constituted by the gate array area 40, the clock buffer 44 can be arranged at an arbitrary position.
[0107]
Finally, in step ST24, a clock tree outside the functional block is generated, and the outside-block clock wiring 41 is formed. The non-block clock wiring 41 in this example shows a state resulting from tapering (in which the wiring width is changed in stages). Tapering is an effective means for optimizing electromigration and clock delay time values. The non-block clock wiring 41 is formed so as to minimize the clock skew from the clock generation source 2 to each clock buffer 44. At this time, resizing of the transistors constituting the clock buffer 44 may be performed in order to finely adjust the clock skew in the entire chip. In that case, as described above, since the clock buffer 44 is arranged outside the functional blocks BL1 to BL4, it is obvious that the clock skew of the entire chip can be finely adjusted only by resizing the transistors constituting the clock buffer 44. It is.
[0108]
【The invention's effect】
According to the present invention, synchronization of the operation of each cell can be ensured not only within a functional block but also between each functional block and between each semiconductor integrated circuit in a system constituted by a plurality of semiconductor integrated circuits. .
[0109]
Or, while avoiding an increase in delay time by a top-down design, ensuring the synchronization of the operation of each cell between each functional block, facilitating the formation of a clock net, and easily avoiding interference between wirings The number of man-hours can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a procedure of a temporary clock design according to a first embodiment.
FIG. 2 is a diagram for explaining a clock design procedure according to the first embodiment;
FIG. 3 is a flowchart showing a layout design procedure according to a second embodiment.
FIG. 4 is a block diagram schematically showing a configuration of a semiconductor integrated circuit according to a second embodiment.
FIG. 5 is a block diagram showing a state in which the determination of the clock tree structure and the determination of the position of the tapping point are completed in the layout design procedure according to the second embodiment.
FIG. 6 is a block diagram showing a state in which the arrangement of flip-flops and the subsequent arrangement of clock buffers are completed in the layout design procedure according to the second embodiment.
FIG. 7 is a block diagram showing a state in which the arrangement of the second type logic cells and the change of the wiring width are completed in the layout design procedure according to the second embodiment.
FIG. 8 is a block diagram illustrating a state in which layout design according to the second embodiment has been completed.
FIG. 9 is a block diagram illustrating a difference in the number of cells between a case where the clock tree structure is a binary tree and a case where the clock tree structure is a binary tree in the layout design procedure according to the second embodiment.
FIG. 10 is a block diagram for explaining a relationship between a functional block and a clock tree size and a difference in size of the clock tree in the layout design procedure according to the second embodiment.
FIG. 11 is a block diagram illustrating the position of a tapping point for setting a clock skew to “0” or a positive value in the layout design procedure according to the second embodiment.
FIG. 12 is a block diagram illustrating the setting of the wiring width for setting the clock skew to “0” or a positive value in the layout design procedure according to the second embodiment.
FIG. 13 is a block diagram schematically showing an overall configuration of a semiconductor integrated circuit according to a third embodiment.
FIG. 14 is a flowchart showing a layout design procedure according to the third embodiment.
FIG. 15 is a block diagram showing a change in the virtual structure of a semiconductor integrated circuit during a layout design procedure according to the third embodiment.
FIG. 16 is a block diagram for explaining a schematic structure of a conventional semiconductor integrated circuit and a clock tree generation method;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Clock generation source 3 1st clock input part 4 2nd clock input part 5 Final branch point 11 Pad 20 Flip-flop (1st kind cell)
21 Clock buffer (type 1 cell)
22 Second type cell 23 Tapping point 40 Gate array region 44 Clock buffer (cell for adjusting delay time outside block)
BL Function block CT Clock tree CN Clock net

Claims (6)

Is composed of a plurality of elements, a semiconductor integrated circuit having a first clock input a clock signal are entered from the outside, is divided into a plurality of cells of at least one element, the plurality of cells the clock signal supply A plurality of first type cells and a plurality of second type cells composed of cells other than the first type cells, and dividing the plurality of cells into a plurality of functional blocks, A method of designing,
Out-of-block delay time from the first clock input section to the second clock input section provided in each functional block and intra-block delay from the second clock input section to each first type cell in each functional block The clock skew, which is the difference between the first type cells in the final delay time, which is the sum of the time and the time, is within the limit range, and the final delay time for each first type cell is within the predetermined range. A first step of determining the layout of the functional blocks and the path of the external wiring provided outside the functional blocks;
A second step of generating a wiring pattern according to each wiring path determined in the first step,
The first step is
Temporarily placing each of the functional blocks and the wiring outside the block;
Based on the arrangement data of the temporary arranged each function block and the block outside wiring, and calculating using the circuit simulator on Kivu lock out delay,
For each of the functional blocks, a template representing a clock tree structure configured so that wiring derived from the second clock input unit is sequentially divided into a plurality of directions and finally reaches each of the first type cells. Generating step;
Based on the template, after placing each first type cell in the functional block, placing the second type cell in an empty area other than the area where the first type cell is arranged;
Based on the arrangement data of the first kind cell, and calculating using the circuit simulator on Kivu lock within the delay time in each functional block,
For each of the first type cells, the final delay time is calculated by adding the non-block delay time and the intra-block delay time, and the clock skew is calculated based on the final delay time. A calculating step;
Arrangement of the functional blocks is performed by adjusting the arrangement of the functional blocks and the path of the wiring outside the block so that the clock skew is within the limit range and the final delay time is within the predetermined range. And a step of determining a path of the out-of-block wiring . The method of designing a semiconductor circuit according to claim 1,
In the first step, the final delay time of each cell is distributed to a plurality of values different from each other within the predetermined range. The method for designing a semiconductor integrated circuit according to claim 1,
The first step,
Accordance logical connection request, determining a wiring path outline between the respective cells,
A step of finally adjusting a delay time from the second clock input unit to each first type cell arranged based on the template to a desired value to determine a wiring path between the cells ;
Method for designing a semiconductor integrated circuit, characterized in that according finalized wiring path and generating a wiring pattern of the functional block. The method of designing a semiconductor integrated circuit according to claim 3,
The step of generating the template is as follows:
Calculating the number of branches of the clock tree;
Calculating the size of the clock tree;
Calculating a position of a tapping point on the clock tree;
A method for designing a semiconductor integrated circuit, comprising: arranging a delay time adjusting cell in the clock tree. The method of designing a semiconductor integrated circuit according to claim 3,
The steps of adjusting the final delay time of each cell include changing the output drive capability of the delay time adjustment cell located at the intermediate node on the clock tree, changing the width of the wiring in the clock tree, A method for designing a semiconductor integrated circuit, which is performed by changing at least one of the tapping points. The method for designing a semiconductor integrated circuit according to claim 1,
A method for designing a semiconductor integrated circuit, further comprising the step of disposing an out-of-block delay time adjusting cell before the second clock input unit and outside the functional block.

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