JPH0980470A - Method for repairing wiring defect of tft substrate - Google Patents

Method for repairing wiring defect of tft substrate

Info

Publication number
JPH0980470A
JPH0980470A JP26214095A JP26214095A JPH0980470A JP H0980470 A JPH0980470 A JP H0980470A JP 26214095 A JP26214095 A JP 26214095A JP 26214095 A JP26214095 A JP 26214095A JP H0980470 A JPH0980470 A JP H0980470A
Authority
JP
Japan
Prior art keywords
line
repair
lines
short
intersection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26214095A
Other languages
Japanese (ja)
Inventor
Hideo Ishimori
英男 石森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi Electronics Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Electronics Engineering Co Ltd filed Critical Hitachi Electronics Engineering Co Ltd
Priority to JP26214095A priority Critical patent/JPH0980470A/en
Publication of JPH0980470A publication Critical patent/JPH0980470A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136272Auxiliary lines

Landscapes

  • Liquid Crystal (AREA)

Abstract

PROBLEM TO BE SOLVED: To effectively and easily repair broken wire of matrix wiring and a short circuit defect on an intersected point on a TFT substrate. SOLUTION: Plural lines of repair lines R1 -Rs are wired insulation-intersecting with respective leader lines of respective gate lines G1 -Gm and drain lines D1 -Dn at two positions in a square shape on surroundings of the matrix wiring, and a repair lines group constituted so as to cut one corners of respective repair lines R1 -Rs is provided. Then, when optional gate line G or drain line D breaks B at an optional position, two positions of insulation intersections between any repair line R and the leader line of the gate line G or the drain line D are connected respectively, and a detour for the broken wire B is constituted to be restored. For the short circuit S on the intersected point, the short- circuited intersected point is cut to be removed, and a similar detour is constituted by two lines of repair lines.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、カラー液晶パネ
ル用のTFT基板の配線欠陥の修復方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for repairing wiring defects on a TFT substrate for a color liquid crystal panel.

【0002】[0002]

【従来の技術】テレビなどの画像表示用のカラー液晶パ
ネルには、TFT基板が使用されている。図2は、TF
T基板1の構成と、これ対する制御部2を示す。TFT
基板1は、方形のガラス基板11に対して、それぞれ複数
m,n本のX電極とY電極とが、言い換えれば、X電極
として、通常、ゲート線12(G1 〜Gm)とY電極とし
て、通常、ドレイン線13(D1 〜Dn)とが、マトリック
ス状に配線(以下マトリックス配線)され、その各交点
にはTFTなどよりなる電極素子14が形成されている。
制御部2はデータ回路21と走査回路22よりなり、データ
回路22からは各ドレイン線Dに対して画像データが与え
られ、これに対して走査回路21は各ゲート線Gを適当な
タイミングで順次に走査し、各電極素子14のTFTをO
NまたはOFFして、カラーフィルタがバックからの照
明光を透過または遮断する仕組みである。
2. Description of the Related Art A TFT substrate is used for a color liquid crystal panel for displaying an image such as a television. Figure 2 shows TF
The structure of the T substrate 1 and the control unit 2 corresponding thereto are shown. TFT
The substrate 1 has a square glass substrate 11 in which a plurality of m electrodes and n electrodes of a plurality of m and n electrodes, respectively, in other words, are usually gate lines 12 (G 1 to G m ) and Y electrodes as X electrodes. As a general rule, the drain lines 13 (D 1 to D n ) are wired in a matrix (hereinafter referred to as matrix wiring), and electrode elements 14 made of TFTs or the like are formed at the respective intersections.
The control unit 2 is composed of a data circuit 21 and a scanning circuit 22, and image data is given from the data circuit 22 to each drain line D, while the scanning circuit 21 sequentially passes each gate line G at an appropriate timing. And scan the TFT of each electrode element 14
It is a mechanism in which the color filter transmits or blocks the illumination light from the back by turning it N or OFF.

【0003】さて、TFT基板1には製造過程において
種々の欠陥が発生する。そのなかにはマトリックス配線
の断線と短絡があり、短絡にはゲート線Gの相互間、ま
たはドレイン線相互間の短絡や、これらの交点の短絡、
または接地などがある。図3は、これらの欠陥を例示す
るもので、例えば、ドレイン線D1 は×印の1箇所で断
線しており、断線Bより下側のドレイン線D1 に接続さ
れたすべての電極素子14にはデータが供給されない。ま
たゲート線G2 は図示の1箇所で接地Eしており、ゲー
ト線G2 に接続されたすべての電極素子14は走査され
ず、いずれも動作が不良となる。またドレイン線D2
ゲート線G1 は交点で短絡Sしており、両線に接続され
たすべての電極素子14がやはり動作不良となる。このよ
うに電極素子14が動作不良すると、液晶パネルには良好
な画像が再生されない。
Various defects occur in the TFT substrate 1 during the manufacturing process. Among them, there are disconnection and short circuit of the matrix wiring, and the short circuit is between the gate lines G or between the drain lines, short circuit of these intersections,
Or there is grounding. FIG. 3 exemplifies these defects. For example, the drain line D 1 is broken at one position marked with “X”, and all the electrode elements 14 connected to the drain line D 1 below the break B are connected. Is not supplied with data. In addition, the gate line G 2 is grounded E at one position shown in the figure, and all the electrode elements 14 connected to the gate line G 2 are not scanned, and the operation of any of them becomes defective. Further, the drain line D 2 and the gate line G 1 are short-circuited S at the intersection, and all the electrode elements 14 connected to both lines also become defective. When the electrode element 14 thus malfunctions, a good image cannot be reproduced on the liquid crystal panel.

【0004】[0004]

【発明が解決しようとする課題】TFT基板1のマトリ
ックス配線は、前記したように、断線や接地または交点
の短絡がたとえ1箇所であっても、多数の電極素子14が
動作不良となるので、製造後行う検査により欠陥を検出
し、可能なものは修正措置がとられている。ただし交点
以外の短絡や接地Eに対しては、レーザカッター方式の
修正装置があり、これにより短絡部分をカットすること
ができて、修正は比較的容易であるが、断線Bと交点の
短絡にはいまのところ有効な修正装置が無いため、一般
的には廃棄処分とされており、このために製品の歩止ま
りの低下を招いているのが現状である。この発明は以上
に鑑みてなされたもので、マトリックス配線の断線と交
点の短絡欠陥に対する、有効な修復方法を提供すること
を目的とする。
As described above, the matrix wiring of the TFT substrate 1 has a large number of electrode elements 14 malfunctioning even if there is a disconnection, grounding, or short-circuiting at one intersection. Defects are detected by post-manufacturing inspections and corrective action is taken where possible. However, there is a laser cutter type correction device for short-circuits other than the crossing point and grounding E. This makes it possible to cut the short-circuited part, and the correction is relatively easy. At present, since there is no effective correction device, it is generally disposed of, and the current situation is that this leads to a decrease in product yield. The present invention has been made in view of the above, and an object thereof is to provide an effective repairing method for a short circuit defect at an intersection and a disconnection of a matrix wiring.

【0005】[0005]

【課題を解決するための手段】この発明はTFT基板の
配線欠陥修復方法であって、マトリックス配線の周囲の
ガラス基板上に、複数本のリペア線を、各ゲート線(X
電極)およびドレイン線(Y電極)の引出し線のそれぞ
れと2箇所で絶縁交差して方形状に配線し、かつ方形状
の各リペア線の1偶をカットして構成されたリペア線群
を設ける。任意のゲート線またはドレイン線が任意の箇
所で断線しているとき、リペア線群のいずれかのリペア
線と、ゲート線またはドレイン線の引出し線との、2箇
所の絶縁交差点をそれぞれ接続して、断線箇所に対する
迂回路を構成して修復する。前記において、マトリック
ス配線の任意の交点でゲート線とドレイン線とが短絡し
ているとき、短絡交点の近傍でゲート線とドレイン線と
をそれぞれカットして、短絡交点を除外し、短絡点が除
外されたゲート線およびドレイン線の引出し線と、リペ
ア線群のいずれか2本のリペア線との、それぞれの2箇
所の絶縁交差点を接続して、短絡交点に対する迂回路を
構成して修復する。
The present invention is a method for repairing wiring defects in a TFT substrate, in which a plurality of repair lines are provided on a glass substrate around a matrix wiring and each gate line (X).
(2) Electrode) and drain wire (Y electrode) lead wires are insulated and intersected at two locations to form a square wire, and a repair wire group is formed by cutting one even of each square repair wire. . When any gate line or drain line is broken at any place, connect two insulation intersections of any repair line of the repair line group and the lead line of the gate line or drain line, respectively. , Configure and repair a detour for the disconnection point. In the above, when the gate line and the drain line are short-circuited at any intersection of the matrix wiring, the gate line and the drain line are respectively cut in the vicinity of the short-circuit intersection, the short-circuit intersection is excluded, and the short-circuit point is excluded. By connecting the two insulated intersections of each of the extracted lead lines of the gate line and the drain line and any two repair lines of the repair line group, a detour path to the short-circuit intersection is formed and repaired.

【0006】[0006]

【発明の実施の形態】前記のTFT基板の配線修復方法
においては、マトリックス配線の周囲のガラス基板上
に、方形状に設けたリペア線群は、複数本のリペア線を
各ゲート線およびドレイン線の引出し線のそれぞれと2
箇所で絶縁交差して配線し、各リペア線の1偶をカット
して構成される。いま、あるゲート線が任意の箇所で断
線しているときは、いずれかのリペア線と、断線してい
るゲート線の引出し線とを、2箇所の絶縁交差点でそれ
ぞれ接続すると、断線箇所の手前(走査回路側)の各電
極素子は走査回路からの走査信号を直接受けて動作する
が、これに対して断線箇所よりあとの各電極素子は、接
続された両絶縁交点により迂回路が構成され、これを迂
回した走査信号により動作する。すなわち断線箇所が修
復される。ドレイン線の断線の場合も同様である。次
に、マトリックス配線のある交点でゲート線とドレイン
線とが短絡したときは、短絡交点の近傍でゲート線とド
レイン線とをそれぞれカットして短絡交点を除外し、こ
れが除外されたゲート線およびドレイン線の引出し線
は、いずれか2本のリペア線との、それぞれの2箇所の
絶縁交差点が接続され、前記と同様に短絡交点に対する
迂回路が構成されて修復される。前記のように、この発
明の修復方法は、マトリックス配線の断線や短絡交点に
対して、リペア線により迂回路を構成する方法であるの
で、修復が容易かつ有効になされる利点がある。
BEST MODE FOR CARRYING OUT THE INVENTION In the above wiring repair method for a TFT substrate, in a repair line group provided in a rectangular shape on a glass substrate around a matrix wiring, a plurality of repair lines are provided for each gate line and drain line. 2 of each of the leader lines
It is constructed by wiring with insulation crossing at a location and cutting one even number of each repair line. Now, when a certain gate line is broken at an arbitrary point, if any repair line and the lead line of the broken gate line are connected at two insulation intersections, respectively, it will be in front of the broken point. Each electrode element (on the side of the scanning circuit) operates by directly receiving the scanning signal from the scanning circuit, while each electrode element after the disconnection point forms a detour by the connected insulation intersections. , Operates by a scanning signal bypassing this. That is, the disconnection point is repaired. The same applies to the case where the drain wire is disconnected. Next, when the gate line and the drain line are short-circuited at a certain intersection of the matrix wiring, the gate line and the drain line are respectively cut in the vicinity of the short-circuited intersection to exclude the short-circuited intersection, and the excluded gate line and The lead line of the drain line is connected to any two insulation intersections with any two repair lines, and a detour for the short-circuiting intersection is formed and repaired in the same manner as described above. As described above, the repairing method of the present invention is a method of constructing a bypass line by a repair line with respect to a disconnection or a short-circuit intersection of a matrix wiring, and therefore has an advantage that repairing is easy and effective.

【0007】[0007]

【実施例】図1は、この発明を適用したTFT基板1の
一実施例を示す。TFT基板1のマトリックス配線の各
交点は一点鎖線の範囲内に存在する。各ドレイン線(D
1 〜Dn)と各ゲート線(G1 〜Gm)は、それぞれの引出
し線が一点鎖線の範囲外のガラス基板11の余白部に引出
されている。この余白部にマトリックス配線を包囲し
て、複数s本のリペア線(R1 〜Rs)を方形状に布線
し、各引出し線との交差点を絶縁し、例えば左上端を除
去してリペア線群15を構成する。各リペア線(R1 〜R
s)は、マトリックス配線と同一の線材で同一の直径のも
のが好ましく、マトリックス配線の形成時に容易に形成
することができる。いま、例えばゲート線G2 が図示の
×印の箇所で断線B1 しているときは、断線B1 の手前
の各電極素子14は、走査回路22(図2参照)よりの走査
信号を直接受ける。これに対して、例えばリペア線R1
をとり、これとゲート線G2 の2箇所の絶縁交差点pa,
b をそれぞれ接続すると、断線B1 のあとの各電極素
子14に対して、絶縁交差点pa,pb を経由するリペア線
1 の迂回路が構成され、走査信号はこれを迂回して、
これらの電極素子14に供給されて断線B1 が修復され
る。ドレイン線D3 が図示の×印の箇所で断線B2 して
いるときも同様で、例えばリペア線R2 をとり、2箇所
の絶縁交差点pc,pd を接続することにより、迂回路が
構成されて断線B2 が修復される。次に、任意のドレイ
ン線Dr とゲート線Gq とが、その交点で短絡Sしてい
るときは、短絡交点の近傍で両線をカットして短絡交点
を除外し、ドレイン線Drとゲート線Gq に対して、適
当な2本のリペア線Rp,Rq をとって、それぞれの絶縁
交差点pe,pf およびpg,ph を接続することにより、
両線に対する迂回路が構成されて交点の短絡Sが修復さ
れる。なおリペア線Rの本数sは、断線Bや交点の短絡
Sの発生頻度を勘案して、適切な値を決めればよい。
1 shows an embodiment of a TFT substrate 1 to which the present invention is applied. Each intersection of the matrix wirings of the TFT substrate 1 exists within the range of a chain line. Each drain wire (D
The lead lines of 1 to D n ) and the gate lines (G 1 to G m ) are drawn to the margins of the glass substrate 11 outside the range of the alternate long and short dash line. A matrix wiring is surrounded by this blank space, and a plurality of s repair lines (R 1 to R s ) are laid in a rectangular shape to insulate the intersection with each lead line, for example, removing the upper left end of the repair line. The line group 15 is formed. Each repair wire (R 1 ~ R
s ) is preferably the same wire material and the same diameter as the matrix wiring, and can be easily formed at the time of forming the matrix wiring. Now, for example, when the gate line G 2 has a disconnection B 1 at a portion marked by X, each electrode element 14 before the disconnection B 1 directly receives a scanning signal from the scanning circuit 22 (see FIG. 2). receive. On the other hand, for example, repair line R 1
, And two insulated intersections p a , of this and the gate line G 2 .
When p b is respectively connected, a bypass line of the repair line R 1 via the insulating intersections p a and p b is formed for each electrode element 14 after the disconnection B 1 , and the scanning signal bypasses this. ,
The disconnection B 1 is repaired by being supplied to these electrode elements 14. The same applies when the drain line D 3 is disconnected B 2 at a point × mark shown, for example, take the repair line R 2, 2 points insulating intersection p c, by connecting the p d, detours Once constructed, the disconnection B 2 is repaired. Next, when the arbitrary drain line D r and the gate line G q are short-circuited S at the intersection, both lines are cut in the vicinity of the short-circuiting intersection to exclude the short-circuiting intersection, and the drain line D r and By taking two appropriate repair lines R p and R q with respect to the gate line G q and connecting the respective insulation intersections p e and p f and p g and p h ,
A detour is constructed for both lines and the short circuit S at the intersection is repaired. The number s of repair lines R may be determined as an appropriate value in consideration of the frequency of occurrence of the disconnection B and the short circuit S at the intersection.

【0008】[0008]

【発明の効果】以上の説明のとおり、この発明による配
線修復方法によれば、リペア線によりマトリックス配線
の断線、または交点の短絡に対する迂回路が構成され
て、従来困難であったこれらの欠陥の修復が有効かつ容
易になされ、TFT基板の製品の歩止まりの向上に寄与
する効果には大きいものがある。
As described above, according to the wiring repairing method of the present invention, the repair line constitutes the detour path for the disconnection of the matrix wiring or the short-circuiting of the intersections. The repair is effective and easy, and there is a great effect to contribute to the improvement of the yield of the TFT substrate product.

【図面の簡単な説明】[Brief description of drawings]

【図1】 図1は、この発明を適用したTFT基板1の
一実施例の構成図である。
FIG. 1 is a configuration diagram of an embodiment of a TFT substrate 1 to which the present invention is applied.

【図2】 図2は、TFT基板1の構成と、制御部2の
説明図である。
FIG. 2 is an explanatory diagram of a configuration of a TFT substrate 1 and a control unit 2.

【図3】 図3は、マトリックス配線に発生した断線と
短絡の説明図である。
FIG. 3 is an explanatory diagram of disconnection and short circuit occurring in matrix wiring.

【符号の説明】[Explanation of symbols]

1…TFT基板、11…ガラス基板、12…ゲート線G、13
…ドレイン線D、14…電極素子、15…リペア線群、2…
制御部、21…データ回路、22…走査回路、B…断線、E
…接地、S…交点の短絡、R1 〜Rs …s本のリペア
線、pa 〜ph …接続される絶縁交差点。
1 ... TFT substrate, 11 ... Glass substrate, 12 ... Gate line G, 13
... Drain line D, 14 ... Electrode element, 15 ... Repair line group, 2 ...
Control unit, 21 ... Data circuit, 22 ... Scanning circuit, B ... Disconnection, E
Insulating intersection ... ground, short-circuiting of S ... intersections, R 1 to R s ... s book repair line is p a ~p h ... connection.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】方形のガラス基板の表面に、複数本のX電
極とY電極とをマトリックス配線し、該マトリックス配
線の各交点にTFTよりなる電極素子を有するTFT基
板において、該マトリックス配線の周囲の該ガラス基板
上に、複数本のリペア線を、前記各X電極およびY電極
の引出し線のそれぞれと2箇所で絶縁交差して方形状に
配線し、かつ該方形状の各リペア線の1偶をカットして
構成されたリペア線群を設け、任意の前記X電極または
Y電極が任意の箇所で断線しているとき、該リペア線群
のいずれかのリペア線と、該X電極またはY電極の引出
し線との、前記2箇所の絶縁交差点をそれぞれ接続し
て、該断線箇所に対する迂回路を構成して修復すること
を特徴とする、TFT基板の配線欠陥修復方法。
1. A TFT substrate having a rectangular glass substrate on the surface of which a plurality of X electrodes and Y electrodes are matrix-wired, and having an electrode element made of a TFT at each intersection of the matrix wires. On the glass substrate, a plurality of repair wires are insulated and intersected at two points with each of the lead wires of each of the X electrodes and the Y electrodes, and the repair wires are wired in a square shape. When a repair line group configured by cutting even numbers is provided and any X electrode or Y electrode is disconnected at any place, any repair line of the repair line group and the X electrode or Y A method for repairing a wiring defect of a TFT substrate, characterized in that the above-mentioned two insulating intersections with a lead wire of an electrode are connected to each other to form a detour path to the disconnected portion and repair the wiring defect.
【請求項2】前記X電極はゲート線であり、前記Y電極
はドレイン線であって、前記マトリックス配線の任意の
交点で前記ゲート線と前記ドレイン線とが短絡している
とき、該短絡交点の近傍で該ゲート線とドレイン線とを
それぞれカットして該短絡交点を除外し、該短絡点が除
外されたゲート線およびドレイン線の引出し線と、前記
リペア線群のいずれか2本のリペア線との、それぞれの
2箇所の前記絶縁交差点を接続して、該短絡交点に対す
る迂回路を構成して修復することを特徴とする、請求項
1記載のTFT基板の配線欠陥修復方法。
2. The X electrode is a gate line, the Y electrode is a drain line, and when the gate line and the drain line are short-circuited at any intersection of the matrix wiring, the short-circuit intersection , The gate line and the drain line are respectively cut to exclude the short-circuit intersection, the lead line of the gate line and the drain line from which the short-circuit point is excluded, and any two repair lines of the repair line group. 2. The method for repairing a wiring defect of a TFT substrate according to claim 1, wherein each of the two insulated intersections with a line is connected to form a detour for the short-circuited intersection and repaired.
JP26214095A 1995-09-14 1995-09-14 Method for repairing wiring defect of tft substrate Pending JPH0980470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26214095A JPH0980470A (en) 1995-09-14 1995-09-14 Method for repairing wiring defect of tft substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26214095A JPH0980470A (en) 1995-09-14 1995-09-14 Method for repairing wiring defect of tft substrate

Publications (1)

Publication Number Publication Date
JPH0980470A true JPH0980470A (en) 1997-03-28

Family

ID=17371616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26214095A Pending JPH0980470A (en) 1995-09-14 1995-09-14 Method for repairing wiring defect of tft substrate

Country Status (1)

Country Link
JP (1) JPH0980470A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670595B1 (en) * 1999-08-02 2003-12-30 Olympus Optical Co., Ltd. Photosensor and photosensor system
KR100490040B1 (en) * 1997-12-05 2005-09-06 삼성전자주식회사 Liquid crystal display device with two or more shorting bars and method for manufacturing same
JP2006171672A (en) * 2004-12-10 2006-06-29 Samsung Electronics Co Ltd Array substrate, display apparatus having array substrate and method for repairing array substrate
KR100692866B1 (en) * 2005-11-29 2007-03-09 엘지전자 주식회사 Organic electro-luminescence display device and method for fabricating and repairing the same
KR100816326B1 (en) * 2001-01-18 2008-03-24 삼성전자주식회사 liquid crystal display having repair lines and repairing method thereof
WO2009151243A3 (en) * 2008-06-09 2010-02-25 주식회사 토비스 Liquid crystal display and method for repairing the same
JP2014527195A (en) * 2011-08-02 2014-10-09 京東方科技集團股▲ふん▼有限公司 Array substrate, liquid crystal display panel and method for repairing disconnection thereof
US9018632B2 (en) 2011-04-28 2015-04-28 Sharp Kabushiki Kaisha TFT substrate and method for correcting wiring fault on TFT substrate
WO2018068542A1 (en) * 2016-10-14 2018-04-19 京东方科技集团股份有限公司 Array substrate and display device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100490040B1 (en) * 1997-12-05 2005-09-06 삼성전자주식회사 Liquid crystal display device with two or more shorting bars and method for manufacturing same
US6670595B1 (en) * 1999-08-02 2003-12-30 Olympus Optical Co., Ltd. Photosensor and photosensor system
KR100816326B1 (en) * 2001-01-18 2008-03-24 삼성전자주식회사 liquid crystal display having repair lines and repairing method thereof
JP2006171672A (en) * 2004-12-10 2006-06-29 Samsung Electronics Co Ltd Array substrate, display apparatus having array substrate and method for repairing array substrate
KR100692866B1 (en) * 2005-11-29 2007-03-09 엘지전자 주식회사 Organic electro-luminescence display device and method for fabricating and repairing the same
WO2009151243A3 (en) * 2008-06-09 2010-02-25 주식회사 토비스 Liquid crystal display and method for repairing the same
US9018632B2 (en) 2011-04-28 2015-04-28 Sharp Kabushiki Kaisha TFT substrate and method for correcting wiring fault on TFT substrate
JP2014527195A (en) * 2011-08-02 2014-10-09 京東方科技集團股▲ふん▼有限公司 Array substrate, liquid crystal display panel and method for repairing disconnection thereof
US10068813B2 (en) 2011-08-02 2018-09-04 Boe Technology Group Co., Ltd. Array substrate, liquid crystal display panel and broken-line repairing method thereof
WO2018068542A1 (en) * 2016-10-14 2018-04-19 京东方科技集团股份有限公司 Array substrate and display device
US10546879B2 (en) 2016-10-14 2020-01-28 Boe Technology Group Co., Ltd. Array substrate and display device

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