JPH05333370A - Active matrix type liquid crystal display element - Google Patents

Active matrix type liquid crystal display element

Info

Publication number
JPH05333370A
JPH05333370A JP13704492A JP13704492A JPH05333370A JP H05333370 A JPH05333370 A JP H05333370A JP 13704492 A JP13704492 A JP 13704492A JP 13704492 A JP13704492 A JP 13704492A JP H05333370 A JPH05333370 A JP H05333370A
Authority
JP
Japan
Prior art keywords
signal line
thin film
disconnection
film transistor
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13704492A
Other languages
Japanese (ja)
Inventor
Yoshihiro Asai
義裕 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13704492A priority Critical patent/JPH05333370A/en
Publication of JPH05333370A publication Critical patent/JPH05333370A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136272Auxiliary lines

Landscapes

  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To provide the active matrix type liquid crystal display element improving the yield. CONSTITUTION:When an array board 26 is completed, the disconnection of a signal line 22 is inspected by measuring resistance at both of terminals of the signal line 22. Concerning the signal line 22 discovered the disconnection at a point X, a selecting voltage Vg is impressed between the gate and source of second thin film transistors at both of terminals connected to this signal line 22, and the respective second thin film transistors 27 are turned on. The disconnection of wiring 25 for repair is inspected by measuring resistance values at both of terminals of the signal line 22. When there is no problem as the result of the disconnection inspection, the crossing part of the signal line 22 having the disconnection and the wiring 25 for repair is irradiated with laser beams L from the side of an insulated board 21. Then, the signal line 22 and the wiring 25 for repair are short-circuited, the wiring 25 for repair is bypassed, and the disconnection of the signal line 22 is relieved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄膜トランジスタ(Th
in Film Transistor)をスイッチ素子として表示を行な
うアクティブマトリクス型液晶表示素子に関する。
The present invention relates to a thin film transistor (Th
The present invention relates to an active matrix type liquid crystal display element that performs display using in film transistor as a switch element.

【0002】[0002]

【従来の技術】近年、液晶を用いた表示素子は、テレビ
表示やグラフィックディスプレイなどを指向し、大容量
で高密度のアクティブマトリクス型表示素子の開発およ
び実用化が盛んである。
2. Description of the Related Art In recent years, display devices using liquid crystals are directed to television displays and graphic displays, and active matrix type display devices of large capacity and high density have been developed and put to practical use.

【0003】そして、このような表示素子では、クロス
トークのない高コントラストの表示を行なえるように、
各画素の駆動と制御を行なう手段として半導体スイッチ
が用いられる。この半導体スイッチとしては、透過型表
示が可能であり大面積化も容易であるなどの理由から、
一般に、絶縁基板上に形成された薄膜トランジスタなど
が用いられている。
In such a display device, high contrast display without crosstalk can be achieved.
A semiconductor switch is used as a means for driving and controlling each pixel. As this semiconductor switch, a transmissive display is possible and it is easy to increase the area.
Generally, a thin film transistor or the like formed on an insulating substrate is used.

【0004】また、従来はこの種の表示素子としてたと
えば特開昭61−4095号公報に記載された構成が知
られている。この特開昭61−4095号公報には、図
6に示すような構成が記載されている。
Further, conventionally, as a display element of this type, a structure described in, for example, Japanese Patent Application Laid-Open No. 61-4095 is known. This Japanese Patent Application Laid-Open No. 61-4095 discloses a structure as shown in FIG.

【0005】そして、図6に示すように、絶縁基板1上
には薄膜トランジスタ2が形成され、この薄膜トランジ
スタ2に接続して透明導電膜からなる表示画素電極3が
配列形成されている。一方、絶縁基板1に対向して絶縁
基板4が設けられ、この絶縁基板4の絶縁基板1に対向
する面上に、透明導電膜からなる対向電極5を全面に形
成されている。そして、絶縁基板1,4の間には液晶6
が挟持され、この液晶6の周囲を封着剤7で封止する。
そうして、薄膜トランジスタ2および表示画素電極3な
どが形成された絶縁基板1にてアレイ基板8が構成さ
れ、対向電極5が形成された絶縁基板4にて対向基板9
が構成される。
Then, as shown in FIG. 6, a thin film transistor 2 is formed on an insulating substrate 1, and a display pixel electrode 3 made of a transparent conductive film is formed in an array so as to be connected to the thin film transistor 2. On the other hand, an insulating substrate 4 is provided so as to face the insulating substrate 1, and a counter electrode 5 made of a transparent conductive film is formed on the entire surface of the surface of the insulating substrate 4 facing the insulating substrate 1. The liquid crystal 6 is placed between the insulating substrates 1 and 4.
Are sandwiched, and the periphery of the liquid crystal 6 is sealed with a sealing agent 7.
Then, the array substrate 8 is configured by the insulating substrate 1 on which the thin film transistor 2 and the display pixel electrode 3 and the like are formed, and the opposing substrate 9 is formed by the insulating substrate 4 on which the counter electrode 5 is formed.
Is configured.

【0006】さらに、図7に示すように、アレイ基板8
上には複数本の信号線10とこの信号線10に直交する複数
本の走査線11とが形成される。また、アレイ基板8の薄
膜トランジスタ2および表示画素電極3からなる画素領
域12外の部分に、信号線10および走査線11を囲うように
コ字状に信号線10の断線を補修するための補修用配線13
が設けられている。
Further, as shown in FIG. 7, the array substrate 8
A plurality of signal lines 10 and a plurality of scanning lines 11 orthogonal to the signal lines 10 are formed on the top. In addition, for repairing to repair the disconnection of the signal line 10 in a U shape so as to surround the signal line 10 and the scanning line 11 in a portion outside the pixel region 12 formed of the thin film transistor 2 and the display pixel electrode 3 of the array substrate 8. Wiring 13
Is provided.

【0007】そして、各信号線10の片端には駆動回路か
ら信号電圧を供給するための信号線パッド15が設けら
れ、同様に走査線11の片端にはゲート電圧を供給するた
めの走査線パッド16が設けられている。また、図8に示
すように、信号線10と補修用配線13とはゲート絶縁膜14
を挟んで交差して設けられている。
A signal line pad 15 for supplying a signal voltage from the driving circuit is provided at one end of each signal line 10, and a scanning line pad for supplying a gate voltage is similarly provided at one end of the scanning line 11. 16 are provided. In addition, as shown in FIG. 8, the signal line 10 and the repair wiring 13 are connected to the gate insulating film 14
Are crossed across.

【0008】また、信号線10のたとえばX点に断線があ
る場合には、この断線している信号線10と補修用配線13
との2か所の交差部分であるY1点、Y2点にアレイ基板8
側からレーザ・ビームLを照射し、信号線10と補修用配
線13を短絡させる。そして、断線部分であるX点から先
の画素には、補修用配線13を経由して信号電圧が供給さ
れるため、信号線10の断線によって生じる線欠陥不良は
救済される。
If there is a break in the signal line 10, for example, at the point X, the broken signal line 10 and the repair wiring 13
Array substrate 8 at Y1 point and Y2 point, which are two intersections with
The laser beam L is irradiated from the side to short-circuit the signal line 10 and the repair wiring 13. Then, since the signal voltage is supplied to the pixel beyond the point X, which is the disconnection portion, through the repair wiring 13, the line defect defect caused by the disconnection of the signal line 10 is relieved.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、この種
の液晶表示素子では、製造工程中において発生するゴミ
等に起因して補修用配線13にも断線が生じる。このた
め、たとえば図7に示すZ点にて補修用配線13が断線し
ている場合には、交差部分であるY1点、Y2点にて信号線
10と補修用配線13を短絡させているのにもかかわらず、
X点よりも先の表示画素電極3には信号電圧は供給され
ず、信号線10の欠陥を救済することはできない。
However, in this type of liquid crystal display element, the repair wiring 13 is also broken due to dust or the like generated during the manufacturing process. Therefore, for example, when the repair wiring 13 is broken at the Z point shown in FIG. 7, the signal line is made at the Y1 point and the Y2 point which are the intersections.
Despite shorting 10 and the repair wiring 13,
No signal voltage is supplied to the display pixel electrode 3 beyond the point X, and the defect of the signal line 10 cannot be repaired.

【0010】また、補修用配線13のZ点の位置によって
は、断線救済できる信号線10が限定される。そして、こ
れら補修用配線13を検査することはアレイ基板8の工程
中および完成時には不可能であるため、断線している信
号線10のY1点、Y2点に相当する交差部分をレーザ・ビー
ムLなどで短絡させた後に、実際に液晶表示素子を駆動
させて画出し検査をするまではわからない問題を有して
いる。
Further, depending on the position of the Z point of the repair wiring 13, the signal line 10 which can be repaired by disconnection is limited. Since it is impossible to inspect these repair wirings 13 during the process of the array substrate 8 and at the time of completion thereof, the laser beam L is applied to the intersecting portions corresponding to the Y1 point and the Y2 point of the broken signal line 10. However, there is a problem that cannot be understood until the liquid crystal display element is actually driven and an image output inspection is performed after the short circuit is made by such as.

【0011】さらに、走査線11側についても信号線10と
同様の問題を有している。
Further, the scanning line 11 side has the same problem as the signal line 10.

【0012】本発明は、上記問題点に鑑みなされたもの
で、歩留まりを向上したアクティブマトリクス型液晶表
示素子を提供することを目的とする。
The present invention has been made in view of the above problems, and an object thereof is to provide an active matrix type liquid crystal display device having an improved yield.

【0013】[0013]

【課題を解決するための手段】本発明は、絶縁基板の一
主面上に複数本の走査線および信号線をマトリクス状に
交差させて配設し、これら走査線および信号線の交点付
近に第1の薄膜トランジスタおよびこの第1の薄膜トラ
ンジスタに接続される表示画素電極からなる一画素を配
した画素領域、および、この画素領域外に前記走査線ま
たは前記信号線の断線を補修する補修用配線を有するア
レイ基板と、前記絶縁基板の一主面上に対向電極を形成
してなる対向基板と、前記アレイ基板と前記対向基板を
互いの前記一主面側が対向して挟持される液晶層とを備
えたアクティブマトリクス型液晶表示素子において、前
記補修用配線と前記走査線および前記信号線の内少なく
ともいずれか一方との交点付近に第2の薄膜トランジス
タを設け、この第2の薄膜トランジスタのソース電極と
ドレイン電極を各々前記補修用配線と前記走査線および
前記信号線の内少なくともいずれか一方に接続したもの
である。
According to the present invention, a plurality of scanning lines and signal lines are arranged in a matrix on one main surface of an insulating substrate, and the scanning lines and the signal lines are provided in the vicinity of the intersections thereof. A pixel region in which one pixel including a first thin film transistor and a display pixel electrode connected to the first thin film transistor is arranged, and a repair wiring for repairing the disconnection of the scanning line or the signal line is provided outside the pixel region. An array substrate having; a counter substrate in which a counter electrode is formed on one main surface of the insulating substrate; and a liquid crystal layer sandwiching the array substrate and the counter substrate so that the one main surface sides face each other. In an active matrix type liquid crystal display device provided with the second thin film transistor, a second thin film transistor is provided near an intersection of the repair wiring and at least one of the scanning line and the signal line. Which are connected to at least one of the source electrode and the drain electrode of the thin film transistors each said repair wire the scanning lines and the signal lines.

【0014】[0014]

【作用】本発明は、補修用配線と走査線または信号線と
の交点付近に、第2の薄膜トランジスタを設け、この第
2の薄膜トランジスタのソース電極とドレイン電極は各
々補修用配線と走査線および信号線の内少なくともいず
れか一方に接続したことにより、この第2の薄膜トラン
ジスタをオン状態とした場合に、信号線または走査線と
補修用配線とが導通するため、断線した信号線または走
査線の両端間の導通検査をすることによって、断線救済
の成否を検査することができるので、補修用配線の断線
に起因した信号線または走査線の欠陥を製造中に検査で
き、歩留まりの低下を防ぐことができる。
According to the present invention, the second thin film transistor is provided near the intersection of the repair wiring and the scanning line or the signal line, and the source electrode and the drain electrode of the second thin film transistor are respectively the repair wiring, the scanning line and the signal line. By connecting to at least one of the lines, when the second thin film transistor is turned on, the signal line or the scanning line and the repair wiring are electrically connected, and therefore both ends of the broken signal line or the scanning line are connected. By conducting a continuity test between the two, it is possible to inspect the success or failure of the disconnection repair, so that it is possible to inspect the signal line or the scanning line defect due to the disconnection of the repair wiring during the manufacturing process, and it is possible to prevent the yield from decreasing. it can.

【0015】[0015]

【実施例】以下、本発明のアクティブマトリクス型液晶
表示素子の一実施例を図面を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the active matrix type liquid crystal display device of the present invention will be described below with reference to the drawings.

【0016】図1および図4に示すように、絶縁基板21
の一主面上に平行な複数本の走査線23および平行な複数
本の信号線22をマトリクス状に交差させて配設する。そ
して、これら走査線23および信号線22の交点付近に、図
示しない第1の薄膜トランジスタおよびこの第1の薄膜
トランジスタに接続される表示画素電極からなる一画素
を配設する。なお、表示画素電極が設けられた部分を画
素領域24とする。そして、この画素領域24外の部分に、
信号線22の両端付近で走査線23と平行に、かつ、信号線
22の一端側で信号線22と平行になり略コ字状に形成され
た信号線22の断線補修をするための補修用配線25を形成
して、アレイ基板26を構成する。
As shown in FIGS. 1 and 4, the insulating substrate 21
A plurality of parallel scanning lines 23 and a plurality of parallel signal lines 22 are arranged in a matrix on one main surface so as to intersect each other. Then, in the vicinity of the intersection of the scanning line 23 and the signal line 22, one pixel including a first thin film transistor (not shown) and a display pixel electrode connected to the first thin film transistor is arranged. The portion where the display pixel electrode is provided is referred to as a pixel region 24. Then, in a portion outside the pixel area 24,
Parallel to the scanning line 23 near both ends of the signal line 22, and
An array substrate 26 is formed by forming repair wiring 25 for repairing disconnection of the signal line 22 which is formed in a substantially U shape in parallel with the signal line 22 on one end side of 22.

【0017】また、信号線22と補修用配線25との交点近
傍には、第2の薄膜トランジスタ27を形成し、この第2
の薄膜トランジスタ27のソース電極28に信号線22を接続
し、ドレイン電極29に補修用配線25を接続する。
A second thin film transistor 27 is formed near the intersection of the signal line 22 and the repair wiring 25.
The signal line 22 is connected to the source electrode 28 of the thin film transistor 27, and the repair wiring 25 is connected to the drain electrode 29.

【0018】そして、アレイ基板26には、対向して図示
しない対向基板を設ける。また、絶縁基板の一主面上に
は対向電極を形成し、アレイ基板26と対向基板を対向す
る互いの一主面側に液晶層を挟持させる。
The array substrate 26 is provided with a counter substrate (not shown) so as to face it. Further, a counter electrode is formed on one main surface of the insulating substrate, and a liquid crystal layer is sandwiched between the two main surfaces of the array substrate 26 and the counter substrate which face each other.

【0019】この第2の薄膜トランジスタ27は、図4に
示すように、絶縁基板21上に、ゲート電極31を形成し、
このゲート電極31を含めた全面に、ゲート絶縁膜32を形
成する。また、このゲート絶縁膜32のゲート電極31上に
は、半導体層33および絶縁体層34を順次形成する。さら
に、半導体層33上に、オーミック層35,36を形成し、こ
れらオーミック層35,36上には、それぞれソース電極28
およびドレイン電極29を形成する。そうして、全面に保
護層37を形成する。また、図示しない第1の薄膜トラン
ジスタもこの第2の薄膜トランジスタ27と同様に形成さ
れる。
In the second thin film transistor 27, as shown in FIG. 4, a gate electrode 31 is formed on an insulating substrate 21,
A gate insulating film 32 is formed on the entire surface including the gate electrode 31. Further, the semiconductor layer 33 and the insulator layer 34 are sequentially formed on the gate electrode 31 of the gate insulating film 32. Further, ohmic layers 35 and 36 are formed on the semiconductor layer 33, and the source electrode 28 is formed on the ohmic layers 35 and 36, respectively.
And the drain electrode 29 is formed. Then, the protective layer 37 is formed on the entire surface. The first thin film transistor (not shown) is also formed in the same manner as the second thin film transistor 27.

【0020】一方、補修用配線25は、図5に示すよう
に、絶縁基板21上に、補修用配線25を形成し、この補修
用配線25上にゲート絶縁膜32を形成し、このゲート絶縁
膜32上に補修用配線25と交差する方向に、信号線22を形
成し、全面に保護層37を形成する。
On the other hand, as for the repair wiring 25, as shown in FIG. 5, the repair wiring 25 is formed on the insulating substrate 21, and the gate insulating film 32 is formed on the repair wiring 25. A signal line 22 is formed on the film 32 in a direction intersecting with the repair wiring 25, and a protective layer 37 is formed on the entire surface.

【0021】また、図3に示すように、ソース電極28お
よび補修用配線25には検査用のソースパッド41が形成さ
れ、ゲート電極31には検査用のゲートパッド42が形成さ
れている。
Further, as shown in FIG. 3, a source electrode 41 for inspection is formed on the source electrode 28 and the repair wiring 25, and a gate pad 42 for inspection is formed on the gate electrode 31.

【0022】さらに、ドレイン電極29はゲート絶縁膜32
に形成されたスルーホール43を介して補修用配線25に接
続され、ゲート電極31はゲート絶縁膜32に形成されたス
ルーホール44により、表面に露出されている。
Further, the drain electrode 29 is a gate insulating film 32.
The gate electrode 31 is connected to the repair wiring 25 through the through hole 43 formed in the gate electrode 31 and is exposed on the surface by the through hole 44 formed in the gate insulating film 32.

【0023】なお、補修用配線は、走査線23に対しても
同様に形成すればよい。
The repair wiring may be similarly formed for the scanning line 23.

【0024】次に、上記実施例の使用方法について説明
する。
Next, a method of using the above embodiment will be described.

【0025】まず、アレイ基板26の完成時においては、
信号線22の両端の抵抗を測定することによって信号線22
の断線検査をする。そして、たとえばX点に断線が発見
された信号線22に対しては、この信号線22に接続された
両端の第2の薄膜トランジスタ27のゲート・ソース間に
選択電圧Vgを与えて、それぞれの第2の薄膜トランジ
スタ27をオン状態とさせる。この信号線22の両端の抵抗
値を再び測定することによって、補修用配線25の断線検
査を行なう。そうして、この断線検査で問題がなけれ
ば、図5に示すように、断線を有する信号線22と補修用
配線25との交差部分を、絶縁基板21側からレーザ・ビー
ムLを照射することにより、信号線22と補修用配線25と
を短絡させることによって、補修用配線25をバイパスと
し、信号線22の断線を救済する。
First, when the array substrate 26 is completed,
Signal line 22 is measured by measuring the resistance across signal line 22.
Check for disconnection. Then, for example, for the signal line 22 in which the disconnection is found at the point X, the selection voltage Vg is applied between the gate and the source of the second thin film transistors 27 at both ends connected to the signal line 22, and each of the second thin film transistors 27 is supplied with the selection voltage. The second thin film transistor 27 is turned on. The resistance value at both ends of the signal line 22 is measured again to perform a disconnection inspection of the repair wiring 25. Then, if there is no problem in this disconnection inspection, as shown in FIG. 5, the intersection of the signal line 22 having the disconnection and the repair wiring 25 is irradiated with the laser beam L from the insulating substrate 21 side. Thus, by short-circuiting the signal line 22 and the repair wiring 25, the repair wiring 25 is bypassed and the disconnection of the signal line 22 is repaired.

【0026】そして、図2に示すように、各信号線22に
信号ホールド回路51を接続し、各走査線23に走査回路52
を接続して完成する。
Then, as shown in FIG. 2, a signal hold circuit 51 is connected to each signal line 22 and a scanning circuit 52 is connected to each scanning line 23.
Connect and complete.

【0027】上記実施例によれば、信号線22または走査
線23の断線を補修するための補修用配線25と、信号線22
または走査線23の交点付近に第2の薄膜トランジスタ27
を設けることによって、アレイ基板26の完成時における
補修用配線25の断線の検査を可能にする。したがって、
信号線22または走査線23の断線の救済に失敗した不良な
アレイ基板のセル工程への流れ込みを防ぐことができる
ため、セル工程歩留まりを向上させて、安価な液晶表示
装置を提供することができる。
According to the above embodiment, the repair wiring 25 for repairing the disconnection of the signal line 22 or the scanning line 23, and the signal line 22.
Alternatively, the second thin film transistor 27 is provided near the intersection of the scanning lines 23.
By providing the above, it becomes possible to inspect the repair wiring 25 for disconnection when the array substrate 26 is completed. Therefore,
Since it is possible to prevent the defective array substrate, which has failed to repair the disconnection of the signal line 22 or the scanning line 23, from flowing into the cell process, it is possible to improve the cell process yield and provide an inexpensive liquid crystal display device. .

【0028】また、第2の薄膜トランジスタ27も第1の
薄膜トランジスタと同様に形成されるので、製造工程は
複雑にならない。
Since the second thin film transistor 27 is also formed in the same manner as the first thin film transistor, the manufacturing process does not become complicated.

【0029】[0029]

【発明の効果】本発明のアクティブマトリクス型液晶表
示素子によれば、補修用配線と走査線または信号線との
交点付近に、第2の薄膜トランジスタを設け、この第2
の薄膜トランジスタのソース電極とドレイン電極は各々
補修用配線と走査線および信号線の内少なくともいずれ
か一方に接続したことにより、この第2の薄膜トランジ
スタをオン状態とした場合に、信号線または走査線と補
修用配線とが導通するため、断線した信号線または走査
線の両端間の導通検査をすることによって、断線救済の
成否を検査することができるので、補修用配線の断線に
起因した信号線または走査線の欠陥を製造中に検査で
き、歩留まりの低下を防ぐことができる。
According to the active matrix type liquid crystal display element of the present invention, a second thin film transistor is provided near the intersection of the repair wiring and the scanning line or the signal line.
Since the source electrode and the drain electrode of the thin film transistor are connected to at least one of the repair wiring, the scanning line and the signal line, when the second thin film transistor is turned on, the source electrode and the drain electrode are connected to the signal line or the scanning line. Since the repair wiring is electrically connected, the success or failure of the disconnection repair can be inspected by conducting a continuity test between both ends of the broken signal line or scanning line. Scan line defects can be inspected during manufacturing, and a decrease in yield can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のアクティブマトリクス型液晶表示素子
の一実施例の検査時を示す等価回路図である。
FIG. 1 is an equivalent circuit diagram showing a test time of an embodiment of an active matrix type liquid crystal display device of the present invention.

【図2】同上補修後を示す等価回路図である。FIG. 2 is an equivalent circuit diagram showing the same as above.

【図3】同上信号線と補修用配線の交点付近に設けた薄
膜トランジスタの構造を示す平面図である。
FIG. 3 is a plan view showing a structure of a thin film transistor provided in the vicinity of an intersection of a signal line and a repair wiring as above.

【図4】同上第2の薄膜トランジスタを示す図3のIVー
IV断面図である。
4 is the same as the second thin film transistor of FIG.
It is an IV sectional view.

【図5】同上信号線および補修用配線を示す図3のVー
V断面図である。
5 is a sectional view taken along line VV of FIG. 3 showing the signal line and the repair wiring.

【図6】従来のアクティブマトリクス型液晶表示素子を
示す断面図である。
FIG. 6 is a cross-sectional view showing a conventional active matrix type liquid crystal display element.

【図7】同上補修後を示す等価回路図である。FIG. 7 is an equivalent circuit diagram showing the same as above.

【図8】同上信号線および補修用配線を示す断面図であ
る。
FIG. 8 is a cross-sectional view showing the signal line and the repair wiring of the above.

【符号の説明】[Explanation of symbols]

22 信号線 23 走査線 24 画素領域 25 補修用配線 26 アレイ基板 27 第2の薄膜トランジスタ 22 signal line 23 scanning line 24 pixel region 25 repair wiring 26 array substrate 27 second thin film transistor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板の一主面上に複数本の走査線お
よび信号線をマトリクス状に交差させて配設し、これら
走査線および信号線の交点付近に第1の薄膜トランジス
タおよびこの第1の薄膜トランジスタに接続される表示
画素電極からなる一画素を配した画素領域、および、こ
の画素領域外に前記走査線または前記信号線の断線を補
修する補修用配線を有するアレイ基板と、前記絶縁基板
の一主面上に対向電極を形成してなる対向基板と、前記
アレイ基板と前記対向基板を互いの前記一主面側が対向
して挟持される液晶層とを備えたアクティブマトリクス
型液晶表示素子において、 前記補修用配線と前記走査線および前記信号線の内少な
くともいずれか一方との交点付近に第2の薄膜トランジ
スタを設け、この第2の薄膜トランジスタのソース電極
とドレイン電極を各々前記補修用配線と前記走査線およ
び前記信号線の内少なくともいずれか一方に接続したこ
とを特徴とするアクティブマトリクス型液晶表示素子。
1. A plurality of scanning lines and signal lines are arranged on a main surface of an insulating substrate so as to intersect each other in a matrix, and a first thin film transistor and the first thin film transistor are provided in the vicinity of an intersection of these scanning lines and signal lines. An array substrate having a pixel region in which one pixel including a display pixel electrode connected to the thin film transistor is arranged, and a repair wiring for repairing the disconnection of the scanning line or the signal line outside the pixel region; and the insulating substrate. An active matrix type liquid crystal display device comprising: a counter substrate having a counter electrode formed on one principal surface thereof; and a liquid crystal layer sandwiching the array substrate and the counter substrate so that the one principal surface sides thereof face each other. In the above, a second thin film transistor is provided in the vicinity of an intersection of the repair wiring and at least one of the scanning line and the signal line. Active matrix liquid crystal display element characterized scan electrode and the drain electrode respectively and the repair wiring that connects the to at least one of the scanning lines and the signal lines.
JP13704492A 1992-05-28 1992-05-28 Active matrix type liquid crystal display element Pending JPH05333370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13704492A JPH05333370A (en) 1992-05-28 1992-05-28 Active matrix type liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13704492A JPH05333370A (en) 1992-05-28 1992-05-28 Active matrix type liquid crystal display element

Publications (1)

Publication Number Publication Date
JPH05333370A true JPH05333370A (en) 1993-12-17

Family

ID=15189560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13704492A Pending JPH05333370A (en) 1992-05-28 1992-05-28 Active matrix type liquid crystal display element

Country Status (1)

Country Link
JP (1) JPH05333370A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2752624A1 (en) * 1996-07-11 1998-02-27 Lg Electronics Inc REPAIR SYSTEM FOR A LIQUID CRYSTAL DISPLAY
JPH10177844A (en) * 1996-12-19 1998-06-30 Hitachi Ltd Manufacture of planar display panel and manufacture of plasma display panel
JP2005234492A (en) * 2004-02-23 2005-09-02 Fujitsu Display Technologies Corp Substrate for display device, liquid crystal display panel, liquid crystal display device, and defect inspection method of wiring for repair
CN100437312C (en) * 2000-11-27 2008-11-26 株式会社日立制作所 Liquid crystal display device
US8023059B2 (en) 2007-12-26 2011-09-20 Infovision Optoelectronics (Kunshan) Co., Ltd. Array substrate of liquid crystal display, method of repairing same, and liquid crystal display
CN103207487A (en) * 2013-03-26 2013-07-17 北京京东方光电科技有限公司 Array substrate, display device and method for maintaining array substrate
WO2014056244A1 (en) * 2012-10-11 2014-04-17 深圳市华星光电技术有限公司 Array substrate, psva-type liquid crystal display panel and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2752624A1 (en) * 1996-07-11 1998-02-27 Lg Electronics Inc REPAIR SYSTEM FOR A LIQUID CRYSTAL DISPLAY
JPH10177844A (en) * 1996-12-19 1998-06-30 Hitachi Ltd Manufacture of planar display panel and manufacture of plasma display panel
CN100437312C (en) * 2000-11-27 2008-11-26 株式会社日立制作所 Liquid crystal display device
JP2005234492A (en) * 2004-02-23 2005-09-02 Fujitsu Display Technologies Corp Substrate for display device, liquid crystal display panel, liquid crystal display device, and defect inspection method of wiring for repair
JP4640916B2 (en) * 2004-02-23 2011-03-02 シャープ株式会社 Substrate for display device, liquid crystal display panel, liquid crystal display device, and defect inspection method for repair wiring
US8023059B2 (en) 2007-12-26 2011-09-20 Infovision Optoelectronics (Kunshan) Co., Ltd. Array substrate of liquid crystal display, method of repairing same, and liquid crystal display
WO2014056244A1 (en) * 2012-10-11 2014-04-17 深圳市华星光电技术有限公司 Array substrate, psva-type liquid crystal display panel and manufacturing method thereof
CN103207487A (en) * 2013-03-26 2013-07-17 北京京东方光电科技有限公司 Array substrate, display device and method for maintaining array substrate
WO2014153894A1 (en) * 2013-03-26 2014-10-02 京东方科技集团股份有限公司 Array substrate, display device and array substrate maintenance method
CN103207487B (en) * 2013-03-26 2015-08-05 北京京东方光电科技有限公司 The method for maintaining of array base palte, display device and array base palte

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