JPH05333377A - Manufacture of liquid crystal display device - Google Patents
Manufacture of liquid crystal display deviceInfo
- Publication number
- JPH05333377A JPH05333377A JP14383592A JP14383592A JPH05333377A JP H05333377 A JPH05333377 A JP H05333377A JP 14383592 A JP14383592 A JP 14383592A JP 14383592 A JP14383592 A JP 14383592A JP H05333377 A JPH05333377 A JP H05333377A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- short
- transistor
- circuited
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、液晶表示装置の製造方
法に関し、特にTFT型液晶表示パネルの製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly to a method for manufacturing a TFT type liquid crystal display panel.
【0002】[0002]
【従来の技術】従来の液晶表示装置の製造の際のTFT
パターンは、図4に示すように、表示部Tr(トランジ
スタ)8を信号入力端子部であるG(ゲート)ライン1
0及びD(ドレイン)ライン21を通して、周囲のシャ
ントバスラインであるG(ゲート)シャントバスライン
3及びD1(ドレイン)シャントバスライン2およびD
2(ドレイン)シャントバスライン4のそれぞれに一括
して接続し、これらのシャントバスライン2,3,4と
COMシャントバスライン1,5とをCOMパターン
(GND)6に接続する方法により信号入力端子部をG
NDに落としていた。この方法によって、製造工程中の
静電気対策を行なっていた。2. Description of the Related Art A TFT used in manufacturing a conventional liquid crystal display device.
As shown in FIG. 4, the pattern is such that the display section Tr (transistor) 8 is connected to the G (gate) line 1 which is the signal input terminal section.
Through 0 and D (drain) lines 21, G (gate) shunt bus lines 3 and D1 (drain) shunt bus lines 2 and D which are surrounding shunt bus lines.
2 (drain) shunt bus lines 4 are collectively connected, and the shunt bus lines 2, 3 and 4 and the COM shunt bus lines 1 and 5 are connected to the COM pattern (GND) 6 to input a signal. The terminal part is G
It was dropped to ND. By this method, measures against static electricity were taken during the manufacturing process.
【0003】[0003]
【発明が解決しようとする課題】従来の液晶表示装置の
TFTパターンでは、表示部のTr(トランジスタ)へ
の信号入力端子を一括してシャントバスラインに接続
し、シャントバスラインを通じてGNDに落とす方法に
より、製造プロセス中の静電気対策を行なっていた。こ
のような構造のために、表示部Tr(トランジスタ)へ
の入力ラインからGNDに至るまでの引き回し配線が長
くなり、引き回しの分配線抵抗が上がるため、表示部に
蓄積された静電気が逃げにくくなり、その結果、内部T
r(トランジスタ)の劣化につながるという問題点があ
った。In the conventional TFT pattern of the liquid crystal display device, the signal input terminals to the Tr (transistor) of the display section are collectively connected to the shunt bus line and dropped to GND through the shunt bus line. Has taken measures against static electricity during the manufacturing process. Due to such a structure, the routing wiring from the input line to the display unit Tr (transistor) to the GND becomes long, and the wiring resistance increases due to the routing, so that the static electricity accumulated in the display unit does not easily escape. , As a result, internal T
There is a problem that it leads to deterioration of r (transistor).
【0004】[0004]
【課題を解決するための手段】本発明の液晶表示装置の
TFTパターンは、表示部のTr(トランジスタ)への
信号入力端子ラインのライン1本1本の根本をCOMパ
ターンにショートさせる構造としている。このため、表
示部Tr(トランジスタ)への入力ラインからGNDに
至るまでの引き回し配線を短くすることができ、配線抵
抗を下げることができる。なお、パターンのショート箇
所は、製造プロセスの前半で形成し、製造プロセスの後
半で分離することにより、途中工程のプロセスダメージ
を防止する。The TFT pattern of the liquid crystal display device of the present invention has a structure in which the root of each signal input terminal line to the Tr (transistor) of the display section is short-circuited to the COM pattern. .. Therefore, the lead wiring from the input line to the display unit Tr (transistor) to the GND can be shortened, and the wiring resistance can be reduced. The short-circuited portion of the pattern is formed in the first half of the manufacturing process and separated in the latter half of the manufacturing process to prevent process damage in the middle of the process.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図1は、本発明の第1の実施例のTFTパターンの
等価回路図である。本実施例は、TFTパターンのG
(ゲート)ライン10とSCライン9をライン本数分シ
ョートパターン11によってショートさせた構造にして
いる。The present invention will be described below with reference to the drawings. FIG. 1 is an equivalent circuit diagram of a TFT pattern according to the first embodiment of the present invention. In this embodiment, the TFT pattern G
The (gate) line 10 and the SC line 9 are short-circuited by the number of lines by the short pattern 11.
【0006】図2(a)〜(f)は第1の実施例のG
(ゲート)ライン10をSCライン9にショートさせた
箇所が形成,分離される過程の断面図である。このショ
ート・パターン11(図1)の形成・分離の過程は、図
2(a)に示すように、ガラス基板13の上にショート
・パターン(Cr膜)16,ショート・パターン(IT
O膜)17を形成しておき、その上に形成される絶縁膜
14,15にあらかじめスルーホール22を開けてお
く。次に図2(b)に示すように、Cr膜18(ドレイ
ンパターン形成用)を成膜し、図2(c)のようにホト
リソグラフィ技術でドレインパターンを形成するのと同
時に、Cr膜18とショートパターン(Cr膜)16を
一度にエッチングする。次に図2(d)に示すようにI
TO膜19(ピクセルの透明電極形成用)を成膜し、図
2(e)のようにホトリソグラフィ技術でピクセルの透
明電極パターンを形成するのと同時にITO膜19とシ
ョート・パターン(ITO膜)17を一度にエッチング
する。そして図2(f)に示すように絶縁膜20を成膜
する。FIGS. 2A to 2F show G of the first embodiment.
FIG. 6 is a cross-sectional view of a process in which a portion where the (gate) line 10 is shorted to the SC line 9 is formed and separated. As shown in FIG. 2A, in the process of forming and separating the short pattern 11 (FIG. 1), the short pattern (Cr film) 16 and the short pattern (IT
An O film) 17 is formed in advance, and through holes 22 are formed in advance in the insulating films 14 and 15 formed thereon. Next, as shown in FIG. 2B, a Cr film 18 (for forming a drain pattern) is formed, and a drain pattern is formed by photolithography as shown in FIG. And the short pattern (Cr film) 16 are etched at once. Next, as shown in FIG.
The TO film 19 (for forming the transparent electrode of the pixel) is formed, and the transparent electrode pattern of the pixel is formed by the photolithography technique as shown in FIG. 2 (e). At the same time, the ITO film 19 and the short pattern (ITO film) are formed. Etch 17 at once. Then, as shown in FIG. 2F, the insulating film 20 is formed.
【0007】以上の図2(a)〜(f)のプロセスによ
り、ショート・パターン16,17を形成し、絶縁膜1
4,15が形成される間、静電気等によるTFTパター
ンのプロセスダメージを防止する。By the processes shown in FIGS. 2A to 2F, the short patterns 16 and 17 are formed and the insulating film 1 is formed.
During formation of 4 and 15, process damage of the TFT pattern due to static electricity or the like is prevented.
【0008】図3は、本発明の第2の実施例のTFTパ
ターンの等価回路図である。本実施例は、TFTパター
ンのD(ドレイン)ライン21とCOMパターン12を
D(ドレイン)ラインの本数分ショート・パターン11
にてショートさせた場合である。このショート・パター
ン11は、ドレインパターン及びピクセルの透明電極形
成時に作られ、パネル組立工程の最終段階でレーザーカ
ッタにて分離する。以上の方法により、ドレイン・パタ
ーンが形成されてからパネル組立工程の最終段階でレー
ザーカッタにてショート・パターンが分離されるまでの
間、静電気等によるTFTパターンのプロセスダメージ
を防止する。FIG. 3 is an equivalent circuit diagram of the TFT pattern of the second embodiment of the present invention. In this embodiment, the D (drain) lines 21 of the TFT pattern and the COM patterns 12 are short patterns 11 corresponding to the number of D (drain) lines.
It is when it is short-circuited in. The short pattern 11 is formed at the time of forming the drain pattern and the transparent electrode of the pixel, and is separated by the laser cutter at the final stage of the panel assembly process. By the above method, the process damage of the TFT pattern due to static electricity or the like can be prevented from the formation of the drain pattern to the separation of the short pattern by the laser cutter at the final stage of the panel assembly process.
【0009】[0009]
【発明の効果】以上説明したように本発明は、液晶表示
装置のTFTパターンにおいて、表示部のTr(トラン
ジスタ)に入力する信号端子部を、周辺に配置するシャ
ントバスラインとは独立に、表示部Trに入る直前でC
OMパターンとショートさせておき、製造プロセスの途
中でショート箇所を分離する構造としたので、表示部T
r(トランジスタ)への入力ラインからGNDに至るま
での引き回し配線を短くすることができ、配線抵抗を下
げることができるので、表示部に静電気が蓄積された場
合、静電気を逃がし易くし、途中工程でのTFTパター
ンのプロセスダメージを防止するという効果を有する。As described above, according to the present invention, in the TFT pattern of the liquid crystal display device, the signal terminal portion input to the Tr (transistor) of the display portion is displayed independently of the shunt bus line arranged in the periphery. C just before entering section Tr
Since the short-circuited portion is separated from the OM pattern and the short-circuited portion is separated during the manufacturing process, the display portion T
The routing wiring from the input line to the r (transistor) to the GND can be shortened and the wiring resistance can be reduced. Therefore, when static electricity is accumulated in the display unit, the static electricity can be easily released and the intermediate process This has an effect of preventing process damage of the TFT pattern in the above.
【図1】本発明の第1の実施例のTFTパターンの等価
回路図である。FIG. 1 is an equivalent circuit diagram of a TFT pattern according to a first embodiment of the present invention.
【図2】(a)〜(f)は、第1の実施例のショート・
パターンの形成過程を示す断面図である。2A to 2F are the short circuit of the first embodiment.
It is sectional drawing which shows the formation process of a pattern.
【図3】本発明の第2の実施例のTFTパターンの等価
回路図である。FIG. 3 is an equivalent circuit diagram of a TFT pattern according to a second embodiment of the present invention.
【図4】従来技術のTFTパターンの等価回路図であ
る。FIG. 4 is an equivalent circuit diagram of a conventional TFT pattern.
1,5 COMシャントバスライン 2 D1シャントバスライン 3 Gシャントバスライン 4 D2シャントバスライン 6 COMパターン(GND) 7 トランスファパッド 8 表示部Tr(トランジスタ) 9 SCライン 10 G(ゲート)ライン 11 ショート・パターン 12 COMパターン 13 ガラス基板 14,15,20 絶縁膜 16 ショート・パターン(Cr膜) 17 ショート・パターン(ITO膜) 18 Cr膜 19 ITO膜 21 D(ドレイン)ライン 22 スルーホール 23 保護トランジスタ 1,5 COM Shunt Bus Line 2 D1 Shunt Bus Line 3 G Shunt Bus Line 4 D2 Shunt Bus Line 6 COM Pattern (GND) 7 Transfer Pad 8 Display Tr (Transistor) 9 SC Line 10 G (Gate) Line 11 Short Pattern 12 COM pattern 13 Glass substrate 14, 15, 20 Insulation film 16 Short pattern (Cr film) 17 Short pattern (ITO film) 18 Cr film 19 ITO film 21 D (drain) line 22 Through hole 23 Protection transistor
Claims (1)
法において、表示部のトランジスタに入力する信号端子
部を、周囲に配置するシャントバスラインとは独立に、
表示部トランジスタに入る直前でCOMパターンとショ
ートさせておき、製造プロセスの途中工程で前記ショー
ト箇所を分離することを特徴とする液晶表示装置の製造
方法。1. A method of manufacturing a TFT pattern of a liquid crystal display device, wherein a signal terminal portion input to a transistor of a display portion is provided independently of a shunt bus line arranged around the signal terminal portion.
A method for manufacturing a liquid crystal display device, comprising short-circuiting with a COM pattern immediately before entering a display transistor, and separating the short-circuited part in an intermediate step of the manufacturing process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14383592A JPH05333377A (en) | 1992-06-04 | 1992-06-04 | Manufacture of liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14383592A JPH05333377A (en) | 1992-06-04 | 1992-06-04 | Manufacture of liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05333377A true JPH05333377A (en) | 1993-12-17 |
Family
ID=15348055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14383592A Withdrawn JPH05333377A (en) | 1992-06-04 | 1992-06-04 | Manufacture of liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05333377A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997013177A1 (en) * | 1995-10-03 | 1997-04-10 | Seiko Epson Corporation | Active matrix substrate |
US7129999B2 (en) | 1998-06-29 | 2006-10-31 | Hitachi, Ltd. | Liquid crystal display device |
JP2007041432A (en) * | 2005-08-05 | 2007-02-15 | Seiko Epson Corp | Method for manufacturing electrooptical device |
US7183147B2 (en) | 2004-03-25 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
-
1992
- 1992-06-04 JP JP14383592A patent/JPH05333377A/en not_active Withdrawn
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997013177A1 (en) * | 1995-10-03 | 1997-04-10 | Seiko Epson Corporation | Active matrix substrate |
US5930607A (en) * | 1995-10-03 | 1999-07-27 | Seiko Epson Corporation | Method to prevent static destruction of an active element comprised in a liquid crystal display device |
USRE38292E1 (en) | 1995-10-03 | 2003-10-28 | Seiko Epson Corporation | Method to prevent static destruction of an active element comprised in a liquid crystal display device |
CN100414411C (en) * | 1995-10-03 | 2008-08-27 | 精工爱普生株式会社 | Method of manufacturing active matrix substrate and method for manufacturing film element |
USRE44267E1 (en) | 1995-10-03 | 2013-06-04 | Seiko Epson Corporation | Method to prevent static destruction of an active element comprised in a liquid crystal display device |
US7129999B2 (en) | 1998-06-29 | 2006-10-31 | Hitachi, Ltd. | Liquid crystal display device |
US7183147B2 (en) | 2004-03-25 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
US7829894B2 (en) | 2004-03-25 | 2010-11-09 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
US8198635B2 (en) | 2004-03-25 | 2012-06-12 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
US8674369B2 (en) | 2004-03-25 | 2014-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
JP2007041432A (en) * | 2005-08-05 | 2007-02-15 | Seiko Epson Corp | Method for manufacturing electrooptical device |
JP4497049B2 (en) * | 2005-08-05 | 2010-07-07 | セイコーエプソン株式会社 | Manufacturing method of electro-optical device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |