JPH0955405A - Flexible board and its mounting method - Google Patents

Flexible board and its mounting method

Info

Publication number
JPH0955405A
JPH0955405A JP7204536A JP20453695A JPH0955405A JP H0955405 A JPH0955405 A JP H0955405A JP 7204536 A JP7204536 A JP 7204536A JP 20453695 A JP20453695 A JP 20453695A JP H0955405 A JPH0955405 A JP H0955405A
Authority
JP
Japan
Prior art keywords
semiconductor element
flexible substrate
semiconductor
inner leads
flexible board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7204536A
Other languages
Japanese (ja)
Inventor
Michiyoshi Takano
道義 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7204536A priority Critical patent/JPH0955405A/en
Publication of JPH0955405A publication Critical patent/JPH0955405A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PROBLEM TO BE SOLVED: To bring a flexible board into a minute state, to bring a semiconductor device into a high density state, and to improve the productivity in a mounting technique (TAB) using a flexible board. SOLUTION: The inner leads 4, which are protruding from a semiconductor element 6, are arranged alternately from the side of the active surface of the semiconductor element 6 and the side in end part direction of the semiconductor element 6. By alternately winding the inner lead 4 from the side of the active surface of the semiconductor element and from the side in end part direction of the semiconductor element as above-mentioned, the pitch equal to the irregular electrode 7 provided on the semiconductor element 6 can be obtained even when the inner lead 4, to be provided on a flexible board 1, has the double pitch when compared with the pitch of the irregular electrode 7, which consists of Au and Cu solder, for example, of the semiconductor element, and the flexible board can be brought into a minute state. Accordingly, the short circuit generating, between the inner lead and the end part of the semiconductor element can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、フレキシブル基板を用
いた半導体装置に係わり、特にフレキシブル基板の構
造、及びフレキシブル基板と半導体素子との実装方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a flexible substrate, and more particularly to a structure of the flexible substrate and a mounting method of the flexible substrate and the semiconductor element.

【0002】[0002]

【従来の技術】半導体装置は、一般にリードフレームに
設けたダイパッドに半導体素子を取り付け、半導体チッ
プの外部電極とリードフレームの端子とをそれぞれワイ
ヤで接続し、これをエポキシ樹脂等の熱硬化樹脂でパッ
ケージした後、各端子を切断し製造している。
2. Description of the Related Art In general, a semiconductor device has a semiconductor element attached to a die pad provided on a lead frame, and an external electrode of a semiconductor chip and a terminal of the lead frame are connected by wires, respectively, which are thermoset resin such as epoxy resin. After packaging, each terminal is cut and manufactured.

【0003】しかし最近では電子機器の小型化、薄型化
に伴い、これに使用する半導体装置も高密度実装を行う
為、リードを微細化した、薄くかつ小型の半導体装置の
出現が望まれている。このような要求に答えるべく、フ
レキシブル基板のデバイスホールに半導体装置を配設し
半導体素子の電極とフレキシブル基板に設けたリードの
インナーリードとを直接接続し、これに液状樹脂(例え
ば、エポキシ樹脂)からなる封止剤を印刷あるいはポッ
ティング、トランスファしてパッケージした方式の半導
体装置が使用されるようになった。
However, recently, with the miniaturization and thinning of electronic equipment, the semiconductor devices used therefor are also mounted at high density. Therefore, the appearance of thin and compact semiconductor devices with miniaturized leads is desired. . In order to meet such demands, a semiconductor device is arranged in the device hole of the flexible substrate, the electrode of the semiconductor element and the inner lead of the lead provided on the flexible substrate are directly connected, and a liquid resin (for example, epoxy resin) is connected to this. A semiconductor device of a type in which a sealing agent composed of is packaged by printing, potting, or transferring has come to be used.

【0004】図3は、フレキシブル基板を用いた従来の
半導体装置を説明する為の平面図、図4は図3のA−A
@ 線断面図、図5は同半導体装置の製造例を示す断面図
である。図3において、1は長さ方向に等間隔に、後述
半導体素子6の表面積より大きい面積のデバイスホール
2が設けられた厚さ25〜150μm程度のフレキシブ
ル基板である。3はフレキシブル基板1に設けられた銅
等の導電率の高い厚さ18〜35μm、幅15〜100
μm程度の金属箔からなる多数のリードで、その一部は
デバイスホール2内に突出して自由端となっており、イ
ンナーリード4を形成している。5はフレキシブル基板
1を搬送する為のスプロケット穴である。6は半導体素
子、7は半導体素子6に設けられた金の凸状電極であ
る。図5は、上記のようなフレキシブル基板1に半導体
素子を取り付ける装置の一例を示す断面図で、半導体素
子台8上に搭載された半導体素子6は、所定の位置に位
置決めされる。フレキシブル基板1は、デバイスホール
2が半導体素子6上に達した位置で停止し、半導体素子
6に設けた多数の凸状電極7と、各リード3のインナー
リード4の先端とをそれぞれ整合(アライメント)させ
る。ついで400度〜600度程度に加熱されたボンデ
ィングツール11を下降させ各リード3を、所定の角度
にフォーミングして各インナーリード4の先端をそれぞ
れ半導体素子6の各凸状電極7に加熱、加圧させ、接続
する。次に、フレキシブル基板1を移動し、リールへ巻
取った後、スキージ印刷、ポッティング、トランスファ
等により半導体素子6及びインナーリード4、リード3
の一部を液状の封止用樹脂で封止した後リード3を切断
して、半導体装置を製造する。
FIG. 3 is a plan view for explaining a conventional semiconductor device using a flexible substrate, and FIG. 4 is an AA of FIG.
FIG. 5 is a cross-sectional view taken along line @, and FIG. 5 is a cross-sectional view showing a manufacturing example of the same semiconductor device. In FIG. 3, reference numeral 1 denotes a flexible substrate having a thickness of 25 to 150 μm, in which device holes 2 having an area larger than the surface area of the semiconductor element 6 described later are provided at equal intervals in the length direction. 3 has a thickness of 18 to 35 μm and a width of 15 to 100 with high conductivity such as copper provided on the flexible substrate 1.
A large number of leads made of metal foil of about μm, some of which protrude into the device hole 2 to form free ends, forming the inner leads 4. Reference numeral 5 is a sprocket hole for carrying the flexible substrate 1. Reference numeral 6 is a semiconductor element, and 7 is a gold convex electrode provided on the semiconductor element 6. FIG. 5 is a cross-sectional view showing an example of an apparatus for mounting a semiconductor element on the flexible substrate 1 as described above, and the semiconductor element 6 mounted on the semiconductor element base 8 is positioned at a predetermined position. The flexible substrate 1 stops at the position where the device hole 2 reaches the semiconductor element 6, and aligns (aligns) the many convex electrodes 7 provided on the semiconductor element 6 with the tips of the inner leads 4 of each lead 3. ) Let me. Then, the bonding tool 11 heated to about 400 to 600 degrees is lowered to form each lead 3 at a predetermined angle and the tip of each inner lead 4 is heated and applied to each convex electrode 7 of the semiconductor element 6. Press and connect. Next, after the flexible substrate 1 is moved and wound on a reel, the semiconductor element 6, the inner leads 4, and the leads 3 are squeegee-printed, potted, transferred, or the like.
After a part of is sealed with a liquid sealing resin, the leads 3 are cut to manufacture a semiconductor device.

【0005】[0005]

【発明が解決しようとする課題】近年では半導体装置の
更なる軽薄短小化が要求されており、フレキシブル基板
を用いた実装技術(TAB)において、これを実現する
には半導体素子自体の縮小化、細密化とフレキシブル基
板の細密化が必要不可欠である。しかし、乾式エッチン
グ(ドライエッチング)を用いている半導体素子は縮小
化、細密化が急速に進んでいるが、フレキシブル基板は
湿式エッチング(ウエットエッチング)を用いているこ
とと、フレキシブル基板のインナーリードは、デバイス
ホールより自由端となる事から製造が難しく、半導体素
子と比較し細密化が困難である。
In recent years, further miniaturization of semiconductor devices has been required, and in the mounting technology (TAB) using a flexible substrate, in order to achieve this, the semiconductor element itself must be miniaturized. Miniaturization and miniaturization of flexible substrates are essential. However, semiconductor elements that use dry etching (dry etching) are rapidly shrinking and becoming finer. However, the flexible substrate uses wet etching (wet etching), and the inner leads of the flexible substrate are Since it is a free end rather than a device hole, it is difficult to manufacture, and it is difficult to make it smaller than a semiconductor element.

【0006】本発明はこのような問題点を解決するもの
で、その目的とするところは、フレキシブル基板の細密
化、半導体装置の高密度化を提供するところにある。
The present invention solves such a problem, and an object thereof is to provide a flexible substrate with a finer density and a semiconductor device with a higher density.

【0007】[0007]

【課題を解決するための手段】本発明のフレキシブル基
板は、インナーリードが、半導体素子の能動面側からと
半導体素子の端部から交互に配列される事を特徴とす
る。
The flexible substrate of the present invention is characterized in that inner leads are alternately arranged from the active surface side of the semiconductor element and from the end of the semiconductor element.

【0008】[0008]

【作用】本発明の上記の構成によれば、フレキシブル基
板のインナーリードは、半導体素子の能動面側からと半
導体装置の端部から交互に配列させるため、半導体素子
の倍のピッチでフレキシブル基板を形成しても半導体素
子のピッチと同等であり、フレキシブル基板の細密化を
可能とする作用がある。
According to the above configuration of the present invention, since the inner leads of the flexible substrate are alternately arranged from the active surface side of the semiconductor element and from the end of the semiconductor device, the flexible substrate is arranged at a pitch twice that of the semiconductor element. Even if it is formed, it has the same pitch as that of the semiconductor element, and has an effect of enabling the flexible substrate to be made fine.

【0009】[0009]

【実施例】以下、実施例により本発明の詳細を示す。The present invention will be described in detail below with reference to examples.

【0010】図1は、本発明の一実施例を示すフレキシ
ブル基板の平面図である。図1において1は例えばポリ
イミドからなるフレキシブル基板、2はフレキシブル基
板に設けられたデバイスホール、3はフレキシブル基板
に設けられたCuなどの導電性の良好な金属に、錫また
はNi/Au等をメッキしたリード、4は、幅15〜1
00μmのデバイスホール2より自由端となり突出した
インナーリード、6は半導体素子である。この時、半導
体素子6より突出するインナーリード4は半導体素子6
の能動面側からと半導体素子6の端部方向側(半導体素
子エッジ側)から交互に配列される。このようにインナ
ーリード4を半導体素子の能動面側からと、半導体素子
の端部方向から交互に引き回すことにより、半導体素子
の例えばAu、Cu、はんだからなる凸状電極7のピッ
チと比較し、フレキシブル基板1に設けられるインナー
リード4は倍のピッチであっても半導体素子6に設けら
れている凸状電極7と同等のピッチを得られることにな
り、容易に細密化を実現することができる。この時、イ
ンナーリード4の全てが半導体素子6の能動面側からと
半導体素子6の端部方向から突出する必要は無く、細密
化を必要とするピッチ部分、または、フレキシブル基板
の配線引き回しの制約上、必要とする部分のみ実施して
もよい。また、この時、デバイスホール2の大きさを半
導体素子6の形状よりも小さくすれば、半導体素子6の
端部(エッジ)とインナーリード4の接触を防ぐことが
可能である。
FIG. 1 is a plan view of a flexible substrate showing an embodiment of the present invention. In FIG. 1, 1 is a flexible substrate made of, for example, polyimide, 2 is a device hole provided in the flexible substrate, and 3 is a highly conductive metal such as Cu provided in the flexible substrate, plated with tin or Ni / Au. Leads, 4 have a width of 15 to 1
Inner leads 6 which are free ends and protrude from the device hole 2 of 00 μm, and 6 are semiconductor elements. At this time, the inner leads 4 protruding from the semiconductor element 6 are
Are alternately arranged from the active surface side of the semiconductor element 6 and from the end direction side of the semiconductor element 6 (semiconductor element edge side). In this way, the inner leads 4 are alternately routed from the active surface side of the semiconductor element and from the end direction of the semiconductor element to compare with the pitch of the convex electrodes 7 made of, for example, Au, Cu, or solder of the semiconductor element, Even if the inner leads 4 provided on the flexible substrate 1 have a double pitch, the same pitch as that of the convex electrodes 7 provided on the semiconductor element 6 can be obtained, and the miniaturization can be easily realized. . At this time, it is not necessary for all of the inner leads 4 to project from the active surface side of the semiconductor element 6 and from the end portion direction of the semiconductor element 6, and the pitch portion that requires miniaturization or the wiring lead restrictions of the flexible substrate. Moreover, you may implement only a required part. At this time, if the size of the device hole 2 is made smaller than the shape of the semiconductor element 6, it is possible to prevent contact between the end portion (edge) of the semiconductor element 6 and the inner lead 4.

【0011】図2は本発明の一実施例を示すフレキシブ
ル基板と半導体素子を実装する際のフレキシブル基板、
半導体素子、ボンディングツールの断面図である。本発
明のフレキシブル基板を半導体素子と実装する際、通常
シングルポイントTAB方式と呼ばれる、アライメント
されたインナーリード4と凸状電極7を一箇所ずつ接合
(ボンディング)する実装手段が挙げられる。しかしシ
ングルポイントTABは接合する箇所に比例し時間を要
するため、例えば半導体素子6に200箇所の凸状電極
7と200本のインナーリード4が形成されている場
合、一箇所0.1秒の接合時間が必要として、半導体素
子一つを実装するために0.1秒×200=20秒もの
時間を必要とし生産性が悪い。本発明はこのような問題
を解決するため、一括接合(ギャングボンディング)に
よって接合を行う。インナーリード4に例えばSnメッ
キ層を設け、半導体素子6に設けた多数の例えばAuメ
ッキで形成されている凸状電極7と、各リード3のイン
ナリード4の先端とをそれぞれ整合させ、ついで、加熱
されたボンディングツール11を下降させて各リード3
を加熱、加圧し、各インナリード4の先端をそれぞれ半
導体素子6の各凸状電極7に加圧、加圧させて接続した
場合に、超硬、焼結ダイヤ、ボロンナイトライド、気相
成長ダイヤ等の硬い材質からからなるボンディングツー
ル11はフレキシブル基板1に設けられたデバイスホー
ル2よりも狭く(小さく)形成する。例えばデバイスホ
ールXの幅が300μm、凸状電極7の幅が100μm
とすると、ボンディングツールYの幅はデバイスホール
幅Xよりも小さく、凸状電極7の幅と同等または大きく
する。よって前述条件の場合なら100〜150μm程
度の幅が適当である。この時の接合条件は、、凸状電極
7の硬度、インナーリード4の数、インナーリード4の
材質、インナーリード4にメッキされている材質等によ
り決定する必要があるが、おおよその目安としてボンデ
ィングツール温度:400〜600℃、荷重:20〜1
00g/リード、ボンディングタイム:0.5〜3.0
秒、必要があれば半導体素子台温度8(下部加熱):5
0〜300℃程度の条件を用いる。この時、ボンディン
グタイムは、一括接合のため、インナーリード4の数、
凸状電極7の数に関係なく一括接合することが可能であ
り生産性が高い。
FIG. 2 shows a flexible substrate according to an embodiment of the present invention and a flexible substrate for mounting a semiconductor element,
It is sectional drawing of a semiconductor element and a bonding tool. When mounting the flexible substrate of the present invention on a semiconductor element, a mounting means for bonding the aligned inner leads 4 and the convex electrodes 7 one by one, which is usually called a single point TAB method, can be mentioned. However, since the single point TAB requires time in proportion to the joining points, for example, if the semiconductor element 6 has 200 convex electrodes 7 and 200 inner leads 4 formed, the joining at one point for 0.1 seconds It takes time, and it takes 0.1 seconds × 200 = 20 seconds to mount one semiconductor element, resulting in poor productivity. In order to solve such a problem, the present invention joins by collective joining (gang bonding). For example, a Sn plating layer is provided on the inner lead 4, a large number of convex electrodes 7 formed on the semiconductor element 6 by, for example, Au plating are aligned with the tips of the inner leads 4 of the respective leads 3, and then, Lower the heated bonding tool 11 to move each lead 3
When heated and pressed to press and connect the tip of each inner lead 4 to each convex electrode 7 of the semiconductor element 6 by pressing and pressurizing, the cemented carbide, sintered diamond, boron nitride, vapor phase growth The bonding tool 11 made of a hard material such as diamond is formed narrower (smaller) than the device hole 2 provided in the flexible substrate 1. For example, the width of the device hole X is 300 μm, and the width of the convex electrode 7 is 100 μm.
Then, the width of the bonding tool Y is smaller than the device hole width X and is equal to or larger than the width of the convex electrode 7. Therefore, in the case of the above conditions, a width of about 100 to 150 μm is suitable. The bonding conditions at this time must be determined by the hardness of the convex electrodes 7, the number of inner leads 4, the material of the inner leads 4, the material plated on the inner leads 4, etc. Tool temperature: 400-600 ° C, load: 20-1
00g / lead, bonding time: 0.5-3.0
Second, if necessary, semiconductor element table temperature 8 (lower heating): 5
Conditions of about 0 to 300 ° C. are used. At this time, the bonding time is the number of inner leads 4 because the bonding is performed collectively.
Regardless of the number of the convex electrodes 7, it is possible to carry out collective bonding and the productivity is high.

【0012】[0012]

【発明の効果】本発明は以上説明したように、フレキシ
ブル基板に設けられるインナーリードを半導体素子能動
面からと半導体素子端部から交互に引き回す事によりフ
レキシブル基板の細密化を図り、かつデバイスホールを
半導体素子の外形より小さくすることにより、インナー
リードと半導体素子とのエッジタッチ(エッジショー
ト)を防止する効果を有する。また、フレキシブル基板
と半導体素子を実装する際、凹状の幅狭ボンディングツ
ールを用いることにより一括接合を可能とし、製造の効
率化(サイクルタイムアップ)を図る効果も有する。
As described above, according to the present invention, by arranging the inner leads provided on the flexible substrate alternately from the semiconductor element active surface and from the semiconductor element end portion, the flexible substrate is made finer and the device hole is formed. By making it smaller than the outer shape of the semiconductor element, it has an effect of preventing edge touch (edge short circuit) between the inner lead and the semiconductor element. Further, when the flexible substrate and the semiconductor element are mounted, a concave narrow bonding tool is used to enable collective bonding, which also has the effect of improving manufacturing efficiency (cycle time).

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すフレキシブル基板平面
図。
FIG. 1 is a plan view of a flexible substrate showing an embodiment of the present invention.

【図2】本発明の一実施例を示すフレキシブル基板、半
導体素子、ボンディングツールの実装断面図。
FIG. 2 is a mounting cross-sectional view of a flexible substrate, a semiconductor element, and a bonding tool showing an embodiment of the present invention.

【図3】従来技術を示すフレキシブル基板と半導体素子
との実装構造の平面図。
FIG. 3 is a plan view of a mounting structure of a flexible substrate and a semiconductor element showing a conventional technique.

【図4】図4のA−A線断面図。4 is a cross-sectional view taken along the line AA of FIG.

【図5】従来技術を示す半導体装置を説明するための断
面図。
FIG. 5 is a sectional view for explaining a semiconductor device showing a conventional technique.

【符号の説明】[Explanation of symbols]

1 フレキシブル基板 2 デバイスホール 3 リード 4 インナーリード 5 スプロケットホール 6 半導体素子 7 凸状電極 8 半導体素子台 9 位置決めガイド 10 テープレール 11 ボンディングツール 1 flexible substrate 2 device hole 3 lead 4 inner lead 5 sprocket hole 6 semiconductor element 7 convex electrode 8 semiconductor element stand 9 positioning guide 10 tape rail 11 bonding tool

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】フレキシブル基板に半導体素子を配設し、
前記半導体素子に設けられた多数の電極に、前記フレキ
シブル基板に設けられたインナーリードの先端を接続
し、しかる後に前記半導体素子及びリードの一部を樹脂
等で封止した半導体装置において、前記フレキシブル基
板に設けられる前記インナーリードは、半導体素子の能
動面側からと半導体素子の端部から交互に配列される事
を特徴とするフレキシブル基板。
1. A semiconductor device is arranged on a flexible substrate,
In the semiconductor device in which the tips of the inner leads provided on the flexible substrate are connected to a large number of electrodes provided on the semiconductor element, and then the semiconductor element and a part of the leads are sealed with a resin or the like, The flexible substrate, wherein the inner leads provided on the substrate are alternately arranged from an active surface side of the semiconductor element and from an end portion of the semiconductor element.
【請求項2】フレキシブル基板に半導体素子を配設し、
半導体素子に設けた多数の電極に、前記フレキシブル基
板に設けられたインナーリードの先端を加熱、加圧等に
よりそれぞれ接続し、しかる後に前記半導体素子及びリ
ードの一部を樹脂等で封止した半導体装置において、前
記フレキシブル基板に設けられるインナーリードは、半
導体素子の能動面側からと半導体素子の端部から交互に
配列され、かつフレキシブル基板に設けられる孔(デバ
イスホール)を半導体素子の形状よりも小さくする事を
特徴としたフレキシブル基板。
2. A semiconductor element is arranged on a flexible substrate,
A semiconductor in which the tips of the inner leads provided on the flexible substrate are connected to a large number of electrodes provided on the semiconductor element by heating, pressurizing, etc., and then the semiconductor element and some of the leads are sealed with resin or the like. In the apparatus, the inner leads provided on the flexible substrate are arranged alternately from the active surface side of the semiconductor element and from the end of the semiconductor element, and the holes (device holes) provided in the flexible substrate are formed more than the shape of the semiconductor element. Flexible board characterized by being small.
【請求項3】フレキシブル基板に半導体素子を配設し、
半導体素子に設けた多数の電極に、前記フレキシブル基
板に設けられたインナーリードの先端を接続し、しかる
後に前記半導体素子及びリードの一部を樹脂等で封止し
た半導体装置において、請求項1、または請求項2記載
のフレキシブル基板を接合する際、一括接合(ギャング
ボンディング)する事を特徴とするフレキシブル基板の
実装方法。
3. A semiconductor element is arranged on a flexible substrate,
A semiconductor device in which the tips of inner leads provided on the flexible substrate are connected to a large number of electrodes provided on a semiconductor element, and then the semiconductor element and a part of the leads are sealed with a resin or the like. Alternatively, a flexible board mounting method is characterized in that when the flexible boards according to claim 2 are bonded, they are collectively bonded (gang bonding).
JP7204536A 1995-08-10 1995-08-10 Flexible board and its mounting method Pending JPH0955405A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7204536A JPH0955405A (en) 1995-08-10 1995-08-10 Flexible board and its mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7204536A JPH0955405A (en) 1995-08-10 1995-08-10 Flexible board and its mounting method

Publications (1)

Publication Number Publication Date
JPH0955405A true JPH0955405A (en) 1997-02-25

Family

ID=16492166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7204536A Pending JPH0955405A (en) 1995-08-10 1995-08-10 Flexible board and its mounting method

Country Status (1)

Country Link
JP (1) JPH0955405A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008210962A (en) * 2007-02-26 2008-09-11 Fujitsu Ltd Flexible substrate, optical component, optical transmitter, and optical receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008210962A (en) * 2007-02-26 2008-09-11 Fujitsu Ltd Flexible substrate, optical component, optical transmitter, and optical receiver
US8283565B2 (en) 2007-02-26 2012-10-09 Fujitsu Limited Flexible substrate

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