JPH0945914A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the current gain of a field effect transistor by suppressing the fluctuation of a threshold voltage (Vth) with time caused by the hot carrier of the field-effect transistor mounted to a semiconductor integrated circuit device and at the same time suppressing the fluctuation of the threshold voltage (Vth) with time caused by, for example, hydrogen ions and hydroxyl ions. SOLUTION: In a semiconductor integrated circuit device with a field-effect transistor where a gate electrode 5 is formed on the surface of a semiconductor substrate 1 via a gate insulation film 3, nitride insulation film 4 is provided between the semiconductor substrate 1 and the gate insulation film 3 and at the same time a nitride insulation film 7 is provided on the side wall surface of the gate insulation film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on the surface of a semiconductor substrate with a gate insulating film interposed. And effective technology.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit device for mounting a field effect transistor having a gate electrode formed on the surface of a semiconductor substrate with a gate insulating film interposed, a semiconductor integrated circuit device, for example, MOSFE.
T (M etal O xide S emicoductor F ield E ffect T r
The development of semiconductor integrated circuit devices for mounting an anistor) is underway.

The above-mentioned MOSFET tends to be miniaturized for the purpose of increasing the degree of integration of a semiconductor integrated circuit device. This M
With the miniaturization of OSFETs, particularly in a MOSFET whose gate length dimension reaches submicron, a part of the region on the channel formation region side of the drain region is disclosed in Japanese Patent Publication No. 62-31506. other regions LDD which is set to a low impurity concentration than the impurity concentration of the adoption of the (L ightly D oped D rain) structure is essential. Since the MOSFET adopting the LDD structure can reduce the diffusion amount of the drain region toward the channel formation region side and secure the channel length dimension, it is possible to suppress the occurrence of the short channel effect. Further, in the MOSFET adopting the LDD structure, the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region can be relaxed and the electric field strength generated in this region can be weakened. The amount of hot carriers generated can be reduced. To reduce the amount of hot carriers generated, use MO
It is possible to suppress the change in the threshold voltage (Vth) of the SFET with time.

[0004]

MO of the LDD structure.
The SFET (Field Effect Transistor) reduces the generation amount of hot carriers (electrons, holes) that are injected and captured in the gate insulating film, and suppresses the change in threshold voltage over time.
However, the change in the threshold voltage of the MOSFET with time depends on the case where high-energy electrons and holes generated by impact ionization are injected and captured in the gate insulating film, and in the final protective film and the interlayer insulating film. The contained hydrogen ions (-H +) and hydroxide ions (-OH) may enter the gate insulating film and be captured. Hydrogen ions, hydroxide ions, and the like may enter the film from the side wall surface of the gate insulating film or may penetrate the gate electrode and enter the gate insulating film. In particular, hydrogen ions, hydroxide ions, etc. have a high rate of penetrating from the side wall surface of the gate insulating film. That is, LD
The MOSFET having the D structure can suppress the temporal change in the threshold voltage due to hot carriers, but cannot suppress the temporal change in the threshold voltage due to hydrogen ions, hydroxide ions and the like. In recent years, the manufacturing process of semiconductor integrated circuit devices has been lowered in temperature, and since the interlayer insulating film formed at a low temperature contains a large amount of hydrogen ions, hydroxide ions, etc., hydrogen ions, hydroxide ions, etc. Due to M
It is important to suppress the variation of the threshold voltage of the OSFET with time.

Further, the LDD structure MOSFET is
Although the change of the threshold voltage with time can be suppressed, since the impurity concentration of a part of the drain region on the channel formation region side is set to be lower than the impurity concentration of the other region, the source region-drain region The amount of current flowing in between decreases, and the current gain of the MOSFET decreases. This MOSF
The decrease in the current gain of ET means the decrease in the operating speed of the semiconductor integrated circuit device in which the MOSFET is mounted.

It is an object of the present invention to provide a semiconductor integrated circuit device having a field effect transistor in which a gate electrode is formed on the surface of a semiconductor substrate with a gate insulating film interposed therebetween, and the time lapse caused by the hot carriers of the field effect transistor. Of the threshold voltage (Vth) over time, and the threshold voltage over time due to hydrogen ions, hydroxide ions, etc.
It is to provide a technique capable of suppressing the fluctuation of (Vth).

Another object of the present invention is to provide a technique capable of achieving the above object and increasing the current gain of the field effect transistor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a semiconductor integrated circuit device having a field effect transistor in which a gate electrode is formed on the surface of a semiconductor substrate with a gate insulating film interposed, a nitride insulating film is provided between the semiconductor substrate and the gate insulating film. A film is provided and a nitride insulating film is provided on the side wall surface of the gate insulating film. The nitride insulating film provided between the semiconductor substrate and the gate insulating film is a silicon oxynitride film formed by oxynitriding treatment, and the nitride insulating film provided on the side wall surface of the gate insulating film is an oxide film. A silicon oxynitride film formed by nitriding treatment or a silicon nitride film formed by a vapor phase chemical growth method.

(2) A nitride insulating film is provided on the upper surface of the gate electrode and the side wall surface thereof. The nitride insulating film provided on the upper surface and the side wall surface of the gate electrode is a silicon oxynitride film formed by an oxynitriding treatment or a silicon nitride film formed by a vapor phase chemical growth method.

[0012]

According to the above means (1), the number of dangling bonds (unpaired electrons) existing on the surface of the semiconductor substrate immediately below the gate insulating film can be reduced by the nitride insulating film. The amount of hot carriers trapped in the gate insulating film can be reduced. In addition, since the nitride insulating film is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions and hydroxide ions contained in the interlayer insulating film are gate-insulated. It is possible to prevent the side wall surface of the film from penetrating into the film. As a result, it is possible to suppress variations in the threshold voltage (Vth) with time due to hot carriers of the field effect transistor, and to reduce the threshold voltage (Vth) with time due to hydrogen ions, hydroxide ions and the like. Fluctuations can be suppressed.

Further, the electric field effect caused by hot carriers is mitigated without reducing the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region and weakening the electric field strength generated in this region. Since the change in the threshold voltage (Vth) of the transistor over time can be suppressed, it is not necessary to set the impurity concentration of a part of the drain region on the channel formation region side to be lower than the impurity concentrations of the other regions. Good. As a result, the amount of current flowing between the source region and the drain region can be increased, so that the current gain of the field effect transistor can be increased.

According to the above-mentioned means (2), the nitride insulating film is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), so that it is included in the interlayer insulating film. It is possible to prevent hydrogen ions, hydroxide ions, and the like that are generated from penetrating into the gate insulating film through the upper surface and the side wall surface of the gate electrode through the film. As a result, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions or the like of the field effect transistor.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a field effect transistor.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) A schematic configuration of a semiconductor integrated circuit device having a MOSFET which is Embodiment 1 of the present invention is shown in FIG.

As shown in FIG. 1, a MOSFET (field effect transistor) Q mounted on a semiconductor integrated circuit device.
Is formed on the surface of the element formation region (active region) of the p-type semiconductor substrate 1 made of, for example, single crystal silicon. The element formation region is defined around the element isolation insulating film 2 formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1, and is insulated and isolated from other element formation regions.

The MOSFET Q is mainly composed of a p-type semiconductor substrate 1 which is a channel forming region, a gate insulating film 3, a gate electrode 5, and a pair of n regions which are a source region and a drain region.
It is composed of the type semiconductor region 8. The gate insulating film 3 is formed on the surface of the p-type semiconductor substrate 1, and is formed of, for example, a thermal silicon oxide film. The gate electrode 5 is formed on the surface of the gate insulating film 3, and is formed of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced. That is, MOSFETQ
Is a field effect transistor in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed.

Each of the pair of n-type semiconductor regions 8 serving as the source region and the drain region is formed on the surface of the p-type semiconductor substrate 1 and is formed in self alignment with the gate electrode 5. A silicide layer 10 is formed on the surface of each of the pair of n-type semiconductor regions 8. That is, M of this embodiment
The source region and the drain region of the OSFET Q are the n-type semiconductor region 8 and the silicide layer 1 formed on the surface portion thereof.
0. Thus, by forming the source region and the drain region with the n-type semiconductor region 8 and the silicide layer 10, the sheet resistance of the n-type semiconductor region 8 is about several tens (between 50 and 100) Ω / □, Since the sheet resistance of the silicide layer 10 is about several Ω / □, the resistance value of each of the source region and the drain region can be reduced, and the amount of current flowing between the source region and the drain region can be increased. The current gain of the MOSFETQ can be increased.

A silicide layer 10 is formed on the upper surface of the gate electrode 5. By thus forming the silicide layer 10 on the upper surface of the gate electrode 5, the sheet resistance of the gate electrode 5 made of a polycrystalline silicon film into which impurities are introduced is several tens (between 50 and 100) Ω / □. Since the sheet resistance of the silicide layer 10 is about several Ω / □, the resistance value of the gate electrode 5 can be reduced, and the MOSFE
The operating speed of T can be increased.

The silicide layers 10 formed on the respective surface portions of the pair of n-type semiconductor regions 8 are self-aligned with the side wall spacers 9 formed on the side wall surfaces of the gate electrode 5 in the gate length direction. It is formed. The silicide layer 10 formed on the upper surface of the gate electrode 5 is self-aligned with the sidewall spacer 9 formed on the side wall surface of the gate electrode 5 in the gate length direction.
That is, the silicide layer 10 formed on the surface of the n-type semiconductor region 8 and the upper surface of the gate electrode 5 is salicided.
cide: is formed by S alf Ali gned Sili cide) technology.

Of the pair of n-type semiconductor regions 8 which are the source region and the drain region, one n-type semiconductor region 8
The wiring 12 is electrically connected to the silicide layer 10 formed on the surface of the n-type semiconductor region 8 through the connection hole 11A formed in the interlayer insulating film 11. A wiring 12 is electrically connected to the wiring 10 through a connection hole 11B formed in the interlayer insulating film 11. The interlayer insulating film 11 is formed for the purpose of insulating and separating the gate electrode 5 and the wiring 12, for example, a chemical vapor deposition method.
It is formed by: (CVD C hemical V apor D eposition) silicon oxide film formed by. Since the interlayer insulating film 11 is formed at a low temperature based on the process of lowering the temperature of the semiconductor integrated circuit device, the interlayer insulating film 11 contains a large amount of hydrogen ions, hydroxide ions and the like. The wiring 12 is formed of, for example, an aluminum film or an aluminum alloy film.

An interlayer insulating film 13 is formed on the wiring 12. The interlayer insulating film 13 is formed for the purpose of insulating and separating the wiring 12 and an upper wiring (not shown), and is formed of, for example, a silicon oxide film formed by a chemical vapor deposition method.
Since the interlayer insulating film 13 is formed at a low temperature based on the temperature lowering process of the semiconductor integrated circuit device like the above-described interlayer insulating film 12, the interlayer insulating film 13 has a large amount of hydrogen ions and hydroxide ions. Etc. are included.

A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. Since the nitride insulating film 4 can reduce the number of dangling bonds (unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 directly below the gate insulating film 3, the nitride insulating film 4 does not exist in the gate insulating film 4. The amount of hot carriers captured can be reduced.

The nitride insulating film 4 is formed of a silicon oxynitride film formed by an oxynitriding process. This silicon oxynitride film is a silicon nitride film (Si ₃ N ₄ , Six) formed by a vapor phase chemical growth method.
Compared with Nx), the film quality is better and the adhesion is higher.

A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 3 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 3. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions and water contained in the interlayer insulating film 11 and the interlayer insulating film 13 are not formed. It is possible to prevent acid ions and the like from entering the film through the side wall surface of the gate insulating film 3.

A nitride insulating film 7 is provided between the side wall surface of the gate electrode 5 and the side wall spacer 9, that is, on the side wall surface of the gate electrode 5. Since this nitride insulating film 7 is impermeable to hydrogen ions, hydroxide ions, etc., the hydrogen ions, hydroxide ions, etc. contained in the interlayer insulating film 11 and the interlayer insulating film 13 will be on the gate electrode 5 side. It is possible to prevent the light from penetrating through the film from the wall surface and entering the gate insulating film 3.

The nitride insulating film 7 is formed of a silicon oxynitride film formed by oxynitriding or a silicon nitride film formed by a vapor phase chemical growth method. In this embodiment, the silicon nitride film 7 is formed of a silicon nitride film formed by a vapor phase chemical growth method.

The MOSFET Q having the above structure is
For example, it is used as a constituent element of a CMOS inverter circuit.

Next, a method of manufacturing the MOSFET Q mounted on the semiconductor integrated circuit device will be described with reference to FIGS.
(Partial cross-sectional views showing each manufacturing process) will be described.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, using the well-known selective oxidation method, the p
An element isolation insulating film 2 made of a silicon oxide film is formed on the surface of the element isolation region (inactive region) of the type semiconductor substrate 1.

Next, a thermal oxidation process is performed to form a gate insulating film 3A made of a thermally oxidized silicon film on the surface of the element forming region (active region) of the p-type semiconductor substrate 1.

Next, an oxynitriding process is performed to form a nitride insulating film 4A made of a silicon oxynitride film between the p-type semiconductor substrate 1 and the gate insulating film 3A as shown in FIG. This oxynitride insulating film 4A is, for example, about 100% in a diluted nitrogen gas atmosphere or a 100% nitrogen gas atmosphere.
It is formed by performing heat treatment at 0 [° C.] for about 30 minutes.

Then, a polycrystalline silicon film is formed on the entire surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3A by, for example, a chemical vapor deposition method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

Next, the polycrystalline silicon film and the gate insulating film 3 are formed.
A and the nitride insulating film 4A are sequentially patterned to form a gate insulating film 3 on the surface of the element formation region of the p-type semiconductor substrate 1 and a gate electrode on the surface of the gate insulating film 3 as shown in FIG. 5, the nitride insulating film 4 is formed between the p-type semiconductor substrate 1 and the gate insulating film 3. In this step, the surface of the other element formation region except the surface of the element formation region of the p-type semiconductor substrate 1 under the gate electrode 5 is exposed.

Next, a nitride insulating film 7 is formed on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the gate electrode 5 and the side wall surface thereof. The nitride insulating film 7 is formed of, for example, a silicon nitride film (Si ₃ N ₄ , Six Nx) formed by a vapor phase chemical growth method.

Next, an n-type impurity is introduced into the surface of the element formation region of the p-type semiconductor substrate 1 by self-alignment with the gate electrode 5 and the element isolation insulating film 2 by, for example, an ion implantation method. As shown in FIG. 4, a pair of n-type semiconductor regions 8 which are a source region and a drain region are formed. In this step, since the n-type impurity is introduced through the nitride insulating film 7, it is possible to suppress physical damage on the surface of the element formation region of the p-type semiconductor substrate 1 due to the impurity introduction.

Next, as shown in FIG. 5, a sidewall spacer 9 is formed on the sidewall surface of the gate electrode 5 in the gate length direction. The sidewall spacer 9 is formed by forming a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the gate electrode 5 by, for example, a chemical vapor deposition method, and then forming the film thickness of the silicon oxide film and the nitride insulating film 7. amount corresponding to the thickness, RIE (R eactive I on this silicon oxide film and a nitride insulating film 7
It is formed by performing anisotropic etching of E tching) or the like. In this step, the upper surface of the gate electrode 5 is exposed. Further, the surface of the element formation region of the p-type semiconductor substrate 1 around the sidewall spacer 9 is exposed.

Next, p including the upper surface of the gate electrode 5
A refractory metal film 10A made of a Ti film, a W film, a Mo film, or the like is formed on the entire surface of the mold semiconductor substrate 1 by a sputtering method. In this embodiment, a Ti film is used as the refractory metal film 10A.

Next, a low temperature heat treatment of about 500 to 600 [° C.] is performed to react Si of each of the gate electrode 5 and the n-type semiconductor region 8 with Ti of the refractory metal film 10A, as shown in FIG. On the upper surface of the gate electrode 5 and the n-type semiconductor region 8
A silicide layer (TiSix layer) 10 is formed on the surface of the.

Next, the unreacted refractory metal film 10A that has not reacted with Si is selectively removed by, for example, a wet etching method.

Next, a high temperature heat treatment of about 900 to 1000 [° C.] is performed to promote the reaction of the silicide layer 10 and reduce the resistance of the silicide layer 10. By this process, M
OSFETQ is almost completed.

Next, the interlayer insulating film 11 is formed on the entire surface of the p-type semiconductor substrate 1, the wiring 12 is formed on the interlayer insulating film 11, and the interlayer insulating film 13 is formed on the wiring 12. The semiconductor integrated circuit device shown in is formed.

As described above, according to this embodiment, the following operational effects can be obtained.

(1) MOSF in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed.
In a semiconductor integrated circuit device having an ET (Field Effect Transistor) Q, a nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3 and nitride is formed on the side wall surface of the gate insulating film 3. An insulating film 7 is provided.

With this structure, p just below the gate insulating film 3 is formed.
Since the number of dangling bonds (unpaired electrons) existing on the surface of the type semiconductor substrate 1 can be reduced by the nitride insulating film 4, the amount of hot carriers trapped in the gate insulating film 3 can be reduced. It can be reduced. Further, since the nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions contained in the interlayer insulating films 11 and 13 and It is possible to prevent hydroxide ions and the like from entering the film through the side wall surface of the gate insulating film 3. As a result, it is possible to suppress variations in the threshold voltage (Vth) with time due to hot carriers in the MOSFET (field effect transistor) Q, and also to suppress the threshold voltage with time due to hydrogen ions, hydroxide ions, etc. The fluctuation of (Vth) can be suppressed.

Further, it is possible to suppress the change of the threshold voltage (Vth) due to the hot carriers of the MOSFET (Field Effect Transistor) Q with the passage of time, and also the threshold with the passage of time due to the hydrogen ions and the hydroxide ions. Value voltage (Vt
Since the fluctuation of h) can be suppressed, the electrical reliability of the semiconductor integrated circuit device having the MOSFET (field effect transistor) Q can be improved.

Further, the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region is relaxed, and the electric field strength generated in this region is not weakened. Since it is possible to suppress variations in the threshold voltage (Vth) of the field effect transistor (Q) over time, a part of the drain region on the channel formation region side has a lower impurity concentration than the other regions. You do not have to set it. As a result,
Since the amount of current flowing between the source region and the drain region can be increased, MOSFET (field effect transistor)
The current gain of Q can be increased.

Further, since the current gain of the MOSFET (field effect transistor) Q can be increased, the MOSF
It is possible to increase the operating speed of the semiconductor integrated circuit device having the ET (field effect transistor) Q.

Further, in this embodiment, the MOSFET Q
When the source region and the drain region of the n-type semiconductor region 8 and the silicide layer 10 are formed, the electric field intensity generated between the drain region and the channel formation region is high, but the electric field intensity is not weakened and the Since it is possible to suppress variation in the threshold voltage (Vth) of the MOSFET (field effect transistor) Q with time due to carriers, the power gain of the MOSFET Q can be increased.

(2) A nitride insulating film 7 is provided on the side wall surface of the gate electrode 5. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), so that the hydrogen ions contained in the interlayer insulating films 11 and 13 are not affected. Gate electrode 5
It is possible to prevent the light from penetrating into the gate insulating film 3 through the side wall surface of the film. As a result, MOSF
It is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions, etc. of the ET (field effect transistor) Q.

In the method of manufacturing the MOSFET Q mounted on the semiconductor integrated circuit device, thermal oxidation is performed after the step of forming the gate electrode 5 and before the step of forming the nitride insulating film 7. Treated or oxynitrided,
As shown in FIG. 7, a step of forming an insulating film 6 made of a thermal silicon oxide film or a silicon oxynitride film on the upper surface of the gate electrode 5 and the side wall surface thereof may be provided. In this case, in the step of forming the gate electrode 5, the removal amount of the gate insulating film 3 removed by the side etching can be supplemented.

The step of forming the pair of n-type semiconductor regions 8 which are the source region and the drain region is after the step of forming the gate electrode 5 and the step of forming the nitride insulating film 7. You may go before.

The step of forming the pair of n-type semiconductor regions 8 serving as the source region and the drain region is after the step of forming the sidewall spacers 9,
It may be performed before the step of forming the refractory metal film 10A.

Example 2 A schematic structure of a semiconductor integrated circuit device having a MOSFET according to Example 2 of the present invention is shown in FIG. 8 (main part sectional view).

As shown in FIG. 8, a MOSFET (field effect transistor) Q mounted on a semiconductor integrated circuit device.
Is formed on the surface of the element formation region (active region) of the p-type semiconductor substrate 1 made of, for example, single crystal silicon. MOSF
The ETQ is mainly composed of a p-type semiconductor substrate 1 which is a channel formation region, a gate insulating film 3, a gate electrode 5, and a pair of n-type semiconductor regions 8 which are a source region and a drain region. That is, the MOSFET Q of this embodiment is composed of a field effect transistor in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween, as in the first embodiment.

A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. In addition, the nitride insulating film 7 is provided between the sidewall surface of the gate insulating film 3 and the sidewall spacer 9, that is, on the sidewall surface of the gate insulating film 3.
Is provided. In addition, between the side wall surface of the gate electrode 5 and the side wall spacer 9, that is, the gate electrode 5
A nitride insulating film 7 is provided on the side wall surface of the. Also,
A nitride insulating film 7 is provided on the upper surface of the gate electrode 5. That is, the surface of the gate electrode 5 of the MOSFET Q of this embodiment is covered with the nitride insulating film 7.

As described above, by providing the nitride insulating film 7 on the upper surface of the gate electrode 5 and on the side wall surface thereof, the nitride insulating film 7 is converted into hydrogen ions (-H +) and hydroxide ions (-OH). On the other hand, since it is impermeable, hydrogen ions, hydroxide ions and the like contained in the interlayer insulating film 11 and the interlayer insulating film 13 permeate through the gate electrode from the upper surface and the side wall surface of the gate insulating film 3 It is possible to prevent the intrusion.
As a result, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions, etc. of the MOSFET (field effect transistor) Q.

(Embodiment 3) FIG. 9 shows a schematic structure of a semiconductor integrated circuit device having a nonvolatile memory element according to a third embodiment of the present invention.

As shown in FIG. 9, a nonvolatile memory element (field effect transistor) mounted on a semiconductor integrated circuit device.
Qe is formed on the surface of the element formation region (active region) of the p-type semiconductor substrate 1 made of, for example, single crystal silicon. The element formation region is defined around the element isolation insulating film 2 formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1, and is insulated and isolated from other element formation regions.

The nonvolatile memory element Qe mainly includes a p-type semiconductor substrate 1, which is a channel forming region, a gate insulating film 3, a charge storage gate electrode (floating gate electrode).
5, a gate insulating film 14, a control gate electrode (control gate electrode) 15, and a pair of n-type semiconductor regions 8 which are a source region and a drain region. Gate insulating film 3
Is formed on the surface of the p-type semiconductor substrate 1, and is formed of, for example, a thermal silicon oxide film. The charge storage gate electrode 5 is formed on the surface of the gate insulating film 3, and is formed of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced. The gate insulating film 14 is formed on the upper surface of the charge storage gate electrode and is formed of, for example, a thermal silicon oxide film. The control gate electrode 15 is formed on the upper surface of the charge storage gate electrode 5 with the gate insulating film 14 interposed, and is formed of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced. That is, the nonvolatile memory element Qe is composed of a field effect transistor in which the charge storage gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed.

Each of the pair of n-type semiconductor regions 8 serving as the source region and the drain region is formed on the surface of the element formation region of the p-type semiconductor substrate 1, and is different from the control gate electrode 15 and the charge storage gate electrode 5. Formed by self-alignment.

Sidewall spacers 9 are formed on the side walls of the charge storage gate electrode 5 and the control gate electrode 15 in the gate length direction.

Of the pair of n-type semiconductor regions 8 which are the source region and the drain region, one n-type semiconductor region 8
The wiring 12 is electrically connected to the wiring through a connection hole 11A formed in the interlayer insulating film 11. The interlayer insulating film 11 is formed for the purpose of insulating and separating the control gate electrode 15 and the wiring 12, and is formed of, for example, a silicon oxide film formed by a chemical vapor deposition method (CVD method). Since the interlayer insulating film 11 is formed at a low temperature based on the process of lowering the temperature of the semiconductor integrated circuit device, the interlayer insulating film 11 contains a large amount of hydrogen ions, hydroxide ions and the like.

An interlayer insulating film 13 is formed on the wiring 12. The interlayer insulating film 13 is formed for the purpose of insulating and separating the wiring 12 and an upper wiring (not shown), and is formed of, for example, a silicon oxide film formed by a chemical vapor deposition method.
Since the interlayer insulating film 13 is formed at a low temperature based on the temperature lowering process of the semiconductor integrated circuit device like the above-described interlayer insulating film 12, the interlayer insulating film 13 has a large amount of hydrogen ions and hydroxide ions. Etc. are included.

A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. Since the nitride insulating film 4 can reduce the number of dangling bonds (unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 directly below the gate insulating film 3, the number of dangling bonds in the gate insulating film 3 is reduced. The amount of hot carriers captured can be reduced.

The nitride insulating film 4 is formed of a silicon oxynitride film formed by oxynitriding. This silicon oxynitride film is a silicon nitride film (Si ₃ N ₄ , Six) formed by a vapor phase chemical growth method.
Compared with Nx), the film quality is better and the adhesion is higher.

A nitride insulating film 7 is provided between the sidewall surface of the gate insulating film 3 and the sidewall spacer 9, that is, on the sidewall surface of the gate insulating film 3. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions and water contained in the interlayer insulating film 11 and the interlayer insulating film 13 are not formed. It is possible to prevent acid ions and the like from entering the film through the side wall surface of the gate insulating film 3.

A nitride insulating film 7 is provided between the side wall surface of the charge storage gate electrode 5 and the side wall spacer 9, that is, on the side wall surface of the charge storage gate electrode 5. This nitride insulating film 7 has hydrogen ions (-H +) and hydroxide ions (-).
OH) and the like are impermeable, so the interlayer insulating film 1
1 and hydrogen ions contained in the interlayer insulating film 13 can be prevented from penetrating into the gate insulating film 3 through the sidewall surface of the charge storage gate electrode 5 through the film. .

A nitride insulating film 7 is provided between the sidewall surface of the gate insulating film 14 and the sidewall spacer 9, that is, on the sidewall surface of the gate insulating film 14. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions and water contained in the interlayer insulating film 11 and the interlayer insulating film 13 are not formed. It is possible to prevent acid ions and the like from penetrating into the gate insulating film 3 through the sidewall surface of the gate insulating film 14 through the film.

Between the side wall surface of the control gate electrode 15 and the side wall spacer 9, that is, the control gate electrode 15
A nitride insulating film 7 is provided on the side wall surface of the. The nitride insulating film 7 is formed by hydrogen ions (-H +) and hydroxide ions (-OH).
Since it has a non-transparency with respect to etc., hydrogen ions, hydroxide ions, etc. contained in the interlayer insulating film 11 and the interlayer insulating film 13 permeate through the side wall surface of the control gate electrode 15 through the film, and thus the gate insulating film is formed. Invasion into the membrane 3 can be prevented.

The nitride insulating film 7 is formed of a silicon oxynitride film formed by an oxynitriding process or a silicon nitride film formed by a vapor phase chemical growth method. In this embodiment, the silicon nitride film 7 is formed of a silicon nitride film formed by a vapor phase chemical growth method.

Next, a method of manufacturing the non-volatile memory element Qe mounted on the semiconductor integrated circuit device will be described with reference to FIGS. 10 to 13 (main part sectional views showing each manufacturing step).

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Then, using the well-known selective oxidation method, the p
An element isolation insulating film 2 made of a silicon oxide film is formed on the surface of the element isolation region (inactive region) of the type semiconductor substrate 1.

Next, a thermal oxidation process is performed to form a gate insulating film 3A made of a thermal silicon oxide film on the surface of the element forming region (active region) of the p-type semiconductor substrate 1.

Next, an oxynitriding process is performed to form a nitride insulating film 4A made of a silicon oxynitride film between the p-type semiconductor substrate 1 and the gate insulating film 3A.

Then, a polycrystalline silicon film 5A is formed on the entire surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3A by, for example, a vapor phase chemical growth method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film 5A during or after the deposition.

Next, a gate insulating film 14A made of a silicon oxide film is formed on the surface of the polycrystalline silicon film 5A by, for example, a vapor phase chemical growth method, and then a vapor phase chemical film is formed on the surface of the gate insulating film 14A. A polycrystalline silicon film 15A is formed by the growth method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film 15A during or after the deposition.

Next, as shown in FIG. 10, the polycrystalline silicon film 1 on the surface of the element forming region of the p-type semiconductor substrate 1 is formed.
A mask 16 is formed on the surface of 5A. The mask 16 is formed of, for example, a photoresist film.

Next, using the mask 16 as an etching mask, the polycrystalline silicon film 15A, the gate insulating film 14A, the polycrystalline silicon film 5A, the gate insulating film 3A, and the nitride insulating film 4A are sequentially patterned. As shown in FIG. 11, the gate insulating film 3 is formed on the surface of the element forming region of the p-type semiconductor substrate 1, the charge storage gate electrode 5 is formed on the surface of the gate insulating film 3, the p-type semiconductor substrate 1 and the gate insulating film. 3, the gate insulating film 14 is formed on the upper surfaces of the nitride insulating film 4 and the charge storage gate electrode 5, and the control gate electrode 15 is formed on the surface of the gate insulating film 14. In this step, the surface of the other element formation region except the surface of the element formation region of the p-type semiconductor substrate 1 below the charge storage gate electrode 5 is exposed.

Next, a nitride insulating film 7 is formed on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the control gate electrode 15 and the side wall surface thereof, and the side wall surface of the charge storage gate electrode 5.

Next, an n-type impurity is introduced into the surface of the element formation region of the p-type semiconductor substrate 1 by self-alignment with the gate electrode 5 and the element isolation insulating film 2, for example, by ion implantation. As shown in 12, a pair of n-type semiconductor regions 8 which are a source region and a drain region are formed. In this step, since the n-type impurity is introduced through the nitride insulating film 7, the p-type semiconductor substrate 1 by the impurity introduction.
It is possible to suppress physical damage on the surface of the element formation region.

Next, as shown in FIG. 13, sidewall spacers 9 are formed on the side walls of the charge storage gate electrode 5 and the control gate electrode 15 in the gate length direction.
The sidewall spacer 9 is formed by forming a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the control gate electrode 15 by, for example, a chemical vapor deposition method, and then forming the film thickness of the silicon oxide film and the nitride insulating film. amount corresponding to the thickness of 7, the silicon oxide film and a nitride insulating film 7 RIE (R eactive I on E tchin
It is formed by performing anisotropic etching such as g).
In this step, the upper surface of the control gate electrode 15 is exposed. In addition, p around the sidewall spacer 9
The surface of the element formation region of the mold semiconductor substrate 1 is exposed. Through this process, the nonvolatile memory element Qe is almost completed.

Next, an interlayer insulating film 11 is formed on the entire surface of the p-type semiconductor substrate 1, a wiring 12 is formed on the interlayer insulating film 11, and an interlayer insulating film 13 is formed on the wiring 12. The semiconductor integrated circuit device shown in is formed.

As described above, according to this embodiment, the following operational effects can be obtained.

(1) In a semiconductor integrated circuit device having a non-volatile memory element (field effect transistor) Qe in which a charge storage gate electrode 5 is formed on the surface of a p-type semiconductor substrate 1 with a gate insulating film 3 interposed therebetween, A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3, and a nitride insulating film 7 is provided on the side wall surface of the gate insulating film 3.

With this structure, p just below the gate insulating film 3 is formed.
Since the number of dangling bonds (unpaired electrons) existing on the surface of the type semiconductor substrate 1 can be reduced by the nitride insulating film 4, the amount of hot carriers trapped in the gate insulating film 3 can be reduced. It can be reduced. Further, since the nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions contained in the interlayer insulating films 11 and 13 and It is possible to prevent hydroxide ions and the like from entering the film through the side wall surface of the gate insulating film 3. As a result, it is possible to suppress variations in the threshold voltage (Vth) due to hot carriers of the non-volatile memory element (field effect transistor) Qe with time, and to eliminate temporal changes due to hydrogen ions and hydroxide ions. The fluctuation of the threshold voltage (Vth) can be suppressed.

Further, it is possible to suppress the temporal change of the threshold voltage (Vth) due to the hot carriers of the non-volatile memory element (field effect transistor) Qe, and it is possible to suppress the temporal change due to the hydrogen ion or the hydroxide ion. Since it is possible to suppress the fluctuation of the threshold voltage (Vth), the electrical characteristics such as the data writing characteristic, the data erasing characteristic and the data holding characteristic can be stabilized.

Further, it is possible to suppress the change of the threshold voltage (Vth) due to the hot carriers of the MOSFET (Field Effect Transistor) Q with the passage of time, and the threshold due to the hydrogen ions or the hydroxide ions with the passage of time. Value voltage (Vt
Since the fluctuation of h) can be suppressed, it is a nonvolatile memory element.
(Field Effect Transistor) The electrical reliability of the semiconductor integrated circuit device having Qe can be improved.

Further, the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region is relaxed, and the electric field strength generated in this region is not weakened, and the non-volatile property caused by hot carriers is obtained. Threshold voltage (Vth) of storage element (field effect transistor) Qe over time
Therefore, it is not necessary to set the impurity concentration of a part of the drain region on the channel formation region side to be lower than the impurity concentration of the other regions. As a result, the amount of current flowing between the source region and the drain region can be increased, so that the current gain of the nonvolatile memory element (field effect transistor) Qe can be increased.

Since the current gain of the non-volatile memory element (field effect transistor) Qe can be increased, the operating speed of the semiconductor integrated circuit device having the non-volatile memory element (field effect transistor) Qe can be increased. You can

(2) A nitride insulating film 7 is provided on the side wall surface of the charge storage gate electrode 5. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH), and the like, so that the hydrogen contained in the interlayer insulating films 11 and 13 is reduced. It is possible to prevent ions, hydroxide ions and the like from penetrating through the film from the side wall surface of the charge storage gate electrode 5 and entering the gate insulating film 3.
As a result, the nonvolatile memory element (field effect transistor) Q
Further, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to the hydrogen ion or the hydroxide ion of e.

(3) A nitride insulating film 7 is provided on the side wall surface of the gate insulating film 14. With this configuration, the nitride insulating film 7
Is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), the hydrogen ions and hydroxide ions contained in the interlayer insulating film 11 and the interlayer insulating film 13 are gated. It is possible to prevent the insulating film 14 from penetrating into the gate insulating film 3 through the sidewall surface of the insulating film 14. As a result, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.

(4) A nitride insulating film 7 is provided on the side wall surface of the control gate electrode 15. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH), and the like, so that the hydrogen contained in the interlayer insulating films 11 and 13 is reduced. It is possible to prevent ions, hydroxide ions and the like from penetrating through the film from the side wall surface of the control gate electrode 15 and entering the gate insulating film 3. As a result, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.

Example 4 A schematic structure of a semiconductor integrated circuit device having a nonvolatile memory element according to Example 4 of the present invention is shown in FIG. 14 (main part sectional view).

As shown in FIG. 14, the nonvolatile memory element (field effect transistor) Qe mounted on the semiconductor integrated circuit device is an element formation region (active region) of the p-type semiconductor substrate 1 made of, for example, single crystal silicon. It is configured on the surface part of. The nonvolatile memory element Qe is mainly composed of a pair of a p-type semiconductor substrate 1 which is a channel formation region, a gate insulating film 3, a charge storage gate electrode 5, a gate insulating film 14, a control gate electrode 15, a source region and a drain region. Of n-type semiconductor region 8. That is, the nonvolatile memory element Qe of this embodiment
Is a field effect transistor in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween, as in the third embodiment.

A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. In addition, the nitride insulating film 7 is provided between the sidewall surface of the gate insulating film 3 and the sidewall spacer 9, that is, on the sidewall surface of the gate insulating film 3.
Is provided. In addition, between the side wall surface of the gate electrode 5 and the side wall spacer 9, that is, the gate electrode 5
A nitride insulating film 7 is provided on the side wall surface of the. Also,
A nitride insulating film 7 is provided between the side surface of the gate insulating film 14 and the sidewall spacer 9, that is, on the side wall surface of the gate insulating film 14. A nitride insulating film 7 is provided between the side wall surface of the control gate electrode 15 and the side wall spacer 9, that is, on the side wall surface of the control gate electrode 15. A nitride insulating film 7 is provided on the upper surface of the control gate electrode 15. That is, the surface of the control gate electrode 15 of the nonvolatile memory element Q of the present embodiment is covered with the nitride insulating film 7.

As described above, by providing the nitride insulating film 7 on the upper surface of the control gate electrode 5 and on the side wall surface thereof, the nitride insulating film 7 becomes hydrogen ion (-H +) or hydroxide ion (-OH).
And the like, hydrogen ions and hydroxide ions contained in the interlayer insulating film 11 and the interlayer insulating film 13 are transmitted through the control gate electrode 15 from the upper surface and the side wall surface thereof. It is possible to prevent entry into the gate insulating film 3. As a result, it is possible to further suppress the temporal change in the threshold voltage (Vth) due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.

As described above, the inventions made by the present inventor are
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device having a field effect transistor in which a source region and a drain region are composed of a pair of p-type semiconductor regions.

[0104]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a field-effect transistor in which a gate electrode is formed on the surface of a semiconductor substrate with a gate insulating film interposed, a threshold voltage ( Vth) fluctuation can be suppressed and the threshold voltage over time due to hydrogen ions, hydroxide ions, etc.
The fluctuation of (Vth) can be suppressed.

Further, the current gain of the field effect transistor can be increased.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having a MOSFET (Field Effect Transistor) that is Embodiment 1 of the present invention.

FIG. 2 is a main-portion cross-sectional view for illustrating the method for manufacturing the MOSFET.

FIG. 3 is a main-portion cross-sectional view for illustrating the method for manufacturing the MOSFET.

FIG. 4 is a main-portion cross-sectional view for illustrating the method for manufacturing the MOSFET.

FIG. 5 is a main-portion cross-sectional view for illustrating the method for manufacturing the MOSFET.

FIG. 6 is a main-portion cross-sectional view for illustrating the method for manufacturing the MOSFET.

FIG. 7 is a fragmentary cross-sectional view for explaining the method for manufacturing the MOSFET.

FIG. 8 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having a MOSFET (Field Effect Transistor) that is Embodiment 2 of the present invention.

FIG. 9 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having a nonvolatile memory element (field effect transistor) according to a third embodiment of the present invention.

FIG. 10 is a main-portion cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.

FIG. 11 is a main-portion cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.

FIG. 12 is a main-portion cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.

FIG. 13 is a main-portion cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.

FIG. 14 is a nonvolatile memory element that is Embodiment 4 of the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit device having (field effect transistor).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... element isolation insulating film, 3 ... gate insulating film, 4 ... nitride insulating film, 5 ... gate electrode, charge storage gate electrode, 6 ... insulating film, 7 ... nitride insulating film, 8 ... n-type semiconductor region, 9 ... Sidewall spacer, 10 ... Silicide layer, 11, 13 ... Interlayer insulating film, 11A, 11B ... Connection hole, 12 ... Wiring, 14 ... Gate insulating film, 15 ... Control gate electrode, 16 ... Mask .

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/788 29/792 (72) Inventor Kosuke Okuyama 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Katsuhiko Kubota 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated Company Hitachi Ltd. Semiconductor Division

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a field effect transistor in which a gate electrode is formed on the surface of a semiconductor substrate with a gate insulating film interposed therebetween, wherein a nitride insulating film is provided between the semiconductor substrate and the gate insulating film. Together with
A semiconductor integrated circuit device comprising a nitride insulating film provided on a side wall surface of the gate insulating film. 2. A nitride insulating film provided between the semiconductor substrate and the gate insulating film is a silicon oxynitride film formed by an oxynitriding treatment, and a nitride provided on a side wall surface of the gate insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a silicon oxynitride film formed by an oxynitriding treatment or a silicon nitride film formed by a vapor phase chemical growth method. 3. The semiconductor integrated circuit device according to claim 1, wherein a nitride insulating film is provided on an upper surface of the gate electrode and a side wall surface thereof. 4. The nitride insulating film provided on the upper surface and the side wall surface of the gate electrode is a silicon oxynitride film formed by an oxynitriding treatment or a silicon nitride film formed by a vapor phase chemical growth method. The semiconductor integrated circuit device according to claim 3, wherein. 5. The source region or the drain region of the field effect transistor is composed of a semiconductor region formed on the surface of the semiconductor substrate and a silicide layer formed on the surface of the semiconductor region. The semiconductor integrated circuit device according to any one of claims 1 to 4. 6. The gate electrode is a charge storage gate electrode for storing charges, and the field-effect transistor is
6. The semiconductor integrated circuit device according to claim 1, wherein the control gate electrode is formed on the charge storage gate electrode with a gate insulating film interposed therebetween, which is a nonvolatile memory element. . 7. A nitride insulating film is formed on a side wall surface of a gate insulating film between the charge storage gate electrode and the control gate electrode, and a nitride insulating film is formed on an upper surface of the control gate electrode and a side wall surface thereof. The semiconductor integrated circuit device according to claim 6, wherein a film is provided. 8. The nitride insulating film provided on the side wall surface of the charge storage gate electrode, the upper surface of the control gate electrode and the side wall surface thereof is a silicon oxynitride film formed by an oxynitriding process or a vapor phase chemistry. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is a silicon nitride film formed by a growth method. 9. The semiconductor integrated circuit device according to claim 1, wherein an interlayer insulating film is formed on the semiconductor substrate.