JPH05235023A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the hot carrier resisting property of a MIS type field-effect transistor. CONSTITUTION:A polycrystalline silicon side wall 21 is arranged on both sides of a gate electrode 8 which is composed of polycrystalline silicon through the intermediary of a silicon oxide film 20. A high density N-type diffusion region 23 is formed on the above-mentioned polycrystalline silicon side wall 21. On this region, a drain high density N-type diffusion region 22 and a low density N-type diffusion region 19 and a P-type silicon substrate 16 are connected. As a result, a gate electric field works on the side face part of the gate electrode 18 in the silicon oxide film 20, and the depletion layer, generated by the implantation and capture of electrons in the silicon oxide film 20 on the interface between the polycrystalline silicon side wall 21 and the silicon oxide film 20, can be removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element structure of a MIS field effect transistor having excellent hot carrier resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the gate length of a transistor in a MIS type semiconductor integrated circuit becomes shorter in recent years, deterioration of transistor characteristics due to hot carriers generated by a high electric field near the drain has become a serious problem. As a countermeasure against this problem, it has become common to use an LDD structure (Lightly Doped Drain structure) for the drain of a MIS transistor having a gate length of about 1 μm or less.

FIG. 3 shows a typical MIS having a conventional LDD structure.
It is a cross-sectional structure of a transistor. In FIG. 3, 1 is a semiconductor substrate, 2 is a gate oxide film, 3 is a gate electrode, 4 is a sidewall oxide film, 5 is a low concentration drain diffusion layer, and 6 is a drain diffusion layer.

The feature of this LDD structure MIS transistor is that, for example, in the case of an N-channel MIS transistor,
In FIG. 3, the drain layer with a low concentration (n minus region)
5 is provided on the side of the gate electrode 3 in the gate oxide film 2 and the sidewall oxide film 4 and in contact with the drain diffusion layer 6 to reduce the magnitude of the electric field generated in the vicinity of the drain (reference. Reference: "Micro Devices," published by Nikkei McGraw-Hill, August 22, 1983).

Next, a typical manufacturing method of the conventional LDD structure MIS transistor will be described with reference to FIG. In FIG. 4, 7 is a semiconductor substrate, 8 is a gate oxide film, 9 is a gate electrode, 10 is phosphorus ions to be implanted, 11 is a low concentration drain diffusion layer, 12 is a CVD silicon oxide film layer, 13 is a sidewall oxide film, 14 is an implanted arsenic ion, and 15 is a drain diffusion layer.

In FIG. 4A, after the gate electrode 9 is formed, phosphorus ions 10 are used with the gate electrode 9 as a mask.
Is ion-implanted to form the drain diffusion layer 11 having a low concentration. Next, as shown in FIG. 4B, CVD is performed on the main surface of the semiconductor substrate.
The silicon oxide film layer 12 is formed by the method of FIG.
As shown in (c), the silicon oxide film layer 12 is etched back by using an anisotropic dry etching technique to form a sidewall oxide film 13 on the side portion of the gate electrode 9. Subsequently, arsenic ions 14 are ion-implanted using the sidewall oxide film 13 as a mask to form a drain diffusion layer 15. In this way, the drain diffusion region 11 having a low concentration for relaxing the electric field near the drain is formed under the sidewall oxide film 13 between the gate electrode 9 and the drain diffusion layer 15.

[0007]

The conventional LDD structure MIS transistor described above is a normal drain structure MIS transistor.
Compared with the transistor, it has a function of suppressing the electric field near the drain and suppressing the generation of hot carriers that cause the deterioration of the transistor. However, in recent years, a deterioration phenomenon peculiar to the conventional MIS transistor having the LDD structure has been discovered (reference document: Eiji Takeda, "Hot Carrier Effect", Nikkei McGraw-Hill, p. 121, 1987). That is, in the conventional MIS transistor having the LDD structure, the region where the electric field is relatively strong spreads over the entire low-concentration drain diffusion layer, so that hot carriers due to impact ionization do not exist under the gate electrode. It also occurs in the diffusion layer region, and in the case of an N-channel transistor, for example, electrons are injected and trapped in the sidewall oxide film, and the concentration is low in the drain diffusion layer region (n minus region).
To pinch off. Therefore, in the case of an N-channel transistor, Gm is deteriorated.

An object of the present invention is to solve the problems of the conventional MIS transistor having the LDD structure.

[0009]

The semiconductor device of the present invention comprises:
On the side of the gate electrode of the MIS field effect transistor of LDD structure having a low concentration drain diffusion layer, it is electrically insulated from the gate electrode and electrically connected to the drain region and has the same conductivity type as the drain region. It has a structure having a side wall of polycrystalline silicon doped with.

The semiconductor device manufacturing method of the present invention is
A step of forming a gate electrode on a semiconductor substrate of one conductivity type; a step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask; A step of forming an insulating film on a side of the semiconductor substrate, a step of exposing the semiconductor substrate in a region where a drain region is to be formed subsequent to the step, and a conductivity type impurity opposite to the semiconductor substrate on the main surface of the semiconductor substrate subsequent to the step. A step of forming a polycrystalline silicon film layer added with, a step of forming a polycrystalline silicon side wall on the side portion of the gate electrode by etching back the polycrystalline silicon film layer, the gate electrode and the polycrystalline silicon side wall. Is used as a mask to perform ion implantation for source / drain formation on the semiconductor substrate.

[0011]

In the present invention, the polycrystalline silicon side wall electrically connected to the drain is provided above the low concentration drain diffusion layer. Therefore, hot carriers due to impact ionization generated in the low-concentration drain diffusion layer region are
Unlike the case of the conventional LDD structure, it is not immediately implanted and captured in the sidewall oxide film on the upper part of the low concentration drain diffusion layer. Some hot carriers are injected and trapped in the insulating film between the polycrystalline silicon side wall and the gate electrode,
The amount of hot carriers injected / trapped is smaller than that in the conventional LDD structure because it is far from the hot carrier generation position. Further, since the position where the injection / capture occurs is close to the gate electrode and far from the low-concentration drain region, the degree to which the conductance of the low-concentration drain diffusion layer region is affected by the injection / capture of hot carriers into the insulating film small.

[0012]

EXAMPLE An example of a semiconductor device of the present invention will be described with reference to FIG. This embodiment is a case of an N channel MIS type transistor formed on a P type silicon substrate, but in the case of an N channel MIS type transistor formed in a P well region, or formed on an N type silicon substrate or in an N well region. Of course, it can be applied to the case of the P-channel MIS type transistor.

In FIG. 1, 16 is an impurity concentration of about 1 × 10 ¹⁵ cm ^-3.
In the P-type silicon substrate of, the impurity concentration near the surface is about 1 ×
It is 10 ¹⁶ cm ^-3 . Reference numeral 17 is a gate oxide film having a film thickness of 20 nm, 18 is a gate electrode formed of polycrystalline silicon to which phosphorus is added, and the film thickness is about 400 nm and the gate length is about 1 μm. 19 junction depth in N-type diffusion region having an impurity concentration of about 1 × 10 ¹⁷ cm ^-3 is about 0.2 [mu] m. Reference numeral 20 denotes a silicon oxide film on the side surface of the polycrystalline silicon electrode, which has a thickness of about 40 nm. Reference numeral 21 denotes a polycrystalline silicon side wall to which phosphorus is added at about 1 × 10 ¹⁷ cm ^−3, which is electrically connected to the N-type diffusion region 19. The width of the polycrystalline silicon side wall 21 is about 0.2 μm. Reference numeral 22 denotes an N-type diffusion region (source / drain diffusion region) having an impurity concentration of about 1 × 10 ²¹ cm ^−3. The surface portion 23 of the polycrystalline silicon side wall is also the source / drain diffusion region 22.
It has the same N-type impurity concentration as.

MI of normal drain structure which is not LDD structure
In the S-transistor, when the gate length is about 1 μm or less, the electric field strength becomes extremely large at the drain end of the channel, and the electrons accelerated by this high electric field cause impact ionization, and the electrons or holes generated at that time are generated. It is injected into the gate oxide film, which causes a change in the threshold voltage of the MIS transistor and deterioration of Gm. In the MIS transistor of this embodiment, the drain diffusion layer 19 having a low impurity concentration is provided on the surface of the silicon substrate at the end of the gate electrode 18. The diffusion layer 19 having a low concentration weakens the electric field strength in the horizontal direction at the end of the drain (usually about 1/2 of the drain structure),
The generation of hot carriers, which is the cause of deterioration, is reduced.
Of the hot carriers thus generated, holes flow to the silicon substrate 16 and most of the electrons are sucked into the drain 22. The electrons not sucked into the drain are injected and captured in the silicon oxide film 20 on the side surface of the polycrystalline silicon electrode 18. In the conventional MIS transistor having the LDD structure described in the section of the prior art, electron injection / capture is performed on the sidewall of the oxide film (4 in FIG. 3) provided immediately above the low-concentration drain region. In addition, the surface of the low-concentration (n-minus) drain region that the electric field of the gate electrode does not reach is depleted, and the conductance of this portion becomes extremely low.
There is a problem that the Gm of the transistor deteriorates.
However, in the semiconductor device of the present invention, since the silicon oxide film 20 on the side surface of the polycrystalline silicon electrode on which the implantation / trapping is performed is close to the gate electrode 18, when a positive voltage is applied to the gate electrode 18, the The depletion layer on the surface of the polycrystalline silicon side wall 21 (interface with the silicon oxide film 20) generated by injection and capture of electrons into the oxide film 20 is easily eliminated. Thus, the MIS transistor of the present invention has excellent hot carrier resistance.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
Will be explained. In this embodiment, N is formed on the P-type semiconductor substrate.
A case of forming a channel MIS type transistor is described.
It First, as shown in FIG. 2A, the impurity concentration is about 1 × 10.¹⁵cm
^-3The gate oxide film 2 is formed on the P-type semiconductor substrate 24 by a usual method.
5 (film thickness 20 nm in this embodiment) and 1 × 10²⁰cm ^-3
Gate made of polycrystalline silicon with some phosphorous added
The electrode 26 (in this embodiment, the film thickness is about 400 nm, the gate length is 1
μm) are sequentially formed, and the gate electrode 26 is used as a mask.
1 x 10 phosphorus ions 27¹³cm^-2Inject approximately low concentration
A rain region 28 is formed. Next, as shown in FIG.
Thermal oxidation treatment is applied to the polycrystalline silicon gate electrode 26
It is oxidized to form a silicon oxide film 29. At this time
The oxide film is a fool of the surface of the polycrystalline silicon gate electrode 26.
Not on the surface of the low concentration drain region 28
However, due to the difference in impurity concentration in the main oxidation process
Oxide film on the crystalline silicon gate electrode 26
Oxide stripes thicker than the oxide film thickness on the surface of the in-region 28
Select the case (in the present embodiment, the former film thickness of about 40 nm
On the other hand, the latter is about 20 nm). Next, as shown in FIG.
Low concentration drain by anisotropic dry etching method
By removing the silicon oxide film on the surface of the region 28,
The surface of the rain area 28 is exposed. At this time
Silicon is formed on the side surface and the upper surface of the recon gate electrode 26.
The oxide film 29 remains. Next, as shown in FIG.
A polycrystalline silicon film layer 30 is formed on the main surface of the semiconductor substrate.
(In this embodiment, the film thickness is about 200 nm). Polycrystalline silicon
Phosphorus 1 × 10 is formed on the film 30 by an ion implantation method.¹⁷cm^-3degree
Add it. Next, as shown in FIG.
The crystalline silicon film 30 is formed by the anisotropic dry etching method.
Etch back to remove polycrystal silicon on the side of the gate electrode 26.
The sidewall 31 is formed. The polycrystalline silicon side wall 31 is low
Is in electrical contact with the concentration drain region 28, and
Is insulated from the gate electrode 26 by the silicon oxide film 29.
There is. Next, as shown in FIG.
The gate electrode 26 and the polycrystalline silicon side wall 31 as a mask.
Then add 1 × 10 arsenic ions 32¹⁵cm^-2Highly impure
A drain region 33 having a physical concentration is formed. At this time
The high-concentration impurity region 34 is also formed on the surface portion of the recon sidewall 31.
It is formed. Next, heat treatment is applied as shown in FIG.
To form a desired diffusion depth. The following is a normal MIS type collection
It depends on the manufacturing method of the product circuit.

[0016]

According to the semiconductor device of the present invention, deterioration of a MIS transistor having a short channel length due to hot carriers can be significantly reduced, and the reliability of a semiconductor integrated circuit can be increased. The semiconductor device manufacturing method of the present invention also provides a method of manufacturing the semiconductor device of the present invention while maintaining consistency with the conventional semiconductor integrated circuit manufacturing method.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional view of a semiconductor device of the present invention.

2A to 2C are cross-sectional views in order of the processes, for illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a sectional view showing a conventional semiconductor device.

4A to 4C are cross-sectional views in order of the processes, for illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 16 P-type silicon substrate 17 Gate oxide film 18 Gate electrode formed of polycrystalline silicon 19 Low-concentration N-type diffusion region 20 Silicon oxide film 21 Polycrystalline silicon sidewall 22, 23 High-concentration N-type diffusion region 24 P-type semiconductor substrate 25 Gate oxide film 26 Gate electrode 27 Phosphorus ion 28 Low concentration drain region 29 Silicon oxide film 30 Polycrystalline silicon film layer 31 Polycrystalline silicon side wall 32 Arsenic ion 33,34 High impurity concentration region

Claims (2)

[Claims] 1. A gate electrode side portion of a MIS field effect transistor having a low concentration drain diffusion layer is electrically insulated from the gate electrode of the transistor and electrically connected to the drain region of the transistor. A semiconductor device having a polycrystalline silicon sidewall doped with an impurity of the same conductivity type as the drain region. 2. A step of forming a gate electrode on a semiconductor substrate of one conductivity type, a step of implanting impurity ions of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask, Subsequent to the step of forming an insulating film on the side of the gate electrode, the step of exposing the semiconductor substrate in the region to form the drain region subsequent to the step, and the semiconductor substrate on the main surface of the semiconductor substrate subsequent to the step Forming a polycrystalline silicon film layer doped with impurities of opposite conductivity type; forming a polycrystalline silicon side wall on the side of the gate electrode by etching back the polycrystalline silicon film layer; And ion implantation for source / drain formation into the semiconductor substrate using the electrodes and the sidewalls of polycrystalline silicon as a mask. The method of manufacturing a semiconductor device according to.