JP3756222B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed. is there.
[0002]
[Prior art]
As a semiconductor integrated circuit device mounting a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed, for example, a MOSFET (MetalOxideSemicoductorFieldEffectTA semiconductor integrated circuit device mounting a ransistor is being developed.
[0003]
The MOSFET tends to be miniaturized for the purpose of increasing the degree of integration of the semiconductor integrated circuit device. With the miniaturization of the MOSFET, in particular, in a MOSFET whose gate length dimension reaches submicron, as described in, for example, Japanese Examined Patent Publication No. Sho 62-31506, a partial region on the channel formation region side of the drain region Is set to a lower impurity concentration than the impurity concentration in other regions.LightlyDopedDrain) structure is an essential requirement. A MOSFET employing an LDD structure can reduce the amount of diffusion of the drain region to the channel formation region side and ensure the channel length dimension, thereby suppressing the occurrence of the short channel effect. Further, a MOSFET adopting the LDD structure can relax the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region, and can weaken the electric field strength generated in this region. The amount of hot carriers generated can be reduced. The reduction in the amount of hot carriers generated can suppress fluctuations in the threshold voltage (Vth) of the MOSFET over time.
[0004]
[Problems to be solved by the invention]
The MOSFET (field effect transistor) having the LDD structure reduces the generation amount of hot carriers (electrons and holes) injected and trapped in the gate insulating film, and suppresses the fluctuation of the threshold voltage with time. However, fluctuations in the threshold voltage of the MOSFET over time include the case where high energy electrons and holes generated by impact ionization are injected and captured in the gate insulating film, and in the final protective film and interlayer insulating film. In some cases, hydrogen ions (-H +), hydroxide ions (-OH), and the like contained in the gate insulating film enter and are trapped. Hydrogen ions, hydroxide ions, and the like may enter the film from the side wall surface of the gate insulating film, or may penetrate the gate electrode and enter the gate insulating film. In particular, hydrogen ions, hydroxide ions, and the like have a high rate of penetration from the side wall surface of the gate insulating film. That is, the LDD-structured MOSFET can suppress a change in threshold voltage over time due to hot carriers, but cannot suppress a change in threshold voltage over time due to hydrogen ions, hydroxide ions, or the like. In recent years, the manufacturing process of semiconductor integrated circuit devices has been reduced in temperature, and since the interlayer insulating film formed at a low temperature contains a large amount of hydrogen ions, hydroxide ions, etc., hydrogen ions, hydroxide ions, etc. It is important to suppress fluctuations in the threshold voltage of the MOSFET over time due to.
[0005]
In addition, although the LDD structure MOSFET can suppress a change in threshold voltage with time, a part of the drain region on the channel formation region side is set to a lower impurity concentration than the impurity concentration of other regions. Therefore, the amount of current flowing between the source region and the drain region is reduced, and the current gain of the MOSFET is reduced. This decrease in the current gain of the MOSFET means a decrease in the operation speed of the semiconductor integrated circuit device on which the MOSFET is mounted.
[0006]
An object of the present invention is to provide a threshold over time caused by hot carriers of a field effect transistor in a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed therebetween. It is an object of the present invention to provide a technique capable of suppressing fluctuations in threshold voltage (Vth) over time caused by hydrogen ions, hydroxide ions, and the like while suppressing fluctuations in value voltage (Vth).
[0007]
Another object of the present invention is to provide a technique capable of achieving the object and increasing the current gain of the field effect transistor.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0010]
(1) In a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed, a nitride insulating film is provided between the semiconductor substrate and the gate insulating film At the same time, a nitride insulating film is provided on the side wall surface of the gate insulating film. The nitride insulating film provided between the semiconductor substrate and the gate insulating film is a silicon oxynitride film formed by oxynitriding, and the nitride insulating film provided on the side wall surface of the gate insulating film is,spiritIt is a silicon nitride film formed by a phase chemical growth method.
[0011]
(2)In a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed therebetween,
  Side wall spacers made of a silicon oxide film are provided on both sides of the gate electrode in the gate length direction,
  Providing a first nitride insulating film between the semiconductor substrate and the gate insulating film;
  A second silicon nitride film is provided between the gate electrode, the gate insulating film, the first nitride insulating film, and the semiconductor substrate and the sidewall spacer;
  The second silicon nitride film is formed on the side wall surface of the gate insulating film.
  In the above means, a pair of semiconductor regions which are self-aligned with the gate electrode to be a source region and a drain region are formed in the semiconductor substrate, and an interlayer insulating film is formed on the entire surface of the semiconductor substrate.
[0012]
[Action]
According to the means (1) described above, the number of dangling bonds (dangling bonds: unpaired electrons) existing on the surface of the semiconductor substrate immediately below the gate insulating film can be reduced by the nitride insulating film. The amount of hot carriers trapped in the film can be reduced. In addition, since the nitride insulating film is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), hydrogen ions and hydroxide ions contained in the interlayer insulating film are gate-insulated. Intrusion into the film from the side wall surface of the film can be prevented. As a result, the temporal threshold voltage (Vth) fluctuation caused by hot carriers of the field effect transistor can be suppressed, and the temporal threshold voltage (Vth) caused by hydrogen ions, hydroxide ions, etc. can be suppressed. Variation can be suppressed.
[0013]
In addition, the gradient of the impurity concentration distribution at the pn junction formed between the drain region and the channel formation region is relaxed, and the field effect transistor caused by hot carriers over time is reduced without weakening the electric field strength generated in this region. Therefore, it is not necessary to set a part of the drain region on the channel formation region side to a lower impurity concentration than the impurity concentration of other regions. As a result, the amount of current flowing between the source region and the drain region can be increased, so that the current gain of the field effect transistor can be increased.
[0015]
【Example】
The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a field effect transistor.
[0016]
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[0017]
(Example 1)
A schematic configuration of a semiconductor integrated circuit device having a MOSFET according to a first embodiment of the present invention is shown in FIG.
[0018]
As shown in FIG. 1, a MOSFET (field effect transistor) Q mounted on a semiconductor integrated circuit device is configured on the surface portion of an element formation region (active region) of a p-type semiconductor substrate 1 made of, for example, single crystal silicon. The The periphery of the element formation region is defined by an element isolation insulating film 2 formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1, and is insulated and isolated from other element formation regions.
[0019]
The MOSFET Q is mainly composed of a p-type semiconductor substrate 1, which is a channel formation region, a gate insulating film 3, a gate electrode 5, and a pair of n-type semiconductor regions 8 which are a source region and a drain region. The gate insulating film 3 is formed on the surface of the p-type semiconductor substrate 1, and is formed of, for example, a thermal silicon oxide film. The gate electrode 5 is formed on the surface of the gate insulating film 3, and is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. That is, the MOSFET Q is composed of a field effect transistor in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed.
[0020]
Each of the pair of n-type semiconductor regions 8 serving as the source region and the drain region is formed on the surface portion of the p-type semiconductor substrate 1 and formed in a self-aligned manner with respect to the gate electrode 5. Silicide layers 10 are formed on the respective surface portions of the pair of n-type semiconductor regions 8. That is, the source region and drain region of the MOSFETQ of this embodiment are composed of the n-type semiconductor region 8 and the silicide layer 10 formed on the surface portion thereof. Thus, by configuring the source region and the drain region with the n-type semiconductor region 8 and the silicide layer 10, the sheet resistance of the n-type semiconductor region 8 is about several tens (between 50 and 100) Ω / □, Since the sheet resistance of the silicide layer 10 is about several Ω / □, the resistance values of the source region and the drain region can be reduced, and the amount of current flowing between the source region and the drain region can be increased. The current gain of MOSFETQ can be increased.
[0021]
A silicide layer 10 is formed on the upper surface of the gate electrode 5. Thus, by forming the silicide layer 10 on the upper surface portion of the gate electrode 5, the sheet resistance of the gate electrode 5 made of a polycrystalline silicon film into which impurities are introduced is several tens (between 50 and 100) Ω / □. Since the sheet resistance of the silicide layer 10 is about several Ω / □, the resistance value of the gate electrode 5 can be reduced, and the operation speed of the MOSFET can be increased.
[0022]
The silicide layers 10 formed on the respective surface portions of the pair of n-type semiconductor regions 8 are formed in a self-aligned manner with respect to the sidewall spacers 9 formed on the sidewall surfaces of the gate electrode 5 in the gate length direction. . The silicide layer 10 formed on the upper surface of the gate electrode 5 is formed in a self-aligned manner with respect to the sidewall spacer 9 formed on the side wall surface of the gate electrode 5 in the gate length direction. That is, the silicide layer 10 formed on the surface portion of the n-type semiconductor region 8 and the upper surface portion of the gate electrode 5 is salicide (Salicide).SalfA ligned Silicide) Formed with technology.
[0023]
Of the pair of n-type semiconductor regions 8 which are the source region and the drain region, the silicide layer 10 formed on the surface portion of one n-type semiconductor region 8 passes through a connection hole 11A formed in the interlayer insulating film 11. The wiring 12 is electrically connected, and the silicide layer 10 formed on the surface portion of the other n-type semiconductor region 8 is electrically connected through the connection hole 11B formed in the interlayer insulating film 11. . The interlayer insulating film 11 is formed for the purpose of insulating and separating the gate electrode 5 and the wiring 12, for example, a chemical vapor deposition method (CVD: CVD).ChemicalVaporDeposition) is formed of a silicon oxide film. Since the interlayer insulating film 11 is formed at a low temperature based on the low temperature process of the semiconductor integrated circuit device, the interlayer insulating film 11 contains a large amount of hydrogen ions, hydroxide ions, and the like. The wiring 12 is formed of, for example, an aluminum film or an aluminum alloy film.
[0024]
An interlayer insulating film 13 is formed on the wiring 12. The interlayer insulating film 13 is formed for the purpose of insulating and separating the wiring 12 and the upper wiring (not shown), and is formed of, for example, a silicon oxide film formed by vapor phase chemical growth. Since the interlayer insulating film 13 is formed at a low temperature based on the low temperature process of the semiconductor integrated circuit device, similarly to the above-described interlayer insulating film 12, a large amount of hydrogen ions and hydroxide ions are formed on the interlayer insulating film 13. Etc. are included.
[0025]
A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. The nitride insulating film 4 can reduce the number of dangling bonds (dangling bonds: unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 immediately below the gate insulating film 3. The amount of hot carriers to be captured can be reduced.
[0026]
The nitride insulating film 4 is formed of a silicon oxynitride film formed by oxynitriding. This silicon oxynitride film is a silicon nitride film (Si_ThreeN_Four, SixNx) has better film quality and higher adhesion.
[0027]
A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 3 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 3. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH) and the like, hydrogen ions and water contained in the interlayer insulating film 11 and interlayer insulating film 13 are used. It is possible to prevent acid ions and the like from entering the film from the side wall surface of the gate insulating film 3.
[0028]
A nitride insulating film 7 is provided between the sidewall surface of the gate electrode 5 and the sidewall spacer 9, that is, on the sidewall surface of the gate electrode 5. Since this nitride insulating film 7 is impermeable to hydrogen ions, hydroxide ions, etc., the hydrogen ions, hydroxide ions, etc. contained in the interlayer insulating film 11 and the interlayer insulating film 13 are on the side of the gate electrode 5. It is possible to prevent the wall from penetrating through the film and entering the gate insulating film 3.
[0029]
The nitride insulating film 7 is formed of a silicon oxynitride film formed by oxynitriding or a silicon nitride film formed by vapor phase chemical growth. In this embodiment, the silicon nitride film 7 is formed of a silicon nitride film formed by vapor phase chemical growth.
[0030]
The MOSFET Q configured as described above is used as a constituent element of a CMOS inverter circuit, for example.
[0031]
Next, a method for manufacturing the MOSFET Q mounted on the semiconductor integrated circuit device will be described with reference to FIGS. 2 to 6 (cross-sectional views of main parts shown for each manufacturing process).
[0032]
First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.
[0033]
Next, an element isolation insulating film 2 made of a silicon oxide film is formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1 using a known selective oxidation method.
[0034]
Next, a thermal oxidation process is performed to form a gate insulating film 3A made of a thermal silicon oxide film on the surface of the element formation region (active region) of the p-type semiconductor substrate 1.
[0035]
Next, an oxynitriding process is performed to form a nitride insulating film 4A made of a silicon oxynitride film between the p-type semiconductor substrate 1 and the gate insulating film 3A, as shown in FIG. The oxynitride insulating film 4A is formed, for example, by performing a heat treatment at about 1000 [° C.] for about 30 minutes in a diluted nitrogen gas atmosphere or a 100% nitrogen gas atmosphere.
[0036]
Next, a polycrystalline silicon film is formed on the entire surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3A by, for example, a chemical vapor deposition method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.
[0037]
Next, the polycrystalline silicon film, the gate insulating film 3A, and the nitride insulating film 4A are sequentially patterned, and the gate insulating film is formed on the surface of the element formation region of the p-type semiconductor substrate 1 as shown in FIG. 3. A nitride insulating film 4 is formed between the gate electrode 5 and the p-type semiconductor substrate 1 and the gate insulating film 3 on the surface of the gate insulating film 3. In this step, the surface of the other element formation region except the surface of the element formation region of the p-type semiconductor substrate 1 under the gate electrode 5 is exposed.
[0038]
Next, a nitride insulating film 7 is formed on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the gate electrode 5 and the side wall surface thereof. The nitride insulating film 7 is, for example, a silicon nitride film (Si_ThreeN_Four, SixNx).
[0039]
Next, n-type impurities are introduced into the surface portion of the element formation region of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode 5 and the element isolation insulating film 2, for example, by ion implantation, and shown in FIG. In this manner, a pair of n-type semiconductor regions 8 which are a source region and a drain region are formed. In this step, since the introduction of the n-type impurity is performed through the nitride insulating film 7, physical damage to the surface of the element formation region of the p-type semiconductor substrate 1 due to the introduction of the impurity can be suppressed.
[0040]
Next, as shown in FIG. 5, sidewall spacers 9 are formed on the sidewall surfaces of the gate electrode 5 in the gate length direction. The sidewall spacer 9 is formed by forming a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the gate electrode 5 by, for example, vapor phase chemical growth, and then forming the silicon oxide film thickness and the nitride insulating film 7. The silicon oxide film and the nitride insulating film 7 are added to the RIE (corresponding to the film thickness ofReactiveIonEIt is formed by performing anisotropic etching such as tching). In this step, the upper surface of the gate electrode 5 is exposed. Further, the surface of the element formation region of the p-type semiconductor substrate 1 around the sidewall spacer 9 is exposed.
[0041]
Next, a refractory metal film 10A made of a Ti film, a W film, a Mo film, or the like is formed on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the gate electrode 5 by sputtering. In this embodiment, a Ti film is used as the refractory metal film 10A.
[0042]
Next, a low temperature heat treatment of about 500 to 600 [° C.] is performed to react each Si in the gate electrode 5 and the n-type semiconductor region 8 with Ti in the refractory metal film 10A, and as shown in FIG. A silicide layer (TiSix layer) 10 is formed on the upper surface of the electrode 5 and the surface of the n-type semiconductor region 8.
[0043]
Next, the unreacted refractory metal film 10A that has not reacted with Si is selectively removed by, for example, a wet etching method.
[0044]
Next, a high-temperature heat treatment of about 900 to 1000 [° C.] is performed to promote the reaction of the silicide layer 10 and to reduce the resistance of the silicide layer 10. By this step, the MOSFET Q is almost completed.
[0045]
Next, an interlayer insulating film 11 is formed on the entire surface of the p-type semiconductor substrate 1, a wiring 12 is formed on the interlayer insulating film 11, and an interlayer insulating film 13 is formed on the wiring 12, thereby the semiconductor shown in FIG. An integrated circuit device is formed.
[0046]
Thus, according to the present embodiment, the following effects can be obtained.
[0047]
(1) In a semiconductor integrated circuit device having a MOSFET (Field Effect Transistor) Q in which a gate electrode 5 is formed on the surface of a p-type semiconductor substrate 1 with a gate insulating film 3 interposed therebetween, the p-type semiconductor substrate 1 and the p-type semiconductor substrate 1 A nitride insulating film 4 is provided between the gate insulating film 3 and a nitride insulating film 7 is provided on the side wall surface of the gate insulating film 3.
[0048]
With this configuration, since the number of dangling bonds (dangling bonds: unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 immediately below the gate insulating film 3 can be reduced by the nitride insulating film 4, the gate insulating film The amount of hot carriers trapped in 3 can be reduced. Further, since the nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH), etc., the hydrogen ions contained in the interlayer insulating film 11 and the interlayer insulating film 13 It is possible to prevent hydroxide ions or the like from entering the film from the side wall surface of the gate insulating film 3. As a result, the temporal threshold voltage (Vth) fluctuation caused by hot carriers of the MOSFET (field effect transistor) Q can be suppressed, and the temporal threshold voltage caused by hydrogen ions, hydroxide ions, etc. Variation in (Vth) can be suppressed.
[0049]
In addition, fluctuations in threshold voltage (Vth) over time caused by hot carriers in MOSFET (field effect transistor) Q can be suppressed, and threshold voltages over time caused by hydrogen ions, hydroxide ions, etc. ( Therefore, the electrical reliability of the semiconductor integrated circuit device having the MOSFET (field effect transistor) Q can be improved.
[0050]
In addition, the MOSFET (field effect transistor) caused by hot carriers is relaxed without reducing the gradient of the impurity concentration distribution of the pn junction formed between the drain region and the channel formation region and weakening the electric field strength generated in this region. ) Since variation in threshold voltage (Vth) over time of Q can be suppressed, a part of the drain region on the side of the channel formation region is not set to a lower impurity concentration than the impurity concentration of other regions. May be. As a result, the amount of current flowing between the source region and the drain region can be increased, so that the current gain of the MOSFET (field effect transistor) Q can be increased.
[0051]
Further, since the current gain of the MOSFET (field effect transistor) Q can be increased, the operation speed of the semiconductor integrated circuit device having the MOSFET (field effect transistor) Q can be increased.
[0052]
In the present embodiment, when the source region and the drain region of the MOSFET Q are configured by the n-type semiconductor region 8 and the silicide layer 10, the electric field strength generated between the drain region and the channel formation region is strong. Since the fluctuation of the threshold voltage (Vth) over time of the MOSFET (field effect transistor) Q caused by hot carriers can be suppressed without weakening the electric field strength, the power gain of the MOSFET Q can be increased.
[0053]
(2) A nitride insulating film 7 is provided on the side wall surface of the gate electrode 5. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (-H +) and hydroxide ions (-OH), so that hydrogen ions contained in the interlayer insulating film 11 and the interlayer insulating film 13 are used. Further, it is possible to prevent hydroxide ions or the like from penetrating through the film from the side wall surface of the gate electrode 5 and entering the gate insulating film 3. As a result, fluctuations in the threshold voltage (Vth) over time due to hydrogen ions, hydroxide ions, etc. of the MOSFET (field effect transistor) Q can be further suppressed.
[0054]
In the method of manufacturing MOSFETQ mounted on the semiconductor integrated circuit device, thermal oxidation treatment or acid treatment is performed after the step of forming the gate electrode 5 and before the step of forming the nitride insulating film 7. As shown in FIG. 7, a step of forming an insulating film 6 made of a thermal silicon oxide film or a silicon oxynitride film on the upper surface of the gate electrode 5 and the side wall surface thereof may be provided. In this case, in the step of forming the gate electrode 5, the removed portion of the gate insulating film 3 removed by the side etching can be supplemented.
[0055]
The step of forming the pair of n-type semiconductor regions 8 which are the source region and the drain region is performed after the step of forming the gate electrode 5 and before the step of forming the nitride insulating film 7. May be.
[0056]
The step of forming the pair of n-type semiconductor regions 8 as the source region and the drain region is after the step of forming the sidewall spacer 9 and before the step of forming the refractory metal film 10A. You may go to
[0057]
(Example 2)
A schematic configuration of a semiconductor integrated circuit device having a MOSFET according to Embodiment 2 of the present invention is shown in FIG.
[0058]
As shown in FIG. 8, a MOSFET (field effect transistor) Q mounted on a semiconductor integrated circuit device is formed on the surface portion of an element formation region (active region) of a p-type semiconductor substrate 1 made of, for example, single crystal silicon. The The MOSFET Q is mainly composed of a p-type semiconductor substrate 1, which is a channel formation region, a gate insulating film 3, a gate electrode 5, and a pair of n-type semiconductor regions 8 which are a source region and a drain region. That is, the MOSFET Q of this embodiment is composed of a field effect transistor in which the gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween, as in the first embodiment.
[0059]
A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 3 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 3. A nitride insulating film 7 is provided between the sidewall surface of the gate electrode 5 and the sidewall spacer 9, that is, on the sidewall surface of the gate electrode 5. A nitride insulating film 7 is provided on the upper surface of the gate electrode 5. That is, the surface of the gate electrode 5 of the MOSFET Q of this embodiment is covered with the nitride insulating film 7.
[0060]
As described above, by providing the nitride insulating film 7 on the upper surface of the gate electrode 5 and on the side wall surface thereof, the nitride insulating film 7 is free from hydrogen ions (-H +), hydroxide ions (-OH), and the like. Since it has transparency, hydrogen ions, hydroxide ions, and the like contained in the interlayer insulating film 11 and the interlayer insulating film 13 permeate through the film from the upper surface and side wall surface of the gate electrode and enter the gate insulating film 3. Can be prevented. As a result, fluctuations in threshold voltage (Vth) over time due to hydrogen ions, hydroxide ions, etc. of MOSFET (field effect transistor) Q can be further suppressed.
[0061]
(Example 3)
FIG. 9 shows a schematic configuration of a semiconductor integrated circuit device having a nonvolatile memory element according to Embodiment 3 of the present invention.
[0062]
As shown in FIG. 9, a nonvolatile memory element (field effect transistor) Qe mounted on a semiconductor integrated circuit device is a surface portion of an element formation region (active region) of a p-type semiconductor substrate 1 made of, for example, single crystal silicon. Configured. The periphery of the element formation region is defined by an element isolation insulating film 2 formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1, and is insulated and isolated from other element formation regions.
[0063]
The nonvolatile memory element Qe mainly includes a p-type semiconductor substrate 1 serving as a channel formation region, a gate insulating film 3, a charge storage gate electrode (floating gate electrode) 5, a gate insulating film 14, a control gate electrode (control gate electrode). ) 15 and a pair of n-type semiconductor regions 8 which are a source region and a drain region. The gate insulating film 3 is formed on the surface of the p-type semiconductor substrate 1, and is formed of, for example, a thermal silicon oxide film. The charge storage gate electrode 5 is formed on the surface of the gate insulating film 3, and is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. The gate insulating film 14 is formed on the upper surface of the charge storage gate electrode, and is formed of, for example, a thermal silicon oxide film. The control gate electrode 15 is formed on the upper surface of the charge storage gate electrode 5 with the gate insulating film 14 interposed therebetween, and is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. That is, the nonvolatile memory element Qe is configured by a field effect transistor in which the charge storage gate electrode 5 is formed on the surface of the p-type semiconductor substrate 1 with the gate insulating film 3 interposed therebetween.
[0064]
Each of the pair of n-type semiconductor regions 8 as the source region and the drain region is formed on the surface portion of the element formation region of the p-type semiconductor substrate 1 and is self-aligned with respect to the control gate electrode 15 and the charge storage gate electrode 5. Formed with.
[0065]
Sidewall spacers 9 are formed on the side wall surfaces of the charge storage gate electrode 5 and the control gate electrode 15 in the gate length direction.
[0066]
Of the pair of n-type semiconductor regions 8 serving as the source region and the drain region, one n-type semiconductor region 8 is electrically connected to a wiring 12 through a connection hole 11 </ b> A formed in the interlayer insulating film 11. The interlayer insulating film 11 is formed for the purpose of insulating and separating the control gate electrode 15 and the wiring 12, and is formed of, for example, a silicon oxide film formed by a chemical vapor deposition method (CVD method). Since the interlayer insulating film 11 is formed at a low temperature based on the low temperature process of the semiconductor integrated circuit device, the interlayer insulating film 11 contains a large amount of hydrogen ions, hydroxide ions, and the like.
[0067]
An interlayer insulating film 13 is formed on the wiring 12. The interlayer insulating film 13 is formed for the purpose of insulating and separating the wiring 12 and the upper wiring (not shown), and is formed of, for example, a silicon oxide film formed by vapor phase chemical growth. Since the interlayer insulating film 13 is formed at a low temperature based on the low temperature process of the semiconductor integrated circuit device, similarly to the above-described interlayer insulating film 12, a large amount of hydrogen ions and hydroxide ions are formed on the interlayer insulating film 13. Etc. are included.
[0068]
A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. The nitride insulating film 4 can reduce the number of dangling bonds (dangling bonds: unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 immediately below the gate insulating film 3. The amount of hot carriers to be captured can be reduced.
[0069]
The nitride insulating film 4 is formed of a silicon oxynitride film formed by oxynitriding. This silicon oxynitride film is a silicon nitride film (Si_ThreeN_Four, SixNx) has better film quality and higher adhesion.
[0070]
A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 3 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 3. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH) and the like, hydrogen ions and water contained in the interlayer insulating film 11 and interlayer insulating film 13 are used. It is possible to prevent acid ions and the like from entering the film from the side wall surface of the gate insulating film 3.
[0071]
A nitride insulating film 7 is provided between the side wall surface of the charge storage gate electrode 5 and the side wall spacer 9, that is, on the side wall surface of the charge storage gate electrode 5. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH) and the like, hydrogen ions and water contained in the interlayer insulating film 11 and interlayer insulating film 13 are used. Acid ions or the like can be prevented from penetrating through the film from the side wall surface of the charge storage gate electrode 5 and entering the gate insulating film 3.
[0072]
A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 14 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 14. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH) and the like, hydrogen ions and water contained in the interlayer insulating film 11 and interlayer insulating film 13 are used. It is possible to prevent acid ions or the like from penetrating through the side wall surface of the gate insulating film 14 and entering the gate insulating film 3.
[0073]
A nitride insulating film 7 is provided between the sidewall surface of the control gate electrode 15 and the sidewall spacer 9, that is, on the sidewall surface of the control gate electrode 15. Since this nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH) and the like, hydrogen ions and water contained in the interlayer insulating film 11 and interlayer insulating film 13 are used. Acid ions or the like can be prevented from penetrating through the film from the side wall surface of the control gate electrode 15 and entering the gate insulating film 3.
[0074]
The nitride insulating film 7 is formed of a silicon oxynitride film formed by oxynitriding or a silicon nitride film formed by vapor phase chemical growth. In this embodiment, the silicon nitride film 7 is formed of a silicon nitride film formed by vapor phase chemical growth.
[0075]
Next, a method of manufacturing the nonvolatile memory element Qe mounted on the semiconductor integrated circuit device will be described with reference to FIGS. 10 to 13 (main part cross-sectional views shown for each manufacturing process).
[0076]
First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.
[0077]
Next, an element isolation insulating film 2 made of a silicon oxide film is formed on the surface of the element isolation region (inactive region) of the p-type semiconductor substrate 1 using a known selective oxidation method.
[0078]
Next, a thermal oxidation process is performed to form a gate insulating film 3A made of a thermal silicon oxide film on the surface of the element formation region (active region) of the p-type semiconductor substrate 1.
[0079]
Next, an oxynitriding process is performed to form a nitride insulating film 4A made of a silicon oxynitride film between the p-type semiconductor substrate 1 and the gate insulating film 3A.
[0080]
Next, a polycrystalline silicon film 5A is formed on the entire surface of the p-type semiconductor substrate 1 including the surface of the gate insulating film 3A by, for example, vapor phase chemical growth. Impurities for reducing the resistance value are introduced into the polycrystalline silicon film 5A during or after the deposition.
[0081]
Next, a gate insulating film 14A made of a silicon oxide film is formed on the surface of the polycrystalline silicon film 5A by, for example, a chemical vapor deposition method, and then the vapor insulating chemical growth method is formed on the surface of the gate insulating film 14A. A polycrystalline silicon film 15A is formed. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film 15A during or after the deposition.
[0082]
Next, as shown in FIG. 10, a mask 16 is formed on the surface of the polycrystalline silicon film 15 </ b> A that is on the surface of the element formation region of the p-type semiconductor substrate 1. The mask 16 is formed of a photoresist film, for example.
[0083]
Next, using the mask 16 as an etching mask, the polycrystalline silicon film 15A, the gate insulating film 14A, the polycrystalline silicon film 5A, the gate insulating film 3A, and the nitride insulating film 4A are sequentially patterned. 11, the gate insulating film 3 is formed on the surface of the element formation region of the p-type semiconductor substrate 1, the charge storage gate electrode 5 is formed on the surface of the gate insulating film 3, and the p-type semiconductor substrate 1 and the gate insulating film 3 are In the meantime, a gate insulating film 14 is formed on the upper surface of the nitride insulating film 4 and the charge storage gate electrode 5, and a control gate electrode 15 is formed on the surface of the gate insulating film 14. In this step, the surface of the other element formation region except the surface of the element formation region of the p-type semiconductor substrate 1 under the charge storage gate electrode 5 is exposed.
[0084]
Next, a nitride insulating film 7 is formed on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the control gate electrode 15 and its side wall surface and the side wall surface of the charge storage gate electrode 5.
[0085]
Next, n-type impurities are introduced into the surface portion of the element formation region of the p-type semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode 5 and the element isolation insulating film 2, for example, by ion implantation, and shown in FIG. In this manner, a pair of n-type semiconductor regions 8 which are a source region and a drain region are formed. In this step, since the introduction of the n-type impurity is performed through the nitride insulating film 7, physical damage to the surface of the element formation region of the p-type semiconductor substrate 1 due to the introduction of the impurity can be suppressed.
[0086]
Next, as shown in FIG. 13, side wall spacers 9 are formed on the side wall surfaces of the charge storage gate electrode 5 and the control gate electrode 15 in the gate length direction. The sidewall spacer 9 is formed by forming a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 including the upper surface of the control gate electrode 15 by, for example, a vapor phase chemical growth method, The silicon oxide film and the nitride insulating film 7 are added to the RIE (corresponding to the film thickness of 7).ReactiveIonEIt is formed by performing anisotropic etching such as tching). In this step, the upper surface of the control gate electrode 15 is exposed. Further, the surface of the element formation region of the p-type semiconductor substrate 1 around the sidewall spacer 9 is exposed. By this step, the nonvolatile memory element Qe is almost completed.
[0087]
Next, an interlayer insulating film 11 is formed on the entire surface of the p-type semiconductor substrate 1, a wiring 12 is formed on the interlayer insulating film 11, and an interlayer insulating film 13 is formed on the wiring 12, whereby the semiconductor shown in FIG. An integrated circuit device is formed.
[0088]
Thus, according to the present embodiment, the following effects can be obtained.
[0089]
(1) In a semiconductor integrated circuit device having a nonvolatile memory element (field effect transistor) Qe in which a charge storage gate electrode 5 is formed on a surface of a p-type semiconductor substrate 1 with a gate insulating film 3 interposed therebetween, the p-type A nitride insulating film 4 is provided between the semiconductor substrate 1 and the gate insulating film 3, and a nitride insulating film 7 is provided on the side wall surface of the gate insulating film 3.
[0090]
With this configuration, since the number of dangling bonds (dangling bonds: unpaired electrons) existing on the surface of the p-type semiconductor substrate 1 immediately below the gate insulating film 3 can be reduced by the nitride insulating film 4, the gate insulating film The amount of hot carriers trapped in 3 can be reduced. Further, since the nitride insulating film 7 is impermeable to hydrogen ions (-H +), hydroxide ions (-OH), etc., the hydrogen ions contained in the interlayer insulating film 11 and the interlayer insulating film 13 It is possible to prevent hydroxide ions or the like from entering the film from the side wall surface of the gate insulating film 3. As a result, fluctuations in the threshold voltage (Vth) over time due to hot carriers in the nonvolatile memory element (field effect transistor) Qe can be suppressed, and time-lapse due to hydrogen ions, hydroxide ions, etc. can be suppressed. Variations in threshold voltage (Vth) can be suppressed.
[0091]
In addition, the temporal threshold voltage (Vth) fluctuation caused by hot carriers of the nonvolatile memory element (field effect transistor) Qe can be suppressed, and the temporal threshold caused by hydrogen ions, hydroxide ions, etc. Since fluctuations in the value voltage (Vth) can be suppressed, electrical characteristics such as data write characteristics, data erase characteristics, and data retention characteristics can be stabilized.
[0092]
In addition, fluctuations in threshold voltage (Vth) over time caused by hot carriers in MOSFET (field effect transistor) Q can be suppressed, and threshold voltages over time caused by hydrogen ions, hydroxide ions, etc. ( Therefore, the electrical reliability of the semiconductor integrated circuit device having the nonvolatile memory element (field effect transistor) Qe can be improved.
[0093]
In addition, a nonvolatile memory element (due to hot carriers) is generated without reducing the gradient of the impurity concentration distribution in the pn junction formed between the drain region and the channel formation region and weakening the electric field strength generated in this region. (Field effect transistor) Since it is possible to suppress the variation of the threshold voltage (Vth) over time of Qe, a part of the drain region on the channel formation region side has a lower impurity concentration than the impurity concentration of other regions. It is not necessary to set. As a result, since the amount of current flowing between the source region and the drain region can be increased, the current gain of the nonvolatile memory element (field effect transistor) Qe can be increased.
[0094]
In addition, since the current gain of the nonvolatile memory element (field effect transistor) Qe can be increased, the operating speed of the semiconductor integrated circuit device having the nonvolatile memory element (field effect transistor) Qe can be increased.
[0095]
(2) A nitride insulating film 7 is provided on the side wall surface of the charge storage gate electrode 5. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (—H +), hydroxide ions (—OH), etc., so that the hydrogen contained in the interlayer insulating film 11 and the interlayer insulating film 13 It is possible to prevent ions, hydroxide ions, and the like from penetrating through the film from the side wall surface of the charge storage gate electrode 5 and entering the gate insulating film 3. As a result, it is possible to further suppress the variation of the threshold voltage (Vth) over time due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.
[0096]
(3) The nitride insulating film 7 is provided on the side wall surface of the gate insulating film 14. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (—H +), hydroxide ions (—OH), etc., so that the hydrogen contained in the interlayer insulating film 11 and the interlayer insulating film 13 It is possible to prevent ions, hydroxide ions, etc. from penetrating through the side wall surface of the gate insulating film 14 and entering the gate insulating film 3. As a result, it is possible to further suppress the variation of the threshold voltage (Vth) with time due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.
[0097]
(4) The nitride insulating film 7 is provided on the side wall surface of the control gate electrode 15. With this configuration, the nitride insulating film 7 is impermeable to hydrogen ions (—H +), hydroxide ions (—OH), etc., so that the hydrogen contained in the interlayer insulating film 11 and the interlayer insulating film 13 It is possible to prevent ions, hydroxide ions, and the like from penetrating through the film from the side wall surface of the control gate electrode 15 and entering the gate insulating film 3. As a result, it is possible to further suppress the variation of the threshold voltage (Vth) over time due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.
[0098]
  Of the present inventionReference exampleA schematic configuration of a semiconductor integrated circuit device having a nonvolatile memory element is shown in FIG.
[0099]
  As shown in FIG. 14, the semiconductor integrated circuit deviceTowerThe mounted non-volatile memory element (field effect transistor) Qe is formed on the surface portion of the element formation region (active region) of the p-type semiconductor substrate 1 made of, for example, single crystal silicon. The nonvolatile memory element Qe mainly includes a p-type semiconductor substrate 1, which is a channel formation region, a gate insulating film 3, a charge storage gate electrode 5, a gate insulating film 14, a control gate electrode 15, a pair of source and drain regions. N-type semiconductor region 8. That is, bookReference exampleThe non-volatile memory element Qe is composed of a field effect transistor in which a gate electrode 5 is formed on the surface of a p-type semiconductor substrate 1 with a gate insulating film 3 interposed, as in the third embodiment.
[0100]
  A nitride insulating film 4 is provided between the p-type semiconductor substrate 1 and the gate insulating film 3. A nitride insulating film 7 is provided between the side wall surface of the gate insulating film 3 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 3. A nitride insulating film 7 is provided between the sidewall surface of the gate electrode 5 and the sidewall spacer 9, that is, on the sidewall surface of the gate electrode 5. A nitride insulating film 7 is provided between the side surface of the gate insulating film 14 and the side wall spacer 9, that is, on the side wall surface of the gate insulating film 14. A nitride insulating film 7 is provided between the side wall surface of the control gate electrode 15 and the side wall spacer 9, that is, on the side wall surface of the control gate electrode 15. A nitride insulating film 7 is provided on the upper surface of the control gate electrode 15. That is, bookReference exampleNonvolatile memory element QeThe surface of the control gate electrode 15 is covered with the nitride insulating film 7.
[0101]
Thus, by providing the nitride insulating film 7 on the upper surface and the side wall surface of the control gate electrode 5, the nitride insulating film 7 is resistant to hydrogen ions (-H +), hydroxide ions (-OH), and the like. Since it has non-permeability, hydrogen ions, hydroxide ions, and the like contained in the interlayer insulating film 11 and the interlayer insulating film 13 permeate through the film from the upper surface and the side wall surface of the control gate electrode 15, and the gate insulating film 3 Intrusion can be prevented. As a result, it is possible to further suppress the variation of the threshold voltage (Vth) with time due to hydrogen ions, hydroxide ions, etc. of the nonvolatile memory element (field effect transistor) Qe.
[0102]
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.
[0103]
For example, the present invention can be applied to a semiconductor integrated circuit device having a field effect transistor in which a source region and a drain region are constituted by a pair of p-type semiconductor regions.
[0104]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0105]
In a semiconductor integrated circuit device having a field effect transistor in which a gate electrode is formed on a surface of a semiconductor substrate with a gate insulating film interposed, a threshold voltage (Vth) over time caused by hot carriers of the field effect transistor The fluctuation can be suppressed, and the fluctuation of the threshold voltage (Vth) with time due to hydrogen ions, hydroxide ions, or the like can be suppressed.
[0106]
In addition, the current gain of the field effect transistor can be increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device having a MOSFET (field effect transistor) that is Embodiment 1 of the present invention.
FIG. 2 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 3 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 4 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 5 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 6 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 7 is a fragmentary cross-sectional view for illustrating the method for manufacturing the MOSFET.
FIG. 8 is a cross-sectional view of a principal part of a semiconductor integrated circuit device having a MOSFET (field effect transistor) which is Embodiment 2 of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor integrated circuit device having a nonvolatile memory element (field effect transistor) that is Embodiment 3 of the present invention.
10 is a fragmentary cross-sectional view for illustrating the method of manufacturing the nonvolatile memory element. FIG.
11 is a fragmentary cross-sectional view for illustrating the method of manufacturing the nonvolatile memory element. FIG.
FIG. 12 is a fragmentary cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.
FIG. 13 is a fragmentary cross-sectional view for illustrating the method for manufacturing the nonvolatile memory element.
FIG. 14 shows the present invention.Reference exampleFIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device having a nonvolatile memory element (field effect transistor) that is.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4 ... Nitride insulating film, 5 ... Gate electrode, charge storage gate electrode, 6 ... Insulating film, 7 ... Nitride insulating film, 8 ... n-type semiconductor region, 9 ... sidewall spacer, 10 ... silicide layer, 11, 13 ... interlayer insulating film, 11A, 11B ... connection hole, 12 ... wiring, 14 ... gate insulating film, 15 ... control gate electrode, 16 ... mask .

Claims (7)

In a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed therebetween,
Side wall spacers made of a silicon oxide film are provided on both sides of the gate electrode in the gate length direction,
Providing a first nitride insulating film between the semiconductor substrate and the gate insulating film;
A second silicon nitride film is provided between the gate electrode, the gate insulating film , the first nitride insulating film, and the semiconductor substrate and the sidewall spacer;
The second silicon nitride film is formed on a side wall surface of the gate insulating film ;
A pair of semiconductor regions that are self-aligned with the gate electrode to form a source region and a drain region are formed in the semiconductor substrate
A semiconductor integrated circuit device, wherein an interlayer insulating film is formed on the entire surface of the semiconductor substrate . In a semiconductor integrated circuit device having a field effect transistor having a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film interposed therebetween,
Side wall spacers made of a silicon oxide film are provided on both sides of the gate electrode in the gate length direction,
Providing a first nitride insulating film between the semiconductor substrate and the gate insulating film;
Said gate electrode, said gate insulating film, a second silicon nitride film between the first nitride insulating film and the semiconductor substrate and the sidewall spacers provided,
The second silicon nitride film is formed on a side wall surface of the gate insulating film;
A pair of semiconductor regions that are self-aligned with the gate electrode to form a source region and a drain region are formed in the semiconductor substrate
Shi Risaido layer is formed on the surface portion of the not covered with the second silicon nitride film of the semiconductor area formed in a surface portion of the semiconductor substrate,
A semiconductor integrated circuit device, wherein an interlayer insulating film is formed on the entire surface of the semiconductor substrate . In the semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the second silicon nitride film is a film formed by vapor phase chemical growth. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The semiconductor integrated circuit device, wherein the first nitride insulating film is formed of a silicon oxynitride film formed by performing an oxynitriding process after forming the gate insulating film . In a method for manufacturing a semiconductor integrated circuit device having a field effect transistor,
A gate electrode is formed by interposing a first nitride insulating film and a gate insulating film in this order on the surface of the semiconductor substrate, and the surface of the element forming region excluding the surface of the element forming region of the semiconductor substrate under the gate electrode Exposing the step,
Forming a second silicon nitride film on the entire surface of the semiconductor substrate, and covering a side wall surface of the gate insulating film with the second silicon nitride film;
Forming a pair of semiconductor regions to be a source region and a drain region in self-alignment with the gate electrode;
Forming a silicon oxide film on the entire surface of the semiconductor substrate;
By performing anisotropic etching on the second silicon nitride film and the silicon oxide film, the second silicon nitride film and the silicon nitride film are interposed between the gate electrode , the gate insulating film , the first nitride insulating film, and the semiconductor substrate . Forming a sidewall spacer made of the silicon oxide film with a silicon nitride film interposed therebetween;
And a step of forming an interlayer insulating film on the entire surface of the semiconductor substrate. In a method for manufacturing a semiconductor integrated circuit device having a field effect transistor,
A gate electrode is formed by interposing a first nitride insulating film and a gate insulating film in this order on the surface of the semiconductor substrate, and the surface of the element forming region excluding the surface of the element forming region of the semiconductor substrate under the gate electrode Exposing the step,
Forming a second silicon nitride film on the entire surface of the semiconductor substrate, and covering a side wall surface of the gate insulating film with the second silicon nitride film;
Forming a pair of semiconductor regions to be a source region and a drain region in self-alignment with the gate electrode;
Forming a silicon oxide film on the entire surface of the semiconductor substrate;
By performing anisotropic etching on the second silicon nitride film and the silicon oxide film, the second nitride is interposed between the gate electrode , the gate insulating film , the first nitride insulating film, and the semiconductor substrate. Forming a sidewall spacer made of the silicon oxide film with a silicon film interposed therebetween;
Forming a silicide layer on a surface portion of the semiconductor region exposed by the anisotropic etching;
And a step of forming an interlayer insulating film on the entire surface of the semiconductor substrate. In the manufacturing method of the semiconductor integrated circuit device according to claim 5,
A method of manufacturing a semiconductor integrated circuit device, wherein the second silicon nitride film and the silicon oxide film are formed by vapor phase chemical growth.

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