JPH09320887A - Laminated ceramic capacitor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stray capacity caused by a protective layer, by making dielectric constant of, at least, the outermost layer out of protective layers lower than that of a dielectric layer sandwiched by inner electrode layers. SOLUTION: A specified number of first sheets 4a, whose dielectric constant after the sintering is ε1 , are laminated, and a first dielectric layer 5a of a lower part is formed. Second sheets 4b for dielectric layers, whose dielectric constant after sintering is ε2 and inner electrodes 2a, alternately laminated, and an effective part 5b is formed. The first sheets 4a are laminated, and a first dielectric layer 5c of an upper part is formed. The ratio of the dielectric constant ε1 of the first dielectric layer 5a to the dielectric constant ε2 of the effective part 5b satisfies ε1 /ε2 <1.1. Thereby mass production of laminated ceramic capacitors is enabled with high capacity precision, and creeping discharge resistance characteristics of an element surface are improved conspicuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a method of manufacturing a laminated ceramic capacitor, first, a ceramic dielectric material, a resin binder, a plasticizer, etc. are mixed to form a slurry, and a ceramic green sheet (hereinafter referred to as a sheet Then, the internal electrode layer 2a is formed on the sheet by a screen printing method while forming the internal electrode layer each time, as shown in the sectional view of FIG. The sheets are stacked so as to be alternately displaced and pressed to each other, then cut into chips having a desired shape, and the obtained laminated body is fired. After that, a method of forming the external electrodes 3 on both ends of the sintered body and connecting to the internal electrode layers 2a is generally performed. At this time, the sheets to be laminated are
Dielectric layer 1 and internal electrode layer 2 sandwiched between internal electrode layers 2a
The dielectric layer 1 which is not sandwiched between a is usually formed by using the same sheet.

On the other hand, in recent years, the movement of ceramic capacitors for medium and high voltage into multilayer chips has become popular. In a medium-high voltage monolithic ceramic capacitor, in order to improve the withstand voltage, an internal electrode layer 2b (hereinafter referred to as a counter electrode) whose end is connected to an external electrode 3 as shown in the cross-sectional view of FIG. And the internal electrode layers 2c (hereinafter, referred to as floating electrodes) whose ends are not connected to the external electrode 3 and overlap with the counter electrodes 2b are alternately arranged with the dielectric layer 1 interposed therebetween. A general method is to use a series-parallel type laminated structure in which the electric field strength applied per layer is halved in terms of an equivalent circuit. Also in this case, the sheets to be laminated are usually formed by using the same sheet for the marginal portions above and below the element and for the effective portion related to the capacitance of the capacitor.

[0004]

Generally, the monolithic ceramic capacitors are roughly classified into those for temperature compensation and those for high permittivity, but most of the former are products requiring high capacitance accuracy. For this reason, it is the current situation that the improvement of the capacity hit rate for accurately realizing a desired capacity value in mass production is an important issue in manufacturing. However, in the configuration described above, stray capacitance is generated due to the dielectric layers that are not sandwiched between the upper and lower internal electrode layers 2a, and it is very difficult to read this value. Causing a decline.

On the other hand, in a medium- and high-voltage monolithic ceramic capacitor, it is basically assumed that the element is not resin-molded and is used as it is. Therefore, the creeping discharge resistance characteristic of the element surface during use is It has become an important issue for quality.

In view of the above problems, it is an object of the present invention to improve the capacity hit rate in a temperature-compensating multilayer ceramic capacitor and to improve the creeping discharge resistance in a medium-high voltage multilayer ceramic capacitor. To do.

[0007]

In order to achieve this object, a monolithic ceramic capacitor of the present invention comprises a laminated body in which dielectric layers and internal electrode layers are laminated alternately, and on both upper and lower surfaces of this laminated body. A ceramic sintered body having a protective layer provided, and an external electrode provided on the exposed end surface of the internal electrode layer of the ceramic sintered body, the relative dielectric constant of at least the outermost layer of the protective layer, The dielectric constant is smaller than the relative dielectric constant of the dielectric layer sandwiched between the internal electrode layers.

Generally, the creeping discharge voltage V on the ceramic surface
Is the surface specific capacitance C, the interelectrode distance L, and the proportional constant α
Then, it is roughly expressed as follows. (See, for example, Discharge Handbook [edited by the Institute of Electrical Engineers] P227) V = α · L ^m / C ^l (0 <l <1,0 <m <1) Here, the specific capacitance C is proportional to the relative permittivity ε of the ceramic. As a result, the creeping discharge voltage V is inversely proportional to ε when L is constant. Therefore, with the above structure, the relative permittivity of at least the outermost layer of the protective layer is made smaller than the relative permittivity of the dielectric layer sandwiched by the internal electrode layers, so that the creepage discharge does not affect the capacity acquisition of the capacitor. The starting voltage (hereinafter referred to as FOV) can be improved.

At the same time, by lowering the relative permittivity of at least the outermost layer of the protective layer, the stray capacitance due to the protective layer is reduced, and the actual capacitance of the capacitor is almost only from the design dimension of the effective portion. It is possible to calculate a correct value and improve the capacity hit rate during mass production.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention comprises a laminated body in which dielectric layers and internal electrode layers are alternately laminated, and protective layers provided on both upper and lower surfaces of the laminated body. A ceramic sintered body having, and an external electrode provided on the exposed end surface of the internal electrode layer of the ceramic sintered body, the relative dielectric constant of at least the outermost layer of the protective layer, in the internal electrode layer A monolithic ceramic capacitor characterized in that it is smaller than the non-dielectric constant of the sandwiched dielectric layer,
It has the effect of improving FOV and capacity hit rate.

According to the second aspect of the invention, when the relative dielectric constant of at least the outermost layer of the protective layer is ε ₁ and the relative dielectric constant of the dielectric layer is ε ₂ , ε ₂ / ε ₁ ≧ 1.1 The multilayer ceramic capacitor according to claim 1, wherein
It provides a preferable condition for the effect of improving V.

According to a third aspect of the invention, the internal electrode layer is
A first internal electrode layer in which at least two electrodes face each other with a constant distance in the same plane, and one ends of which are connected to different external electrodes; The multilayer ceramic capacitor according to claim 1, further comprising a second internal electrode layer that is provided so as to overlap with the first internal electrode layer with a dielectric layer interposed therebetween. It has the effect of improving the hit rate.

According to a fourth aspect of the invention, when the thickness of at least the outermost layer of the protective layer is t1 and the thickness of the dielectric layer is t2, 1 ≦ t ₁ / t ₂ ≦ 4 is satisfied. The laminated ceramic capacitor described above can improve the integral sinterability of the protective layer and the dielectric layer.

According to a fifth aspect of the present invention, a step of laminating a desired number of first ceramic sheets to form a lower first dielectric layer, and then a second dielectric layer on the first dielectric layer are provided. A step of obtaining a first laminated body by alternately laminating dielectric layers and internal electrode layers so as to have a desired number of laminated layers, and laminating a desired number of the first ceramic sheets on the first laminated body. Forming an upper first dielectric layer to obtain a second laminated body, and thereafter, cutting the second laminated body into a chip having a desired shape, and then firing the chip, and then forming an end face of the chip. And a step of forming an external electrode, wherein the relative dielectric constant of the first dielectric layer is smaller than the relative dielectric constant of the second dielectric layer, and a FOV is improved. It also has the effect of improving the capacity hit rate.

According to a sixth aspect of the present invention, the shrinkage rate of the first dielectric layer upon firing is S ₁ (%) and the shrinkage rate of the second dielectric layer upon firing is S ₂ (%). Then, | S ₁ −S ₂ | ≦
The laminated ceramic capacitor manufacturing method according to claim 5, wherein the dielectric layer having a thickness of 3.0 is used, and the integral sinterability of the protective layer and the dielectric layer can be improved.

According to a seventh aspect of the present invention, there is provided a laminated ceramic capacitor according to the fifth aspect, wherein at least one adhesive sheet is provided between the first dielectric layer and the second dielectric layer. The method has a function of strengthening the fixing force between the protective layer and the dielectric layer.

According to an eighth aspect of the present invention, the adhesive sheet has a shrinkage ratio between at least the shrinkage ratio of the first dielectric layer and the shrinkage ratio of the second dielectric layer. 7
Which is a method for manufacturing the multilayer ceramic capacitor described in
It is possible to improve the integral sinterability of the protective layer and the dielectric layer.

According to a ninth aspect of the present invention, in the method for producing a laminated ceramic capacitor according to the seventh aspect, the adhesive sheet has a higher adhesiveness than the first dielectric layer and the second dielectric layer. It has an effect of strengthening the fixing force between the protective layer and the dielectric layer.

According to a tenth aspect of the present invention, a step of alternately laminating second dielectric layers and internal electrode layers to form a first laminated body, and the internal electrode of the first laminated body Forming a second laminated body by pressure-bonding the first dielectric layer to the non-exposed surface of the layer, and firing the second laminated body, and then applying an external electrode to the exposed end surface of the internal electrode layer. Has a forming step,
A method of manufacturing a monolithic ceramic capacitor in which the relative permittivity of the first dielectric layer is smaller than that of the second dielectric layer, and has the effect of improving FOV and capacitance hit rate. Have.

According to an eleventh aspect of the present invention, a step of forming a prismatic laminated body by alternately laminating second dielectric layers and internal electrode layers, and using this laminated body as a first dielectric layer. A step of press-fitting into a square tube formed using to obtain a sintered body by firing,
A step of forming an external electrode on the exposed end surface of the internal electrode layer of the sintered body, wherein the relative dielectric constant of the first dielectric layer is higher than that of the second dielectric layer. It is a manufacturing method of a reduced monolithic ceramic capacitor, and has an effect of improving FOV and capacity hit rate.

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing an example of a method of laminating a monolithic ceramic capacitor according to the present invention for a single element. First, a predetermined number of first sheets 4a having a relative permittivity of ε ₁ after sintering are laminated to form a first dielectric layer 5a at the bottom, and subsequently, a relative permittivity of ε ₂ after sintering is ε _2. The second sheet 4b for the second dielectric layer and the internal electrode layer 2a
Alternately, the effective portion 5b for obtaining the electrostatic capacitance is produced, and when the desired number of stacked layers is completed, the first sheet 4a is formed.
5 shows a stacking step of stacking a predetermined number of layers to form the upper first dielectric layer 5c.

At this time, the first and second sheets 4a,
In 4b, the dielectric material is slurried and then formed on a carrier film by a reverse roll coater. The internal electrode layer 2a is usually formed by a screen printing method, but when forming the internal electrode layer 2a, a method of repeating printing and laminating each time when laminating, or a second sheet 4b in which the internal electrode layer 2a is formed in advance is used.
There are various methods such as a method of superposing them, but the present invention is not particularly limited thereto. Further, the first dielectric layer 5a,
It is preferable that 5c has the same thickness in consideration of sinterability. In addition, in FIG. 1, the pattern of the internal electrode layer 2a has a general parallel type configuration shown in FIG.
It is needless to say that also in the production of the medium-high voltage capacitor having the floating electrode 2c shown in FIG. 7, the same lamination method can be obtained only by changing the pattern of the internal electrode layer 2a.

The above-mentioned lamination process is usually carried out with a green sheet of a predetermined size obtained from a plurality of elements, and after the lamination is completed, the obtained laminated molded body is cut into desired chips and the organic binder is placed in an electric furnace. After degreasing, 1200-1
It is fired at 300 ° C. to obtain a sintered body. Next, the external electrode 3 containing silver as a main component is formed on the end surface of the obtained sintered element where the internal electrode layer 2a is exposed by baking to produce a laminated ceramic capacitor.

In this embodiment, the upper and lower first
As the first sheet 4a provided for the dielectric layers 5a and 5c, and the sheet having a relative dielectric constant ε ₁ of 50 after sintering as the second sheet 4b provided for the effective portion 5b. A sheet with a relative permittivity ε ₂ of 100 and a thickness of 50 μm is used, the element shape is 3216 type, and the capacitance is 100 p.
After designing the area of the internal electrode layers 2a and the number of laminated layers so as to be F, a laminated ceramic capacitor was produced by the above-described method.

As a comparative example, the relative dielectric constant ε ₂ after sintering
A multilayer ceramic capacitor was manufactured in the same manner as above using only the second sheet 4b having a value of 100.

The initial capacitance was measured for each of the two types of monolithic ceramic capacitors thus obtained, and the results are shown in (Table 1).

[0027]

[Table 1]

As can be seen from Table 1, the product of the present invention realizes the desired capacitance value of 100 pF almost faithfully and has a very small variation.
It can be seen that in the comparative example, the capacitance value is large overall. That is, in the product of the present invention, the first dielectric layers 5a, 5c
It is shown that the influence of the stray capacitance caused by is canceled out, and the initial design value considering only the effective portion 5b of the capacitor is almost obtained.

(Embodiment 2) Next, as shown in the sectional view of FIG. 10, a series-parallel type laminated structure in which opposed electrodes 2b and floating electrodes 2c are alternately arranged with a dielectric layer 1 in between is shown. Similar investigations were conducted for the medium- and high-voltage monolithic ceramic capacitors.

Basically, the above-mentioned first and second sheets 4a and 4b are used. At this time, in order to obtain a high withstand voltage, the second dielectric layer is formed by stacking three second sheets 4b per layer. used. In the multilayer ceramic capacitor of the present embodiment, the internal electrode layer structure is designed in a predetermined shape (not shown) so that the element shape is 4520 type and the electrostatic capacitance is 82 pF, and the number of stacked layers is adjusted, A monolithic ceramic capacitor was produced in the same manner as in Form 1. As a comparative example, a laminated ceramic capacitor having the same specifications was produced using only the second sheet 4b having a relative dielectric constant ε ₂ of 100 after sintering.

For each of the two types of monolithic ceramic capacitors thus obtained, the initial capacitance and FO
V was measured and the results are shown in (Table 2).

[0032]

[Table 2]

As is clear from (Table 2), the product of the present invention realizes the desired capacitance value of 82 pF almost faithfully,
Also, it can be seen that the capacitance value is large as a whole in the comparative example, while the variation is very small.
Further, in the product of the present invention, the FOV value is obviously improved as compared with the comparative example. That is, it was confirmed that the above-described effects of the present invention can be reliably obtained even in a medium- and high-voltage type capacitor in which the internal electrode layers have a series-parallel structure.

(Third Embodiment) Although the basic effects of the present invention have been confirmed in the first and second embodiments, the present embodiment will exemplify preferable conditions for embodying the present invention.

Since the main point of the present invention is to integrally sinter two kinds of materials having different relative permittivities, the relative ratio of the relative permittivity at which the effect of the present invention is exerted and the effective portion 5b. It is necessary to select conditions for ensuring the mechanical strength of the element body at the interface with the first dielectric layer 5a.

Therefore, the relative ratio of the relative permittivity, the difference in the contraction rate during sintering of the first dielectric layer 5a and the effective portion 5b, the first
Under various conditions with respect to the respective thickness ratios of the dielectric layer 5a and the second dielectric layer, a multilayer ceramic capacitor was manufactured in the same manner as above, and the optimum conditions were examined. The multilayer ceramic capacitor used for the examination had the same specifications as those of the second embodiment.

For each of the 100 obtained various samples, first, the relative ratio (ε ₂ / ε ₁ ) of the relative permittivity was measured by FOV, and then the number of structural defects generated by observing the cross section of the device. According to the bending strength test, the difference (| S ₁ −S ₂ |) between the optimum shrinkage ratios when the shrinkage ratios of the first dielectric layer 5a and the effective portion 5b are S ₁ and S ₂ (%), respectively, and The optimum value of the thickness ratio (t ₁ / t ₂ ) was obtained when the thicknesses of the first dielectric layer 5a and the second dielectric layer were t ₁ and t ₂ , respectively. The above results are summarized (Table 3), (Table 4),
The results are shown in (Table 5).

[0038]

[Table 3]

[0039]

[Table 4]

[0040]

[Table 5]

As can be seen from Table 3, the relative permittivity of the first dielectric layer 5a is ε ₁ and the relative permittivity of the effective portion 5b is ε _2.
In that case, the ratio is preferably ε ₂ / ε ₁ ≧ 1.1.

Next, as can be seen from (Table 4), the first
When the contraction rate of the dielectric layer 5a is S ₁ (%) and the contraction rate of the effective portion 5b is S ₂ (%), the difference in contraction rate is | S ₁ −S
₂ | ≦ 3.0 is preferable.

Finally, as can be seen from (Table 5), the first
The thickness of the dielectric layer 5a is t ₁ , and the thickness of the second dielectric layer 5b is 1
When the thickness per layer is t ₂ , the thickness ratio is 1 ≦ t ₁ /
It can be seen that t ₂ ≦ 4 is preferable.

The best condition is that these three conditions are satisfied at the same time. However, if the mechanical strength is at a level where there is no practical problem, the relative permittivity of the dielectric constant can be maximized in order to maximize the effects of the present invention. It suffices to select the conditions in a manner that emphasizes the relative ratio.

(Embodiment 4) In this embodiment, a manufacturing method for the purpose of improving the mechanical strength of the element body at the interface between the effective portion 5b and the first dielectric layer 5a will be described. .

FIG. 2 is a diagram showing an example of a single element as an example of a method for laminating a monolithic ceramic capacitor according to the present invention. First, a predetermined number of first sheets 4a having a relative dielectric constant of ε ₁ after sintering are laminated to form a lower first dielectric layer 5a.
And then the first or second sheet 4a, 4b
The amount of the resin binder in the sheet is increased as compared with that of, that is, the third sheet 4c having a higher adhesiveness than the first or second sheets 4a and 4b is interposed and laminated, and The second sheets 4b having a relative permittivity of ε ₂ after sintering and the internal electrode layers 2a are alternately laminated to form an effective portion 5b for obtaining a capacitance, and the desired number of layers is completed. At that time, one third sheet 4c is interposed and laminated,
Finally, a predetermined number of the first sheets 4a are stacked and the upper first
2 shows a stacking step for producing the dielectric layer 5c.

Here, the first and second sheets 4a and 4b used in the first embodiment are used, and a sheet obtained by increasing the binder amount by 10% in the first sheet 4a is manufactured as the third sheet 4c. , Used as an adhesive sheet.
The specifications of the monolithic ceramic capacitor and other manufacturing methods were exactly the same as in the first embodiment.

The bending strength of the device was measured for 100 monolithic ceramic capacitors thus obtained. At this time, the invention product manufactured in the first embodiment, that is, without using an adhesive sheet between the first dielectric layers 5a and 5c and the effective portion 5b, only uses the first and second sheets 4a and 4b. The same measurement was performed using a laminated ceramic capacitor as a comparative example. The results are shown in (Table 6).

[0049]

[Table 6]

As is clear from this (Table 6), the bending strength of the product of the present invention was higher than that of the comparative example, and the mechanical properties were successfully improved.

In the present embodiment, the adhesive sheet is the third sheet 4c in which the binder amount is increased by 10% in the first sheet 4a, but the first and second sheets 4a, A sheet having a higher tackiness than 4b may be a sheet that does not include a dielectric material but includes only adhesive elements such as a plasticizer and a binder.

(Fifth Embodiment) In this embodiment, in addition to the fourth embodiment, the first dielectric layers 5a and 5c and the effective portion 5 are formed.
A manufacturing method for improving the mechanical strength of the element body at the interface with b will be described.

FIG. 3 is an explanatory view thereof, but the basic configuration is exactly the same as that of FIG. 2 except that it is between the upper and lower first dielectric layers 5a and 5c and the effective portion 5b. First as a main component of the third sheet 4d for adhesion to be interposed in
In addition, the dielectric materials having different relative dielectric constants after sintering, which are included in the second sheets 4a and 4b, are mixed at an appropriate ratio.

Here, the first and second sheets 4a and 4b used in the first embodiment are used, and the relative dielectric constant after sintering which is provided to the first sheet 4a as the third sheet 4d is ε.
_The dielectric material to be ₁ and the dielectric material to be used for the second sheet 4b and having a relative dielectric constant of ε ₂ after sintering are in a weight ratio of 1: 1.
The third sheet 4 produced by mixing so that the binder amount and other configurations are set to be exactly the same as those of the first sheet 4a.
d was used as an adhesive sheet. The specifications and manufacturing method of the monolithic ceramic capacitor were exactly the same as in the first embodiment.

The bending strength of the device was measured for 100 monolithic ceramic capacitors thus obtained. At this time, the invention product manufactured in the first embodiment, that is, the first dielectric layers 5a and 5c and the effective portion 5b are not laminated by using an adhesive layer and are laminated only by the first and second sheets 4a and 4b. The same measurement was performed using the laminated ceramic capacitor obtained as above as a comparative example. The results are shown in (Table 7).

[0056]

[Table 7]

As is clear from this (Table 7), in the product of the present invention, the bending strength was increased as compared with the comparative example, and the mechanical properties were successfully improved.

The mixing ratio of the dielectric material of the adhesive sheet is such that the relative permittivity after sintering is that of the first and second sheets 4.
Any mixing may be performed as long as it has a value between the relative dielectric constants of a and 4b after sintering.

In Embodiments 4 and 5, one adhesive sheet is used between the first dielectric layers 5a and 5c and the effective portion 5b, but a plurality of adhesive sheets may be used.

(Embodiment 6) FIG. 4 is a diagram showing an outline of a method for manufacturing a monolithic ceramic capacitor according to the present invention for a single element.

First, using the second sheet 4b and the internal electrode layer 2a having a relative dielectric constant ε ₂ of 100 after sintering, the edge of the internal electrode layer 2a opposite to the side connected to the external electrode 3 is used. The effective portion 5d is manufactured by the stacking method described in the first embodiment or the like so that the three edges other than the above are exposed.

Separately, a predetermined number of first sheets 4a having a relative dielectric constant ε ₁ of 50 after sintering are laminated to form a laminated molded body for forming a first dielectric layer (see FIG. (Not shown), and then the first dielectric layer is cut into rectangular plates 5e by cutting the laminated molded body into dimensions corresponding to the upper, lower and side surfaces of the effective portion 5d, and then as shown in FIG. Effective part 5d
Except for the end surface where the external electrode 3 is to be formed, the upper surface, the lower surface and the side surface are respectively crimped and integrated as shown in FIG. The subsequent manufacturing method is exactly the same as the method described in the first embodiment.

In this manufacturing method, the first dielectric layer 5e is used not only on the end surface of the effective portion 5d where the external electrode 3 is to be formed, but also on the lower surface and the side surface, so that the dielectric constant can be lowered. Therefore, the effect of the present invention can be further exerted.

(Embodiment 7) FIGS. 6, 7 and 8 are views showing an outline of a method for manufacturing a monolithic ceramic capacitor according to the present invention for a single element.

First, similar to the sixth embodiment, only the effective portion 5d for obtaining the electrostatic capacitance is manufactured.

Separately, by using only the first sheet 4a having a relative dielectric constant ε ₁ of 50 after sintering, a predetermined number of layers are laminated until the thickness of the desired final shape of the molded element is equal to that of the laminated molded article. Then, after the laminated molded body is cut into a chip shape (not shown) by cutting into a size corresponding to the final shape of the desired molded body element, as shown in FIG. 6 according to the size of the effective portion 5d. Square cylinder 5 by punching the inside with a press etc.
f, and then the effective portion 5d as shown in FIGS.
Is press-fitted into the hollow portion of the square tube 5f to be integrated. The subsequent manufacturing method is exactly the same as the method described in the first embodiment.

In this manufacturing method, the dielectric constant of the dielectric can be lowered not only on the upper and lower surfaces of the monolithic ceramic capacitor but also on the side surfaces thereof, so that the effect of the present invention can be further exerted.

In Embodiments 3 to 7, only one of the internal electrode layers connected in parallel and the one connected in series was described, but the same effect can be obtained in either type. Needless to say.

In Embodiments 1 to 7, the first dielectric layers 5a, 5c, and 5e are mainly described as having a low dielectric constant. However, in order to obtain the effect of the present invention, they are laminated. It is also possible to make at least one layer from the outermost layer of the ceramic capacitor have a lower dielectric constant than the second dielectric layer of the effective portions 5b and 5d.

[0070]

As described above, according to the present invention, it becomes possible to mass-produce a monolithic ceramic capacitor with high capacitance accuracy.
In addition, it is possible to significantly improve the creeping discharge resistance of the element surface, which brings about an epoch-making effect in manufacturing a monolithic ceramic capacitor. In particular, it is possible to improve the capacity hit rate at the time of manufacturing a temperature compensation capacitor that requires particularly strict capacitance accuracy, and to improve the creeping discharge resistance of a medium / high voltage application product that requires a high withstand voltage.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing a laminating process according to a first embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a laminating process according to a fourth embodiment of the present invention.

FIG. 3 is an exploded perspective view showing a laminating process according to a fifth embodiment of the present invention.

FIG. 4 is an exploded perspective view showing a manufacturing process according to a sixth embodiment of the present invention.

FIG. 5 is a perspective view of a laminated body according to a sixth embodiment of the present invention.

FIG. 6 is an exploded perspective view showing a manufacturing process according to a seventh embodiment of the present invention.

FIG. 7 is an exploded perspective view showing a manufacturing process according to a seventh embodiment of the present invention.

FIG. 8 is a perspective view of a laminated body according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view of a general monolithic ceramic capacitor having a parallel structure.

FIG. 10 is a cross-sectional view of a medium- and high-voltage monolithic ceramic capacitor having a series structure.

[Explanation of symbols]

 1 Dielectric Layer 2a Internal Electrode Layer 2b Counter Electrode 2c Floating Electrode 3 External Electrode 4a First Sheet 4b Second Sheet 4c Third Sheet 4d Third Sheet 5a First Dielectric Layer 5b Effective Part 5c First Dielectric layer 5d Effective part 5e Square plate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisao Nagura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Iwao Ishikawa, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. Within

Claims (11)

[Claims] 1. A ceramic sintered body having a laminated body in which dielectric layers and internal electrode layers are alternately laminated, and protective layers provided on both upper and lower surfaces of the laminated body, and a ceramic sintered body of the ceramic sintered body. An external electrode provided on the exposed end surface of the internal electrode layer, wherein the relative dielectric constant of at least the outermost layer of the protective layer is smaller than the non-dielectric constant of the dielectric layer sandwiched between the internal electrode layers. A multilayer ceramic capacitor characterized by the above. 2. When the relative permittivity of at least the outermost layer of the protective layer is ε1 and the relative permittivity of the dielectric layer is ε2, ε ₂ /
The multilayer ceramic capacitor according to claim 1, wherein ε ₁ ≧ 1.1. 3. The internal electrode layer includes a first internal electrode layer in which at least two electrodes face each other at a constant distance in the same plane, and one end of each is connected to another external electrode, and an end portion. 2. The multilayer ceramic capacitor according to claim 1, further comprising a second internal electrode layer provided in a non-contact state with the external electrode and overlapping the first internal electrode layer with a dielectric layer interposed therebetween. . 4. The thickness of at least the outermost layer of the protective layer is t
1. When the thickness of the dielectric layer is t2, 1 ≦ t ₁ / t ₂ ≦ 4
The multilayer ceramic capacitor according to claim 3. 5. A step of laminating a desired number of first ceramic sheets to form a lower first dielectric layer, and then forming a second dielectric layer and an internal electrode layer on the first dielectric layer. And (3) are alternately laminated to obtain a first laminated body, and a desired number of the first ceramic sheets are laminated on the first laminated body to form an upper first dielectric body. Forming a layer to obtain a second laminated body, and thereafter cutting the second laminated body into chips having a desired shape, then firing the chips, and then forming external electrodes on the end faces of the chips. And a relative dielectric constant of the first dielectric layer is smaller than that of the second dielectric layer. 6. The shrinkage factor of the first dielectric layer during firing is S ₁
(%), And the shrinkage rate of the second dielectric layer during firing is S ₂ (%)
The method for manufacturing a monolithic ceramic capacitor according to claim 5, wherein a dielectric layer satisfying | S ₁ −S ₂ | ≦ 3.0 is used. 7. The adhesive sheet of at least one layer is provided between the first dielectric layer and the second dielectric layer.
A method for manufacturing the multilayer ceramic capacitor described in. 8. The multilayer ceramic capacitor according to claim 7, wherein the adhesive sheet has a shrinkage ratio between at least the shrinkage ratio of the first dielectric layer and the shrinkage ratio of the second dielectric layer. Manufacturing method. 9. The method for manufacturing a laminated ceramic capacitor according to claim 7, wherein the adhesive sheet has higher adhesiveness than the first dielectric layer and the second dielectric layer. 10. A step of alternately stacking second dielectric layers and internal electrode layers to form a first stacked body, and a step of forming a first stacked body on a non-exposed surface of the internal electrode layers of the first stacked body. A step of pressure-bonding the first dielectric layer to form a second laminated body; and a step of firing the second laminated body and then forming external electrodes on the exposed end surfaces of the internal electrode layers, A method of manufacturing a laminated ceramic capacitor, wherein the relative dielectric constant of the first dielectric layer is smaller than the relative dielectric constant of the second dielectric layer. 11. A step of alternately stacking second dielectric layers and internal electrode layers to form a prismatic stacked body, and a step of forming the stacked body using the first dielectric layer. The method has a step of press-fitting into a cylinder and firing to obtain a sintered body, and a step of forming an external electrode on the exposed end surface of the internal electrode layer of the sintered body. A method for manufacturing a monolithic ceramic capacitor, wherein the dielectric constant is smaller than the relative dielectric constant of the second dielectric layer.