WO2019053954A1 - Multilayer capacitor and circuit module - Google Patents

Abstract

The present invention provides a multilayer capacitor in which, when mounted in a circuit module, a current that flows internally is taken into consideration, and a circuit module provided with the multilayer capacitor. The multilayer capacitor (10) of the present invention is provided with: a multilayer body in which internal electrodes (1) and internal electrodes (2) are alternately layered with a dielectric layer therebetween; an external electrode (4) electrically connected to the internal electrodes (1); an external electrode (5) electrically connected to the internal electrodes (2); and at least one internal electrode (6) which is layered on the multilayer body and not electrically connected to the external electrodes (4, 5). The internal electrode (6) is disposed in a position in which an eddy current is generated due to a current flowing between the external electrode (4) and the external electrode (5), and is not provided with an external electrode for electrical connection from the outside of the multilayer body.

Description

Multilayer capacitor and circuit module

The present invention relates to a multilayer capacitor and a circuit module.

In order to control power, circuit modules in which a semiconductor element of a power element, a multilayer capacitor, and the like are mounted on a substrate have been developed. In the circuit module, the current supplied from the power supply to the power supply line is output to the load through the power supply line, the semiconductor element, the multilayer capacitor, and the like. In the circuit module, since the current flowing through the wiring of the power supply line is large, the influence of the magnetic field due to the current, that is, the influence of the parasitic inductance generated between the wirings becomes a problem. As a specific influence, for example, when the semiconductor element mounted on the circuit module is switched, a surge voltage is generated due to the parasitic inductance.

In Non-Patent Document 1, in the circuit module of the converter, in order to reduce the parasitic inductance of the current loop flowing through the wiring, the layout of the substrate and the arrangement of components are changed. Specifically, in Non-Patent Document 1, the current loop is formed only by the wiring in the surface layer of the substrate, and the current loop is formed using the wiring in the surface layer of the substrate and the wiring in the middle layer of the substrate. It has changed. By changing the configuration, Non-Patent Document 1 can reduce the area of the current loop, and can reduce the distance between two opposing wires through which current flows in the reverse direction. Therefore, in Non-Patent Document 1, the magnetic fluxes generated by the currents flowing through the respective wires cancel each other, and the parasitic inductance can be reduced.

Further, Patent Document 1 discloses a circuit module provided with a semiconductor element and a multilayer capacitor, and a semiconductor such that the current flowing through the wiring on the surface layer of the substrate and the current flowing through the wiring on the back surface are opposite. An element and a multilayer capacitor are disposed and mounted. Therefore, in Patent Document 1, the current flowing in the wiring on the surface layer of the substrate and the wiring on the back surface is in the opposite direction, and the magnetic flux generated by the current cancels each other to reduce the parasitic inductance.

Furthermore, according to Patent Document 2, a circuit module mounting a capacitor includes a current loop including the capacitor in a current path, and a closed conductor loop formed by a wiring pattern parallel and opposite to the current loop. Therefore, in Patent Document 2, the closed conductor loop is coupled to the current loop in a ceramic manner, and the first inductor, which is a parasitic inductor component of the capacitor, is coupled to the closed conductor loop with a magnetically large coupling coefficient. Thus, the parasitic inductance of the capacitor can be reduced.

JP, 2016-207783, A International Publication No. 2017/033950

However, in Non-Patent Document 1, the current loop is reduced by optimizing the layout of the substrate and the arrangement of components, and the distance between the two opposing wires through which the current flows in the opposite direction is reduced. Therefore, in Non-Patent Document 1, the current flowing inside the component mounted on the substrate is not considered, and there is a limit in reducing the parasitic inductance.

Further, in Patent Document 1, the wiring and component layout are optimized to reduce the parasitic inductance so that the current flowing in the wiring in the surface layer of the substrate and the current flowing in the wiring in the back surface are opposite. Therefore, even in Patent Document 1, the current flowing in the inside of the component mounted on the substrate is not considered, and there is a limit to reducing the parasitic inductance.

Furthermore, in Patent Document 2, the parasitic inductance of the capacitor is reduced by configuring a closed conductor loop for magnetically coupling to a current loop including a capacitor in the current path. Therefore, in Patent Document 2, if the resonance frequency of the impedance of the current loop including the capacitor in the current path and the impedance of the closed conductor loop are not matched, strong magnetic coupling does not occur, and there is a problem that the parasitic inductance can not be reduced.

Therefore, an object of the present invention is to provide a multilayer capacitor and a circuit module including the multilayer capacitor in consideration of the current flowing inside when mounted in a circuit module.

In the multilayer capacitor in accordance with an embodiment of the present invention, a multilayer body in which first internal electrodes and second internal electrodes are alternately stacked with a dielectric layer interposed therebetween, and a first electrically connected to the first internal electrodes At least one or more first electrodes stacked on the laminated body, the second external electrode electrically connected to the second internal electrode, and not electrically connected to the first external electrode and the second external electrode; The third internal electrode is provided at a position where an eddy current is generated by the current flowing between the first external electrode and the second external electrode, and the external is electrically connected from the outside of the laminate There is no electrode.

A circuit module according to an aspect of the present invention includes the multilayer capacitor described above and a wiring board on which the multilayer capacitor is mounted.

According to the present invention, by providing the third inner electrode in which an eddy current is generated by the current flowing inside the multilayer capacitor, the magnetic flux due to the eddy current and the magnetic flux due to the current loop of the current path flowing inside the multilayer capacitor cancel each other. Therefore, parasitic inductance can be reduced. Further, according to the present invention, since the eddy current is generated not in the wiring pattern but in the internal electrode, the eddy current can be generated according to the magnetic flux generated by the current loop, and the parasitic inductance can be generated for the current of any frequency. Can be made smaller.

FIG. 1 is a schematic view for illustrating the configuration of the multilayer capacitor in accordance with a first embodiment of the present invention. FIG. 2 is a circuit diagram of a circuit module on which the multilayer capacitor in accordance with the first embodiment of the present invention is mounted. It is the schematic for demonstrating the structure of the circuit module which mounted the multilayer capacitor which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the structure of the circuit module which mounted the multilayer capacitor of comparison object. FIG. 7 is a schematic diagram for illustrating the configuration of the multilayer capacitor in accordance with Embodiment 2 of the present invention. FIG. 7 is a schematic view for illustrating the shape of the internal electrode of the multilayer capacitor in accordance with Embodiment 2 of the present invention. It is the schematic for demonstrating the structure of the circuit module which mounted the multilayer capacitor which concerns on Embodiment 2 of this invention. It is the schematic for demonstrating the structure of the circuit module which mounted the multilayer capacitor of comparison object. FIG. 10 is a circuit diagram of a circuit module on which the multilayer capacitor in accordance with the third embodiment of the present invention is mounted. FIG. 7 is a schematic diagram for illustrating the configuration of the multilayer capacitor in accordance with Embodiment 3 of the present invention. FIG. 13 is a schematic view for illustrating the shape of the internal electrode of the multilayer capacitor in accordance with Embodiment 3 of the present invention. It is the schematic for demonstrating the structure of the circuit module which mounted the multilayer capacitor which concerns on Embodiment 3 of this invention. It is the schematic for demonstrating the structure of the multilayer capacitor which concerns on Embodiment 4 of this invention. FIG. 13 is a schematic view for illustrating the shape of the internal electrode of the multilayer capacitor in accordance with the fourth embodiment of the present invention. It is the schematic for demonstrating the structure of the multilayer capacitor which concerns on Embodiment 5 of this invention. FIG. 18 is a schematic diagram for illustrating the shape of the internal electrode of the first block of the multilayer capacitor in accordance with Embodiment 5 of the present invention. FIG. 16 is a schematic diagram for illustrating the shape of the internal electrode of the second block of the multilayer capacitor in accordance with Embodiment 5 of the present invention. FIG. 21 is a schematic diagram for illustrating the shape of the internal electrode of the third block of the multilayer capacitor in accordance with Embodiment 5 of the present invention. FIG. 8 is a schematic view for explaining the configuration of the multilayer capacitor in accordance with the modification of the present invention.

Hereinafter, multilayer capacitors and circuit modules according to embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

Embodiment 1
Hereinafter, the multilayer capacitor and the circuit module according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram for explaining the configuration of the multilayer capacitor 10 in accordance with the first embodiment of the present invention. 1 (a) is a plan view of the multilayer capacitor 10 viewed from the surface on which the external electrodes 4 and 5 are formed, and FIG. 1 (b) is a cross-sectional view of the multilayer capacitor 10.

The multilayer capacitor 10 shown in FIG. 1 is a multilayer ceramic capacitor, in which a plurality of internal electrodes 1 and 2 for obtaining capacitance and dielectric ceramic layers 3 are alternately stacked. That is, the laminated body is configured by alternately laminating the internal electrode 1 (first internal electrode) and the internal electrode 2 (second internal electrode) with the dielectric ceramic layer 3 interposed therebetween. The stacked internal electrodes 1 and 2 are alternately drawn out at one end and the other end of the multilayer capacitor 10. The internal electrodes 1 and 2 drawn out to the respective end portions are connected to external electrodes 4 and 5 provided to the respective end portions of the multilayer capacitor 10. That is, the external electrode 4 (first external electrode) is formed at one end (first side surface) of the laminate, and the external electrode 5 (second external electrode) is a laminate of the one facing the one end. It is formed at the other end (second side surface).

Furthermore, the multilayer capacitor 10 includes the internal electrode 6 (third internal electrode) not electrically connected to the external electrode 4 and the external electrode 5 as shown on the upper side of the laminated body shown in FIG. They are respectively provided on the upper side of the upper layer and the lower side (lower side of the lowermost layer of the internal electrode 2). The internal electrode 6 may be provided on one of the upper side and the lower side of the laminate.

The internal electrode 6 is provided at a position where an eddy current is generated by the current flowing between the external electrode 4 and the external electrode 5, and the external electrode electrically connected from the outside of the laminate is not provided. That is, the internal electrode 6 can not supply current from the outside. Further, in the internal electrode 6, since the eddy current is generated by the magnetic flux generated in the current loop flowing between the external electrode 4 and the external electrode 5, the magnetic flux by the current loop and the magnetic flux by the eddy current cancel each other to reduce the parasitic inductance. can do.

Further, since the internal electrode 6 is a plate-like electrode, it is not restricted by the size of the current path if in the plane of the electrode, and an eddy current can be generated in accordance with the magnetic flux generated by the current loop. That is, when the size is fixed as in the wiring pattern, the eddy current can be generated only when a current of a specific frequency flows in the current loop, but in the internal electrode 6, any frequency can be generated in the current loop The eddy current can be generated even if the current of Therefore, the multilayer capacitor 10 can reduce the parasitic inductance with respect to the current of any frequency by providing the internal electrode 6.

The multilayer capacitor 10 is formed, for example, by laminating a plurality of barium titanate ceramic green sheets (dielectric ceramic layer 3) on which an electrode pattern is formed by printing a conductive paste (Ni paste) by a screen printing method. It can be formed.

The internal electrode 6 is an electrode other than an electrode for forming a capacitance, but as shown in FIG. 1B, it is parallel to the internal electrodes 1 and 2 which are electrodes for forming a capacitance It is laminated on a laminate. Since the internal electrode 6 and the internal electrodes 1 and 2 are arranged in parallel, the magnetic flux generated by the current loop flowing through the internal electrodes 1 and 2 and the magnetic flux generated by the eddy current generated in the internal electrode 6 are more It is possible to cancel each other to make the parasitic inductance smaller. Of course, even if the internal electrode 6 and the internal electrodes 1 and 2 are not arranged in parallel, the multilayer capacitor 10 is arranged such that the magnetic flux generated by the current loop and the magnetic flux generated by the eddy current cancel each other. Any arrangement may be used.

In the multilayer capacitor 10, the distance between the internal electrode 1 and the internal electrode 6 or the distance between the internal electrode 2 and the internal electrode 6 is the same as the distance between the internal electrode 1 and the internal electrode 2. That is, in the multilayer capacitor 10, the internal electrode 1, the internal electrode 2 and the internal electrode 6 are laminated at equal intervals. Therefore, the internal electrode 6 can be formed in the same process as the internal electrodes 1 and 2 and the manufacture becomes easy. Of course, in the multilayer capacitor 10, the distance between the internal electrode 1 and the internal electrode 6 or the distance between the internal electrode 2 and the internal electrode 6 may be shorter than the distance between the internal electrode 1 and the internal electrode 2.

In the multilayer capacitor 10, the thickness of the internal electrode 6 (up and down direction in FIG. 1B) is made as large as possible in the range included in the dielectric ceramic layer 3. By thickening the internal electrode 6, a large eddy current can be generated in accordance with the magnetic flux generated by the current loop.

In the multilayer capacitor 10, the electrode material of the internal electrode 6 is the same as the electrode material of the internal electrode 1 and the internal electrode 2. For example, the electrode material of the internal electrode 6 is the same as the electrode material of the internal electrode 1 and the internal electrode 2, for example, a conductive paste (Ni paste). Therefore, the internal electrode 6 can be formed in the same process as the internal electrodes 1 and 2 and the manufacture becomes easy. Of course, in the multilayer capacitor 10, the electrode material of the internal electrode 6 may be different from the electrode material of the internal electrode 1 and the internal electrode 2.

Next, a circuit module on which the multilayer capacitor 10 is mounted will be described. The case where it is a half bridge circuit which connected two switching elements and one laminated capacitor 10 in series as a circuit module, for example is explained. FIG. 2 is a circuit diagram of a circuit module on which the multilayer capacitor 10 according to the first embodiment of the present invention is mounted. In the circuit diagram shown in FIG. 2, one electrode of the multilayer capacitor 10 and the switching element S1 are connected by the VDD wiring V, the switching element S1 and the switching element S2 are connected by the intermediate wiring N, and the switching element S2 and the multilayer capacitor The other electrode 10 is connected by the GND wiring G.

Based on the circuit diagram shown in FIG. 2, a circuit module in which the switching elements S1 and S2 and the multilayer capacitor 10 are mounted on the substrate is shown in FIG. FIG. 3 is a schematic diagram for explaining the configuration of a circuit module 100 on which the multilayer capacitor in accordance with the first embodiment of the present invention is mounted. 3A shows a plan view of the circuit module 100 as viewed from the surface on which the multilayer capacitor 10 is mounted, and FIG. 3B shows a cross-sectional view of the circuit module 100. As shown in FIG.

In the circuit module 100 shown in FIG. 3, the switching elements S1 and S2 and the multilayer capacitor 10 are respectively connected to the VDD wiring V, the middle wiring N and the GND wiring G formed on the surface of the substrate 20. The GND wirings G provided at both ends of the substrate 20 are connected by the wirings formed on the back surface of the substrate 20 through the vias 21 provided at the end of the substrate 20 as shown in FIG. 3B. There is. Therefore, in the circuit module 100, a current loop R as shown by the arrow in FIG. 3 (b) is formed.

In the circuit module 100, a current loop R flowing inside the multilayer capacitor 10 generates a magnetic flux penetrating from the back to the front of FIG. 3B. An eddy current P is generated in the internal electrode 6 by the magnetic flux generated by the current loop R. The eddy current P flows in the direction opposite to the current direction of the current loop R, and the eddy current P generates a magnetic flux in the opposite direction which penetrates from the front to the back of FIG. 3B. Therefore, in the circuit module 100, the magnetic flux due to the current loop R and the magnetic flux due to the eddy current P cancel each other, and the parasitic inductance can be reduced.

Here, a circuit module mounted with a multilayer capacitor without the internal electrode 6 will be described for comparison. FIG. 4 is a schematic diagram for explaining the configuration of a circuit module 100z on which multilayer capacitors to be compared are mounted. 4 (a) is a plan view of the circuit module 100z as viewed from the surface on which the multilayer capacitor is mounted, and FIG. 4 (b) is a cross-sectional view of the circuit module 100z.

Also in the circuit module 100z shown in FIG. 4, the switching elements S1 and S2 and the multilayer capacitor 10z are respectively connected to the VDD wiring V, the middle wiring N and the GND wiring G formed on the surface of the substrate 20. The GND wirings G provided at both ends of the substrate 20 are connected by the wirings formed on the back surface of the substrate 20 through the vias 21 provided at the end of the substrate 20, as shown in FIG. 4B. There is.

However, the multilayer capacitor 10 z does not have the internal electrode 6 as the multilayer capacitor 10 does. Therefore, the eddy current P is not generated by the magnetic flux generated by the current loop R. That is, no magnetic flux is generated that offsets the magnetic flux generated by the current loop R.

Comparing the circuit module 100 shown in FIG. 3 (b) with the circuit module 100z shown in FIG. 4 (b), the circuit module 100 shown in FIG. 3 (b) is provided with the internal electrode 6, so the internal electrode An eddy current P is generated at 6 and a magnetic flux due to the eddy current P is generated. As a result, in the circuit module 100 shown in FIG. 3, since the magnetic flux due to the eddy current P offsetting the magnetic flux generated by the current loop R is generated as compared with the circuit module 100z shown in FIG. Can. That is, in the circuit module 100 shown in FIG. 3, in consideration of the current flowing inside the multilayer capacitor 10, the internal electrode 6 for generating the eddy current P is provided in the multilayer body to reduce the parasitic inductance.

As described above, the circuit module 100 according to the first embodiment includes the multilayer capacitor 10 and the substrate 20 on which the multilayer capacitor 10 is mounted. Furthermore, in the multilayer capacitor 10, the internal electrode 6 is provided at a position where an eddy current is generated by the current flowing between the external electrode 4 and the external electrode 5. The internal electrode 6 is not further provided with an external electrode electrically connected from the outside of the laminate. Further, the substrate 20 is provided with a wire that allows current to flow between the external electrodes 4 and 5 when the multilayer capacitor 10 is mounted.

Therefore, in the circuit module 100 according to the first embodiment, by considering the current flowing inside the multilayer capacitor 10, the internal electrode 6 generating eddy current is provided in the multilayer body, so that the magnetic flux due to the eddy current and the multilayer capacitor The magnetic flux due to the current loop of the current path flowing inside the can cancel each other to reduce the parasitic inductance. Further, in the circuit module 100 according to the first embodiment, since the eddy current is generated not in the wiring pattern but in the internal electrode 6, the eddy current can be generated in accordance with the magnetic flux generated by the current loop. The parasitic inductance can be reduced with respect to the current of

Second Embodiment
In the multilayer capacitor 10 according to the first embodiment, as shown in FIG. 1B, the configuration in which the plurality of dielectric ceramic layers are stacked in the vertical direction in the drawing has been described. However, the direction in which the dielectric ceramic layers are stacked is not limited to the vertical direction. Therefore, in the second embodiment of the present invention, a multilayer capacitor 10b in which a plurality of dielectric ceramic layers are horizontally stacked will be described. FIG. 5 is a schematic diagram for explaining the configuration of the multilayer capacitor 10b according to the second embodiment of the present invention. 5 (a) is a plan view of the multilayer capacitor 10b viewed from the surface on which the external electrodes 4 and 5 are formed, and FIG. 5 (b) is a front view of the multilayer capacitor 10b viewed from the laminating direction. It shows. Further, in FIG. 5A, the external electrodes 4 and 5 are shown by broken lines in order to explain the arrangement of the internal electrodes 1, 2 and 6.

The multilayer capacitor 10b shown in FIG. 5 (a) is a multilayer ceramic capacitor, in which a plurality of internal electrodes 1 and 2 for obtaining capacitance and dielectric ceramic layers 3 are alternately stacked in the horizontal direction in the figure. ing. That is, the laminated body is configured by alternately laminating the internal electrode 1 (first internal electrode) and the internal electrode 2 (second internal electrode) with the dielectric ceramic layer 3 interposed therebetween. Furthermore, in the multilayer capacitor 10 b, the internal electrode 6 is laminated between the internal electrode 1 and the internal electrode 2. FIG. 6 is a schematic diagram for illustrating the shapes of the internal electrodes 1, 2, 6 of the multilayer capacitor 10b according to the second embodiment of the present invention.

FIG. 6A shows a layer on which the internal electrode 1 which is an electrode for forming a capacitance is provided. The internal electrode 1 has the lead-out electrode part 1a of width a and height h as shown to Fig.6 (a). An external electrode 4 electrically connected to the lead electrode portion 1a is formed on the surface of the multilayer capacitor 10b from which the lead electrode portion 1a is drawn. In FIG. 6B, a layer provided with an internal electrode 6 which is an electrode other than an electrode for forming a capacitance is illustrated. The internal electrode 6 is an electrode having a width x and a height y as shown in FIG. 6 (b). When the internal electrodes 6 are stacked as shown in FIG. 5B, the internal electrodes 6 are provided at positions not overlapping with the lead-out electrode portion 1a as viewed from the stacking direction. The layer which provides the internal electrode 2 which is an electrode for forming a capacity | capacitance in FIG.6 (c) is shown in figure. The internal electrode 2 has the lead-out electrode part 2a of width b and height h as shown in FIG.6 (c). When the lead-out electrode portions 2a are stacked as shown in FIG. 5B, the lead-out electrode portions 2a are provided at positions not overlapping with the lead-out electrode portions 1a and the internal electrodes 6 when viewed in the stacking direction. An external electrode 5 electrically connected to the lead electrode portion 2a is formed on the surface of the multilayer capacitor 10b from which the lead electrode portion 2a is drawn.

That is, the internal electrodes 1 and 2 to be laminated are alternately drawn out at one end and the other end of the multilayer capacitor 10b. The internal electrode 6 to be laminated is provided in the middle of the multilayer capacitor 10b sandwiched between the internal electrodes 1 and 2. The internal electrode 1 drawn out at one end is connected to the external electrode 4 provided at one end of the multilayer capacitor 10b, and the internal electrode 2 drawn out at the other end is the other side of the multilayer capacitor 10b. It is connected to the external electrode 5 provided at the end of the. That is, the internal electrode 6 is formed on the same surface side of the laminate in which the external electrode 4 (first external electrode) and the external electrode 5 (second external electrode) are formed. Here, the extraction electrode portion 1a is a portion not facing the internal electrode 2 in the internal electrode 1, and the extraction electrode portion 2a is a portion not facing the internal electrode 1 in the internal electrode 2 (see FIG. b) see).

The internal electrode 6 is formed in the dielectric ceramic layer 3 so as to be stacked in parallel with the electrode surface of the internal electrodes 1 and 2. The material and thickness thereof (vertical direction in the drawing of FIG. 5A) Are the same as the internal electrodes 1 and 2. Since the internal electrode 6 and the internal electrodes 1 and 2 are arranged in parallel, the internal electrode 6 can be adjusted to the magnetic flux generated by the current loop flowing between the external electrodes 4 and 5 via the internal electrodes 1 and 2. Large eddy currents can be generated.

The internal electrode 6 is disposed between the lead-out electrode portions 1a and 2a of the internal electrodes 1 and 2, the width x can be expressed as x = c- (a + b) -2α, and the height y is expressed as y = h be able to. Here, α indicates the gap between the lead-out electrode portions 1a and 2a and the internal electrode 6, and it is possible to secure a sufficient distance such that the lead-out electrode portions 1a and 2a and the inner electrode 6 do not short. It is a value. The reason that the height y of the internal electrode 6 is the same as the height h of the lead-out electrode portions 1a and 2a is to prevent the internal electrode 6 and the internal electrodes 1 and 2 from overlapping to form a capacitance. In addition, a gap is generated between the internal electrode 6 and the internal electrodes 1 and 2 to prevent a magnetic flux from being generated in the gap to form a parasitic inductance.

As shown in FIG. 5A, the internal electrodes 6 are stacked on the laminate at an equal interval of 1 per internal electrode 1 and 2. With such a stacking relationship, the distance A between the internal electrode 1 and the adjacent internal electrode 1 or the distance A between the internal electrode 2 and the adjacent internal electrode 2 is greater than when the internal electrode 6 is not provided. It becomes long (see FIG. 5 (a)). The rate at which the internal electrodes 6 are stacked is not limited to the above ratio. For example, the internal electrodes 6 are stacked in the laminate at an equal ratio of one to two each of the internal electrodes 1 and 2 You may

Next, a circuit module on which the multilayer capacitor 10b is mounted will be described. The case where it is a half bridge circuit which connected two switching elements and one laminated capacitor 10b in series as a circuit module, for example is explained. Since the circuit diagram is the same as the circuit diagram shown in FIG. 2, detailed description will not be repeated. FIG. 7 is a schematic diagram for describing a configuration of a circuit module 100b mounting the multilayer capacitor in accordance with the second embodiment of the present invention. 7 (a) is a plan view of the circuit module 100b as viewed from the surface on which the multilayer capacitor 10b is mounted, and FIG. 7 (b) is a cross-sectional view of the circuit module 100b.

In the circuit module 100b shown in FIG. 7, the switching elements S1 and S2 and the multilayer capacitor 10b are respectively connected to the VDD wiring V, the middle wiring N and the GND wiring G formed on the surface of the substrate 20. The GND wirings G provided at both ends of the substrate 20 are connected by the wirings formed on the back surface of the substrate 20 through the vias 21 provided at the end of the substrate 20, as shown in FIG. 7B. There is. Therefore, in the circuit module 100b, a current loop R2 as shown by the arrow in FIG. 7B is formed.

In the circuit module 100b, the current loop R2 flowing inside the multilayer capacitor 10b generates a magnetic flux penetrating from the back to the front of FIG. 7B. An eddy current P2 is generated in the internal electrode 6 by the magnetic flux generated by the current loop R2. A current flows in the opposite direction to the current direction of the current loop R2, and the eddy current P2 generates a magnetic flux in the opposite direction which penetrates from the front to the back of FIG. 7B by the eddy current P2. Therefore, in the circuit module 100b, the magnetic flux due to the current loop R2 and the magnetic flux due to the eddy current P2 cancel each other, and the parasitic inductance can be reduced.

Here, a circuit module mounted with a multilayer capacitor without the internal electrode 6 will be described for comparison. FIG. 8 is a schematic diagram for illustrating the configuration of a circuit module 100x mounting the multilayer capacitor to be compared. 8 (a) is a plan view of the circuit module 100x as viewed from the surface on which the multilayer capacitor is mounted, and FIG. 8 (b) is a cross-sectional view of the circuit module 100x.

Also in the circuit module 100x shown in FIG. 8, the switching elements S1 and S2 and the multilayer capacitor 10x are respectively connected to the VDD wiring V, the middle wiring N and the GND wiring G formed on the surface of the substrate 20. The GND wires G provided at both ends of the substrate 20 are connected by the wires formed on the back surface of the substrate 20 via the vias 21 provided at the end of the substrate 20 as shown in FIG. 8B. There is.

However, the multilayer capacitor 10 x does not have the internal electrode 6 as the multilayer capacitor 10 does. Therefore, the eddy current P2 is not generated by the magnetic flux generated by the current loop R2. That is, no magnetic flux is generated that offsets the magnetic flux generated by the current loop R2.

Comparing the circuit module 100b shown in FIG. 7 (b) with the circuit module 100x shown in FIG. 8 (b), the circuit module 100b shown in FIG. An eddy current P2 is generated at 6 and a magnetic flux is generated by the eddy current P2. As a result, in the circuit module 100b shown in FIG. 7, a magnetic flux is generated due to the eddy current P2 that offsets the magnetic flux generated by the current loop R2 compared to the circuit module 100x shown in FIG. Can. That is, in the circuit module 100b shown in FIG. 7, in consideration of the current flowing inside the multilayer capacitor 10b, the internal electrode 6 for generating the eddy current P2 is provided in the multilayer body to reduce the parasitic inductance.

In the multilayer capacitor 10b, there is a gap B between the lead electrode portions 1a and 2a and the internal electrode 6 as shown in FIG. 5 (b). Therefore, when the multilayer capacitor 10b is mounted on the herb bridge circuit as shown in FIG. 7B, the current indicated by the arrow of the current loop R2 flows around the gap B in the multilayer capacitor 10b, and the current flows A magnetic flux T is generated in the direction of penetrating the gap B (see FIG. 5A).

As described above, multilayer capacitor 10 b according to the second embodiment has lead electrode portion 1 a (first lead portion) for connecting internal electrode 1 to external electrode 4 in a portion where internal electrode 1 does not face internal electrode 2. It has a lead-out electrode portion 2a (second lead-out portion) for connecting to the external electrode 5 in a portion where the internal electrode 2 does not face the internal electrode 1. Furthermore, in the multilayer capacitor 10b, the internal electrode 6 is laminated on the layer of the laminated body between the internal electrode 1 and the internal electrode 2, and viewed from the laminating direction, between the lead electrode portion 1a and the lead electrode portion 2a. And, it is disposed at a position not overlapping the internal electrode 1 and the internal electrode 2.

Therefore, in the circuit module 100b according to the second embodiment, in consideration of the current flowing inside the multilayer capacitor 10b, the internal electrode 6 that generates an eddy current is provided in the multilayer body, so that the magnetic flux due to the eddy current and the multilayer capacitor The magnetic flux due to the current loop of the current path flowing inside the can cancel each other to reduce the parasitic inductance. Further, in the circuit module 100b according to the second embodiment, since the eddy current is generated not in the wiring pattern but in the internal electrode 6, the eddy current can be generated in accordance with the magnetic flux generated by the current loop. The parasitic inductance can be reduced with respect to the current of

Third Embodiment
In the multilayer capacitor 10b according to the second embodiment, as shown in FIG. 5B, the configuration in which the internal electrode 6 is disposed between the lead-out electrode portion 1a and the lead-out electrode portion 2a as viewed from the stacking direction explained. However, the arrangement of the internal electrodes 6 is not limited to between the lead electrode portion 1a and the lead electrode portion 2a. Therefore, in the third embodiment of the present invention, the configuration in which the internal electrode 6 is formed on the surface of the laminate facing the surface of the laminate on which the external electrode 4 and the external electrode 5 are formed will be described.

The multilayer capacitor according to the third embodiment is not the half bridge circuit shown in FIG. 2, but two switching elements on the high side, two switching elements on the low side, and one multilayer capacitor in series. It is possible to implement in the connected half bridge circuit.

FIG. 9 is a circuit diagram of a circuit module on which the multilayer capacitor in accordance with the third embodiment of the present invention is mounted. In the circuit diagram shown in FIG. 9, one electrode of the multilayer capacitor 10c and the switching element S1 are connected by the VDD wiring V, and the switching element S1 and the switching element S2 are connected by the wiring N1. Further, in the circuit diagram shown in FIG. 9, the switching element S2, the switching element S3, and the wiring N1 are connected by the intermediate wiring N, the switching element S3 and the switching element S4 are connected by the wiring N2, and the switching element S4 and the multilayer capacitor 10c. The other electrode of is connected by the GND wiring G.

Next, the configuration of the multilayer capacitor 10c will be described with reference to the drawings. FIG. 10 is a schematic diagram for illustrating the configuration of the multilayer capacitor 10c according to the third embodiment of the present invention. 10 (a) is a plan view of the multilayer capacitor 10c viewed from the surface on which the external electrodes 4 and 5 are formed, and FIG. 10 (b) is a front view of the multilayer capacitor 10c viewed from the stacking direction. It shows. FIG. 11 is a schematic diagram for illustrating the shapes of the internal electrodes 1, 2, 6 of the multilayer capacitor 10c in accordance with the third preferred embodiment of the present invention. In the multilayer capacitor 10c shown in FIGS. 10 and 11, the same components as those in the multilayer capacitor 10b shown in FIGS. 5 and 6 are denoted by the same reference numerals, and the detailed description will not be repeated. Further, in FIG. 10A, the external electrodes 4 and 5 are shown by broken lines in order to explain the arrangement of the internal electrodes 1, 2 and 6.

FIG. 11A shows a layer on which the internal electrode 1 which is an electrode for forming a capacitance is provided. The internal electrode 1 is formed on the opposite side of the side on which the lead electrode portion 1a is formed from the inside by a height l from the surface of the laminate. In FIG. 11B, a layer provided with an internal electrode 6 which is an electrode other than an electrode for forming a capacitance is illustrated. The internal electrode 6 is an electrode having a width x1 and a height y1 formed on the lower side in the drawing of the laminate as shown in FIG. 11 (b). When the internal electrodes 6 are stacked as shown in FIG. 10B, they are provided at positions not overlapping with the internal electrodes 1 and 2 when viewed in the stacking direction. FIG. 11C shows a layer on which the internal electrode 2 which is an electrode for forming a capacitance is provided. The internal electrode 2 is formed on the opposite side of the side on which the lead electrode portion 2a is formed from the inside by a height l from the surface of the laminate.

That is, the internal electrode 6 (third internal electrode) is formed on the surface side of the laminate facing the surface of the laminate on which the external electrode 4 (first external electrode) and the external electrode 5 (second external electrode) are formed. ing.

The internal electrode 6 is formed in the dielectric ceramic layer 3 so as to be stacked in parallel with the electrode surface of the internal electrodes 1 and 2, and its material and thickness (vertical direction in the drawing of FIG. 10A) Are the same as the internal electrodes 1 and 2. The arrangement of the internal electrode 6 and the internal electrodes 1 and 2 in parallel causes a current flowing through the internal electrode 6 and a current loop flowing between the external electrodes 4 and 5 through the internal electrodes 1 and 2. A large eddy current can be generated in accordance with the magnetic flux.

The internal electrode 6 is disposed inside the surface of the laminate facing the surface of the laminate on which the external electrodes 4 and 5 are formed, and the width x1 can be expressed as x1 ≦ c, and the height y1 is y1 = l. Can be represented. The reason that the height y1 of the internal electrode 6 is the same as the height l is to prevent the internal electrode 6 and the internal electrodes 1 and 2 from overlapping to form a capacitance, and the internal electrode 6 and the internal A gap is generated between the electrodes 1 and 2 to prevent a magnetic flux from being generated in the gap to form a parasitic inductance. The internal electrode 6 may be configured as one electrode or divided into a plurality of components. Although it has been described that the width x1 is x1 ≦ c, the longer the distance between the internal electrodes 1, 2 and the internal electrode 6 becomes longer, the magnetic flux due to the current flowing through the internal electrodes 1, 2 and the vortex flowing into the internal current 6 Since the effect of the magnetic flux due to the current mutually cancels out, from the viewpoint of the effect, the width x1 is preferably x1 ≧ c.

Next, a circuit module on which the multilayer capacitor 10c is mounted will be described. FIG. 12 is a schematic diagram for illustrating the configuration of a circuit module 100c on which the multilayer capacitor 10c according to the third embodiment of the present invention is mounted. 12 (a) is a schematic diagram for explaining the configuration of the circuit module 100c, and FIG. 12 (b) is a schematic diagram for explaining the configuration of the circuit module 100w on which the multilayer capacitor to be compared is mounted. Respectively.

In the circuit module 100c shown in FIG. 12A, the multilayer capacitor 10c is embedded in the substrate 20, and the VDD wiring V, the wirings N1 and N2, and the GND wiring G formed on the surface of the substrate 20 have switching elements S1 and S4 respectively. It is connected. Further, in the circuit module 100c, the switching elements S2 and S3 are connected to the wirings N1 and N2 and the middle wiring N formed on the back surface of the substrate 20, respectively. The wirings N1 and N2 provided at both ends of the substrate 20 are, as shown in FIG. 12A, the wirings N1 and N2 formed on the back surface of the substrate 20 via the vias 21 provided at the end of the substrate 20. Connected to each other. Therefore, in the circuit module 100c, a current loop R3 as shown by an arrow in FIG. 12A is formed.

In the circuit module 100c, a magnetic flux penetrating from the back to the front of FIG. 12A is generated by the current loop R3 flowing inside the multilayer capacitor 10c. An eddy current P3 is generated in the internal electrode 6 by the magnetic flux generated by the current loop R3. A current flows in the eddy current P3 in the direction opposite to the current direction of the current loop R3, and the eddy current P3 generates a magnetic flux in the opposite direction penetrating from the front to the back of FIG. Therefore, in the circuit module 100c, the magnetic flux due to the current loop R3 and the magnetic flux due to the eddy current P3 cancel each other, and the parasitic inductance can be reduced.

Here, a circuit module mounted with a multilayer capacitor without the internal electrode 6 will be described for comparison. Also in the circuit module 100w shown in FIG. 12B, the multilayer capacitor 10w is embedded in the substrate 20, and the VDD wiring V, the wirings N1, N2 and the GND wiring G formed on the surface of the substrate 20 are switching elements S1 and S4, respectively. It is connected. Further, in the circuit module 100 w, the switching elements S 2 and S 3 are respectively connected to the wirings N 1 and N 2 and the middle wiring N formed on the back surface of the substrate 20. The wirings N1 and N2 provided at both ends of the substrate 20 are, as shown in FIG. 12B, the wirings N1 and N2 formed on the back surface of the substrate 20 via the vias 21 provided at the end of the substrate 20. Connected to each other.

However, the multilayer capacitor 10 w does not have the internal electrode 6 as the multilayer capacitor 10 does. Therefore, the eddy current P3 is not generated by the magnetic flux generated by the current loop R3. That is, no magnetic flux is generated that offsets the magnetic flux generated by the current loop R3.

Comparing the circuit module 100c shown in FIG. 12 (a) with the circuit module 100w shown in FIG. 12 (b), the circuit module 100c shown in FIG. An eddy current P3 is generated at 6 and a magnetic flux is generated by the eddy current P3. As a result, in the circuit module 100c shown in FIG. 12A, a magnetic flux due to the eddy current P3 that cancels out the magnetic flux generated by the current loop R3 is generated as compared to the circuit module 100w shown in FIG. Parasitic inductance can be reduced. That is, in the circuit module 100c shown in FIG. 12A, in consideration of the current flowing inside the multilayer capacitor 10c, the internal electrode 6 for generating the eddy current P3 is provided in the multilayer body to reduce the parasitic inductance.

As described above, in the multilayer capacitor 10c according to the third embodiment, the internal electrode 6 is formed on the surface of the laminate facing the surface of the laminate on which the external electrode 4 and the external electrode 5 are formed. Therefore, in the multilayer capacitor 10c, the capacitor itself can be embedded in the substrate to make it easy to use, and the internal electrode 6 can be formed without being restricted by the shapes of the lead electrode portions 1a and 2a.

Embodiment 4
In the multilayer capacitor 10b according to the second embodiment, as shown in FIG. 5A, the distance A between the internal electrode 1 and the adjacent internal electrode 1 or the distance A between the internal electrode 2 and the adjacent internal electrode 2 is internal It became long by having provided the electrode 6. When forming the external electrodes 4 and 5 in the plating step, when the distance A is long, the lead electrode portions 1a of the plurality of internal electrodes 1 and the lead electrode portions 2a of the plurality of internal electrodes 2 are plated. It is difficult to form the external electrodes 4 and 5 so as to short. Therefore, in the fourth embodiment of the present invention, a configuration in which a dummy electrode is formed to shorten the distance between the internal electrodes forming the external electrodes 4 and 5 will be described.

FIG. 13 is a schematic diagram for illustrating the configuration of the multilayer capacitor 10d according to the fourth embodiment of the present invention. 13 (a) is a plan view of the multilayer capacitor 10d viewed from the surface on which the external electrodes 4 and 5 are formed, and FIG. 13 (b) is a front view of the multilayer capacitor 10d viewed from the stacking direction. It shows. FIG. 14 is a schematic diagram for illustrating the shapes of the internal electrodes 1, 2, 6 of the multilayer capacitor 10d in accordance with the fourth embodiment of the present invention. In the multilayer capacitor 10d shown in FIGS. 13 and 14, the same components as those in the multilayer capacitor 10b shown in FIGS. 5 and 6 are denoted by the same reference numerals, and the detailed description will not be repeated. Further, in FIG. 13A, in order to explain the arrangement of the internal electrodes 1, 2, 6, the external electrodes 4, 5, 7 are shown by broken lines.

FIG. 14A shows a layer on which the internal electrode 1 which is an electrode for forming a capacitance is provided. The internal electrode 1 has an extraction electrode portion 1a on the left side of the drawing of FIG. 14 (a). Further, in the layer in which the internal electrode 1 is provided, the dummy electrode 2b is provided at a position corresponding to the lead-out electrode portion 2a of the layer in which the internal electrode 2 is provided (right side in the drawing of FIG. The lead-out electrode portion 1 a is electrically connected to the internal electrode 1, but the dummy electrode 2 b is not electrically connected to the internal electrode 1. In addition, the external electrode 5 is formed on the dummy electrode 2b. FIG. 14B shows a layer on which the internal electrode 6, which is an electrode other than the electrode for forming a capacitance, is provided. FIG. 14C shows a layer on which the internal electrode 2 is provided, which is an electrode for forming a capacitance. The internal electrode 2 has an extraction electrode portion 2a on the right side of the drawing of FIG. 14 (c). Further, in the layer in which the internal electrode 2 is provided, the dummy electrode 1b is provided at a position corresponding to the lead-out electrode portion 1a of the layer in which the internal electrode 1 is provided (left side in the drawing of FIG. 14C). Although the extraction electrode portion 2 a is electrically connected to the internal electrode 2, the dummy electrode 1 b is not electrically connected to the internal electrode 2. In addition, the external electrode 4 is formed on the dummy electrode 1 b.

As shown in FIG. 13A, in the multilayer capacitor 10d, the external electrode 4 is formed by forming the dummy electrode 1b, even if the distance A between the internal electrode 1 and the adjacent internal electrode 1 is the same. The distance C between the lead-out electrode portion 1a and the dummy electrode 1b becomes shorter than the distance A. Similarly, in the multilayer capacitor 10d, by forming the dummy electrode 2b, the lead-out electrode portion 2a and the dummy electrode in which the external electrode 5 is formed even if the distance A between the internal electrode 2 and the adjacent internal electrode 2 is the same. The distance C to 2 b is shorter than the distance A.

Therefore, in the multilayer capacitor 10d, the dummy electrode 1b and the lead-out electrode portion 1a, and the dummy electrode 2b and the lead-out electrode portion 2a at a distance C shorter than the distance A are shorted by plating. It becomes easy to form.

As described above, the multilayer capacitor 10d according to the fourth embodiment is provided at a position corresponding to the lead electrode portion 2a of the layer in which the internal electrode 1 is laminated, and is a dummy electrode 2b (first electrode isolated from the internal electrode 1). A dummy electrode) and a dummy electrode 1 b (second dummy electrode) provided at a position corresponding to the extraction electrode portion 1 a of the layer in which the internal electrode 2 is laminated and insulated from the internal electrode 2.

Therefore, in the multilayer capacitor 10d, the dummy electrodes 1b and 2b are formed, whereby the internal electrodes 1 and 2 shown in FIG. 5 and the dielectric ceramic layer 3 are alternately stacked in the horizontal direction in the figure. However, since the dummy electrode 1b and the lead-out electrode portions 1a, and the dummy electrode 2b and the lead-out electrode portion 2a are shorted by plating, the external electrodes 4 and 5 can be easily formed.

Fifth Embodiment
In the multilayer capacitor 10b according to the second embodiment, as shown in FIG. 5B, there is a gap B between the lead electrode portions 1a and 2a and the internal electrode 6, so that the magnetic flux T penetrating the gap B is It occurs (see FIG. 5 (a)). Therefore, in the fifth embodiment of the present invention, a configuration for preventing the generation of a magnetic flux passing through gap B will be described.

FIG. 15 is a schematic diagram for illustrating the configuration of the multilayer capacitor 10e according to the fifth embodiment of the present invention. 15 (a) is a plan view of the multilayer capacitor 10e as viewed from the surface on which the external electrodes 4 and 5 are formed, and FIG. 15 (b) is a front view of the multilayer capacitor 10e as viewed from the laminating direction. It shows. In the multilayer capacitor 10e shown in FIG. 15, the same components as those in the multilayer capacitor 10b shown in FIG. 5 are designated by the same reference numerals and their detailed description will not be repeated.

In the multilayer capacitor 10e, in order to prevent the magnetic flux from penetrating the gaps between the lead electrode portions 1a and 2a and the internal electrode 6, the shapes of the internal electrodes are made different by dividing into several blocks. Specifically, in the multilayer capacitor 10e, as shown in FIG. 15A, the internal electrodes 1, 2, and 6 may have different shapes by being divided into three blocks (first block B1 to third block B3). I'm sorry. Thus, in the multilayer capacitor 10e, the gap B penetrating in the stacking direction as shown in FIG. 5B does not occur (see FIG. 15B).

Next, the shapes of the internal electrodes 1, 2, and 6 in each block (first block B1 to third block B3) will be described. FIG. 16 is a schematic diagram for illustrating the shape of the internal electrode of the first block B1 of the multilayer capacitor 10e in accordance with the fifth embodiment of the present invention. FIG. 17 is a schematic diagram for illustrating the shape of the internal electrode of the second block B2 of the multilayer capacitor 10e in accordance with the fifth embodiment of the present invention. FIG. 18 is a schematic diagram for illustrating the shape of the internal electrode of the third block B3 of the multilayer capacitor 10e in accordance with the fifth embodiment of the present invention. In the multilayer capacitor 10e shown in FIGS. 16 to 18, the same components as those of the internal electrode shown in FIG. 6 are designated by the same reference numerals and their detailed description will not be repeated.

The internal electrode 1 of the first block B1 has a shape in which the width of the lead electrode portion 1a is wide as shown in FIG. 16 (a). Similarly, as shown in FIG. 16C, the internal electrode 2 of the first block B1 has a shape in which the width of the lead-out electrode portion 2a is wide. Therefore, as shown in FIG. 16B, the internal electrode 6 of the first block B1 is sandwiched between the wide lead-out electrode part 1a and the lead-out electrode part 2a, and has a narrow width. FIG. 16 (d) is a view in which the internal electrodes of FIGS. 16 (a) to 16 (c) are overlapped.

Next, as shown to Fig.17 (a), the internal electrode 1 of 2nd block B2 is a shape where the width | variety of the lead-out electrode part 1a is narrow. Similarly, as shown in FIG. 17C, the internal electrode 2 of the second block B2 has a shape in which the width of the lead-out electrode portion 2a is narrow. Further, the internal electrode 6 of the second block B2 has a narrow width as shown in FIG. 17 (b). FIG. 17 (d) is a diagram in which the internal electrodes of FIGS. 17 (a) to 17 (c) are overlapped.

Next, as shown to Fig.18 (a), the internal electrode 1 of 3rd block B3 is a shape where the width | variety of the extraction electrode part 1a is narrow. Similarly, as shown in FIG. 18C, the internal electrode 2 of the third block B3 has a shape in which the width of the lead-out electrode portion 2a is narrow. Therefore, as shown in FIG. 18B, the internal electrode 6 of the third block B3 is sandwiched between the narrow lead-out electrode 1a and the lead-out electrode 2a, and has a wide width. FIG. 18 (d) is a diagram in which the internal electrodes of FIGS. 18 (a) to 18 (c) are overlapped.

In the multilayer capacitor 10e, by laminating the first block B1 to the third block B3 in the order shown in FIG. 15A, the magnetic flux does not penetrate between the lead electrode portions 1a and 2a and the internal electrode 6 In addition, the conductor is disposed at a position perpendicular to the magnetic flux. In the multilayer capacitor 10e, an example has been described in which the shapes of the internal electrodes 1, 2, and 6 in each block (the first block B1 to the third block B3) are divided into a plurality of blocks. However, the multilayer capacitor may have a plurality of different shapes in each of the shapes of the extraction electrode portions 1 a and 2 a and the internal electrode 6. For example, in the multilayer capacitor 10e, the internal electrode 1 has a wide and narrow shape of the lead electrode portion 1a, the internal electrode 2 has a wide and narrow shape of the lead electrode portion 2a, and the internal electrode 6 has a wide width Each has a wide shape and a narrow shape. That is, by combining the internal electrodes having different shapes, it is possible to arrange the conductor at a position perpendicular to the magnetic flux so that the magnetic flux can not penetrate between the lead-out electrode portions 1a and 2a and the internal electrode 6 Good.

As described above, the multilayer capacitor 10e according to the fifth embodiment has different shapes from the plurality of internal electrodes 1 having different shapes of the lead electrode portion 1a and the plurality of inner electrodes 2 having different shapes of the lead electrode portion 2a. A plurality of internal electrodes 6 are stacked in combination. Therefore, in the multilayer capacitor 10e, a conductor perpendicular to the magnetic flux can be disposed so that the magnetic flux does not penetrate between the lead-out electrode portions 1a and 2a and the internal electrode 6. When a conductor perpendicular to the magnetic flux is disposed, an eddy current is generated in the conductor due to the magnetic flux. The generated eddy current generates a magnetic flux in the opposite direction to the magnetic flux penetrating between the lead-out electrode portions 1 a and 2 a and the internal electrode 6, thereby canceling out the magnetic flux and reducing the parasitic inductance.

(Other modifications)
(1) In the multilayer capacitor in accordance with the above-described embodiment, the dielectric constant of the dielectric layer sandwiched between the internal electrodes 1, 2 and the dielectric layer interposed between the internal electrodes 1, 2 and the internal electrode 6 Was described as being the same as the However, the present invention is not limited to this, and in the multilayer capacitor, the dielectric constant of the dielectric layer sandwiched between the internal electrode 6 and the internal electrodes 1 and 2 is the permittivity of the dielectric layer sandwiched between the internal electrodes 1 and 2 It may be configured to be smaller than.

FIG. 19 is a schematic diagram for explaining the configuration of the multilayer capacitor in accordance with the modification of the present invention. The multilayer capacitor 10f shown in FIG. 19 (a) has substantially the same configuration as the multilayer capacitor 10 shown in FIG. 1 (b). However, multilayer capacitor 10 f has a dielectric constant higher than dielectric ceramic layer 3 a sandwiched between internal electrodes 1 and 2 between internal electrode 6 and internal electrode 1 and between internal electrode 6 and internal electrode 2. The difference is that the small dielectric layer 3b is sandwiched. In the multilayer capacitor 10f, the configuration other than the dielectric layer 3b is the same as the configuration of the multilayer capacitor 10 shown in FIG. 1B, and therefore the detailed description will not be repeated.

The multilayer capacitor 10g shown in FIG. 19 (b) has substantially the same configuration as the multilayer capacitor 10b shown in FIG. 5 (b). However, the multilayer capacitor 10g has a smaller dielectric constant than the dielectric ceramic layer 3a sandwiched between the internal electrodes 1 and 2 between the internal electrodes 6 and the lead-out electrode portions 1a and 2a of the internal electrodes 1 and 2. It differs in that it sandwiches the body layer 3b. In multilayer capacitor 10g, the configuration other than dielectric layer 3b is the same as the configuration of multilayer capacitor 10b shown in FIG. 5 (b), and therefore the detailed description will not be repeated.

The multilayer capacitor 10h shown in FIG. 19 (c) has substantially the same configuration as the multilayer capacitor 10c shown in FIG. 10 (b). However, multilayer capacitor 10 h has a point in which dielectric layer 3 b having a smaller dielectric constant than dielectric ceramic layer 3 a sandwiched between internal electrodes 1 and 2 is interposed between internal electrode 6 and internal electrodes 1 and 2. It is different. In multilayer capacitor 10h, the configuration other than dielectric layer 3b is the same as the configuration of multilayer capacitor 10c shown in FIG. 10 (b), and therefore the detailed description will not be repeated.

In the multilayer capacitors 10f to 10h, the parasitic capacitance formed between the internal electrodes 1 and 2 and the internal electrode 6 can be reduced by reducing the dielectric constant of the dielectric layer 3b. When the parasitic capacitance is large, there is a problem that when the circuit module including the multilayer capacitors 10f to 10h is operated, charging and discharging to the parasitic capacitance occur to increase the power loss. Specifically, in the circuit diagram shown in FIG. 2, the parasitic capacitances of the multilayer capacitors are formed in parallel to the switching elements S1 and S2. Therefore, charging and discharging to the parasitic capacitance occur each time the switching elements S1 and S2 perform switching. Therefore, in the multilayer capacitors 10f to 10h, the above problem can be solved by reducing the parasitic capacitance formed between the internal electrodes 1, 2 and the internal electrode 6.

(2) Although the half bridge circuit has been described in the circuit module according to the above-described embodiment, the present invention is not limited to this, and any circuit may be used as long as a multilayer capacitor is mounted.

(3) In the multilayer capacitor in accordance with the above-described embodiment, as shown in FIG. 1B, even if the thickness of the internal electrode 6 is made thicker than the thicknesses of the internal electrode 1 and the internal electrode 2 in the stacking direction Good. By increasing the thickness of the internal electrode 6, the amount of current that can be supplied to the internal electrode 6 can be increased. In addition, since the internal electrodes 1 and 2 are respectively laminated by n layers, the sum of the thicknesses becomes n times the thickness of one internal electrode 1 and 2 and a large amount of current can flow. On the other hand, since only one internal electrode 6 is present on the upper side or lower side of the laminated body, it is necessary to make the thickness of one sheet thicker than the thickness of the internal electrodes 1 and 2 to ensure an amount of current flowable There is.

(4) In the multilayer capacitor in accordance with the above-described embodiment, as shown in FIG. 1B, the length of the internal electrode 6 is in the direction orthogonal to the laminating direction (left and right direction in FIG. 1B). The length may be longer than the length facing the internal electrodes 1 and 2. By lengthening the length of the internal electrode 6, the area of the electrode through which the eddy current flows increases, and the effect of canceling out the magnetic flux due to the current flowing through the internal electrodes 1 and 2 and the magnetic flux due to the eddy current flowing through the internal electrode 6 increases. .

(5) In the multilayer capacitor in accordance with the above-described embodiment, as shown in FIG. 5A, the internal electrode 6 is disposed inside the dielectric ceramic layer 3 in parallel to the electrode surface of the internal electrodes 1 and 2 The configuration formed by stacking has been described. However, the present invention is not limited to this configuration, and the internal electrode 6 may be provided inside the dielectric ceramic layer 3 as long as it does not overlap the lead electrode portion 1 a and the lead electrode portion 2 a when viewed in the stacking direction. It may be shaped. For example, the internal electrode 6 may have a rectangular parallelepiped shape extending in the stacking direction between the extraction electrode portion 1 a and the extraction electrode portion 2 a. By making the shape of the internal electrode 6 into a rectangular solid (a lump of metal), the resistance value of the internal electrode 6 decreases, and eddy current easily flows.

It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is indicated not by the above description but by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

1, 2, 6 internal electrodes, 1a, 2a lead electrode portions, 1b, 2b dummy electrodes, 3 dielectric ceramic layers, 3a dielectric layers, 4, 5 external electrodes, 10 multilayer capacitors, 20 substrates, 100 circuit modules.

Claims (14)

1. A stacked body in which first internal electrodes and second internal electrodes are alternately stacked with a dielectric layer interposed therebetween;
   A first external electrode electrically connected to the first internal electrode;
   A second external electrode electrically connected to the second internal electrode;
   At least one third internal electrode which is laminated on the laminate and is not electrically connected to the first external electrode and the second external electrode;
   The third inner electrode is provided at a position where an eddy current is generated by a current flowing between the first outer electrode and the second outer electrode, and an outer electrode electrically connected from the outside of the laminate is provided. Not a laminated capacitor.
2. The multilayer capacitor according to claim 1, wherein the third inner electrode is stacked on the multilayer body in parallel to the first inner electrode or the second inner electrode.
3. The distance between the third internal electrode and the first internal electrode or the second internal electrode is equal to the distance between the first internal electrode and the second internal electrode. Multilayer capacitors.
4. The multilayer capacitor according to any one of claims 1 to 3, wherein an electrode material of the third inner electrode is the same as an electrode material of the first inner electrode and the second inner electrode.
5. The dielectric constant of the dielectric layer sandwiched between the first internal electrode or the second internal electrode and the third internal electrode is equal to that of the dielectric interposed between the first internal electrode and the second internal electrode. The multilayer capacitor according to any one of claims 1 to 4, which is smaller than the dielectric constant of a layer.
6. The first external electrode is formed on a first side of the laminate,
   The multilayer capacitor according to any one of claims 1 to 5, wherein the second external electrode is formed on a second side surface of the multilayer body facing the first side surface.
7. The first external electrode and the second external electrode are respectively formed on a single surface of the laminate perpendicular to the first internal electrode and the second internal electrode. The multilayer capacitor according to any one of the above.
8. The multilayer capacitor according to claim 6, wherein the third inner electrode is formed on the same surface side of the multilayer body as at least a part of the first outer electrode and the second outer electrode.
9. The multilayer capacitor according to claim 7, wherein the third inner electrode is formed on the surface side of the multilayer body facing the surface of the multilayer body on which the first outer electrode and the second outer electrode are formed.
10. The first internal electrode is a portion not facing the second internal electrode, and has a first lead-out portion for connecting to the first external electrode.
    The second internal electrode is a portion not facing the first internal electrode, and has a second lead-out portion for connecting to the second external electrode.
    The third internal electrode is
    Laminated on a layer of the laminate between the first internal electrode and the second internal electrode,
    8. The display device according to claim 7, wherein the first internal electrode and the second internal electrode are disposed so as not to overlap with the first internal electrode and the second internal electrode, as viewed in the stacking direction. Multilayer capacitors.
11. The laminate is
    A first dummy electrode provided at a position corresponding to the second lead-out portion of the layer in which the first inner electrode is stacked, and insulated from the first inner electrode;
    The multilayer capacitor according to claim 10, further comprising: a second dummy electrode provided at a position corresponding to the first lead-out portion of the layer in which the second inner electrode is stacked, and insulated from the second inner electrode.
12. The laminate is
    A plurality of first internal electrodes different in shape of the first lead-out portion;
    A plurality of second internal electrodes different in shape of the second lead-out portion;
    The multilayer capacitor according to claim 10, wherein the plurality of third internal electrodes having different shapes are combined and stacked.
13. The multilayer capacitor according to any one of claims 1 to 12, wherein a shape of the third inner electrode is a rectangular solid.
14. The multilayer capacitor according to any one of claims 1 to 13.
    And a wiring board on which the multilayer capacitor is mounted.

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