JPH08273971A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH08273971A
JPH08273971A JP7169695A JP7169695A JPH08273971A JP H08273971 A JPH08273971 A JP H08273971A JP 7169695 A JP7169695 A JP 7169695A JP 7169695 A JP7169695 A JP 7169695A JP H08273971 A JPH08273971 A JP H08273971A
Authority
JP
Japan
Prior art keywords
electrode
layer
ceramic capacitor
internal
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7169695A
Other languages
Japanese (ja)
Inventor
Hikoharu Okuyama
彦治 奥山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7169695A priority Critical patent/JPH08273971A/en
Publication of JPH08273971A publication Critical patent/JPH08273971A/en
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE: To improve the insulation breakdown voltage value of a laminated ceramic capacitor for middle/high voltages and to reduce its scattering. CONSTITUTION: A sharp part is provided on opposite sides of inner electrodes 2a and 2b which oppose with a certain distance within the same plane, the concentration of electric field is induced at this part when a high voltage is applied so that insulation breakdown constantly occurs from this part, thus suppressing the scattering of the insulation breakdown voltage and simultaneously improving level.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は積層セラミックコンデン
サに関するものであり、特に高い耐電圧が要求される中
高圧用積層セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor, and more particularly to a monolithic ceramic capacitor for medium and high voltage which requires a high withstand voltage.

【0002】[0002]

【従来の技術】一般的な積層セラミックコンデンサは、
セラミックグリーンシートとセラミックグリーンシート
上に内部電極を形成したシートを内部電極層が一定寸法
交互にずれるように積み重ねて圧着させた後、所望形状
のチップに切断し、得られた積層体を焼成後、焼結体の
両端部に現れる内部電極を外部電極と接続することで作
製し、その構成は個々のコンデンサが並列に接続された
形になっている。
2. Description of the Related Art A general monolithic ceramic capacitor is
After stacking the ceramic green sheets and sheets with internal electrodes formed on the ceramic green sheets so that the internal electrode layers are alternately displaced by a certain size and crimping, cutting into chips of the desired shape and firing the obtained laminated body It is manufactured by connecting the internal electrodes appearing at both ends of the sintered body to the external electrodes, and the structure is such that individual capacitors are connected in parallel.

【0003】一方、中高圧用積層セラミックコンデンサ
(特に、1KV級以上)においては、絶縁耐圧を向上さ
せるために、図6にその断面図を示すように、端部が外
部電極4a,4bに接続されている内部電極2a,2b
(以下、対向電極と記す)と、端部が外部電極4a,4
bに接続されずかつ上記対向電極層のそれぞれに重なる
ような内部電極層3(以下、浮遊電極と記す)とを誘電
体層1を介して交互に配置させることで1層当たりに加
わる電界強度が実質的に半減される直列型の積層構造に
することが一般的な手段として行われている。
On the other hand, in a medium- and high-voltage monolithic ceramic capacitor (particularly 1 KV class or higher), in order to improve the withstand voltage, the ends are connected to the external electrodes 4a and 4b as shown in the sectional view of FIG. Internal electrodes 2a, 2b
(Hereinafter referred to as a counter electrode), the end portions are external electrodes 4a, 4
The internal electrode layers 3 (hereinafter, referred to as floating electrodes) which are not connected to b and overlap with each of the counter electrode layers are alternately arranged with the dielectric layer 1 interposed therebetween, so that the electric field strength applied per layer is increased. Is generally used as a general means.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記の構
成では、高電圧下で誘電体の絶縁破壊が生じる時、破壊
発生箇所がセラミック焼結体の微構造に大きく左右され
ることから破壊箇所が特定せず結果的には絶縁耐圧が大
きくばらつき、製造・品質上の問題となる。
However, in the above configuration, when dielectric breakdown of the dielectric occurs under high voltage, the location of the breakdown is greatly influenced by the microstructure of the ceramic sintered body, so that the location of the breakdown is specified. As a result, the withstand voltage greatly varies, which causes problems in manufacturing and quality.

【0005】そこで本発明は上記問題点に鑑み、絶縁破
壊電圧のばらつきを抑制した高品質の中高圧用積層セラ
ミックコンデンサを提供しようとするものである。
In view of the above problems, the present invention is intended to provide a high-quality medium- and high-voltage monolithic ceramic capacitor in which variations in dielectric breakdown voltage are suppressed.

【0006】[0006]

【課題を解決するための手段】そこで本発明の積層セラ
ミックコンデンサは、第1の内部電極層と第2の内部電
極層とを誘電体層を介して交互に対向するように積層し
た積層体と、この積層体の端面に設けた外部電極とを備
え、前記第1の内部電極層は2つの内部電極からなり、
この2つの内部電極は前記誘電体層表面において距離を
おいて対向し、それぞれ一端側が前記外部電極に接続す
るように形成されたもので、前記第1の内部電極層のう
ち少なくとも1層において、2つの内部電極が対向する
側の端部に少なくとも1個以上の尖鋭部を有し、前記第
2の内部電極層は端部が前記外部電極に接続されずかつ
前記誘電体層の端部に至らないように設けたものであ
る。
Therefore, a laminated ceramic capacitor of the present invention comprises a laminated body in which a first internal electrode layer and a second internal electrode layer are laminated so as to alternately face each other with a dielectric layer interposed therebetween. And an external electrode provided on an end surface of the laminated body, wherein the first internal electrode layer includes two internal electrodes,
The two internal electrodes face each other at a distance on the surface of the dielectric layer and are formed so that one ends thereof are connected to the external electrode, and at least one layer of the first internal electrode layers is The two internal electrodes have at least one sharp portion at the end portion on the opposite side, and the second internal electrode layer has an end portion not connected to the external electrode and an end portion of the dielectric layer. It is provided so that it does not reach.

【0007】[0007]

【作用】この構成によって、高電圧印加時には対向電極
上に設けた尖鋭部に電界集中が誘起され、その結果絶縁
破壊は常にこの部位が起点となるように発生するため、
破壊箇所が特定され絶縁破壊電圧のばらつきを抑制する
ことが可能となる。
With this configuration, when a high voltage is applied, electric field concentration is induced in the sharp portion provided on the counter electrode, and as a result, dielectric breakdown always occurs at this point as the starting point.
It is possible to specify the breakdown point and suppress variations in the dielectric breakdown voltage.

【0008】[0008]

【実施例】【Example】

(実施例1)以下、本発明の一実施例について図面を参
照しながら説明する。まず、本実施例で用いた対向電極
2a,2bの形状を図1(a)に、中央部に配置される
浮遊電極3の形状を図1(b)に平面図として示した。
また、誘電体層1は誘電体スラリーを作製しリバースロ
ールコータによりキャリアフィルム上に厚み100μm
のグリーンシートを成形して作製した。
(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. First, the shapes of the counter electrodes 2a and 2b used in this example are shown in FIG. 1A, and the shape of the floating electrode 3 disposed in the central portion is shown in FIG. 1B as a plan view.
For the dielectric layer 1, a dielectric slurry is prepared and a reverse roll coater is used to form a 100 μm thick film on the carrier film.
Was prepared by molding.

【0009】次に、上記グリーンシート上にパラジウム
を主成分とする市販ペーストを用いてスクリーン印刷法
により、図1(a)及び(b)に示される形状の内部電
極2a,2b,3をそれぞれ所定の数量形成し、さらに
このグリーンシートを積層に供される所定の大きさに切
断した。
Next, the internal electrodes 2a, 2b and 3 having the shapes shown in FIGS. 1 (a) and 1 (b) are respectively formed on the green sheet by screen printing using a commercially available paste containing palladium as a main component. A predetermined quantity was formed, and this green sheet was cut into a predetermined size to be laminated.

【0010】次に、積層用のパレットを用意し、図4に
概略の構成を示したように、内部電極2a,2b,3が
印刷されていないグリーンシートを所定枚数積層して予
めコンデンサの静電容量に関与しない下部層5を作製し
た後、この上に図1(a)及び(b)に示す内部電極2
a,2b,3を形成したグリーンシートをキャリアフィ
ルムから剥離した状態で、加熱圧着により交互に所定枚
数積層し、最後に下部層5と同等のコンデンサの静電容
量に関与しない上部層6を形成して積層成形体を作製し
た。
Next, a pallet for lamination is prepared, and a predetermined number of green sheets on which the internal electrodes 2a, 2b and 3 are not printed are laminated as shown in the schematic construction of FIG. After forming the lower layer 5 that does not contribute to the capacitance, the internal electrode 2 shown in FIGS.
The green sheets on which a, 2b and 3 are formed are peeled from the carrier film, and a predetermined number of layers are alternately laminated by thermocompression bonding, and finally the upper layer 6 which is equivalent to the lower layer 5 and does not contribute to the capacitance of the capacitor is formed. Then, a laminated molded body was produced.

【0011】次に、上記積層成形体を所望のチップ状に
切断し、電気炉内で有機バインダの脱脂のため350℃
で途中5時間保持した後、1300℃で2時間焼成し
た。焼成後、得られた素子の内部電極2a,2bが露出
した端面に図6に示すように銀を主成分とする外部電極
4a,4bを形成し、積層セラミックコンデンサを作製
した。
Next, the above-mentioned laminated molded body is cut into a desired chip shape and 350 ° C. for degreasing the organic binder in an electric furnace.
After being held for 5 hours on the way, it was baked at 1300 ° C. for 2 hours. After firing, external electrodes 4a and 4b containing silver as a main component were formed on the exposed end faces of the internal electrodes 2a and 2b of the device, as shown in FIG. 6, to produce a laminated ceramic capacitor.

【0012】尚、比較例として、図1(a)に示した対
向電極2a,2bの代わりに図5に示すパターンの対向
電極10a,10bを用いて、図1(b)に示した浮遊
電極3と合わせて上記と全く同様にして積層セラミック
コンデンサを作製し従来品の試料とした。
As a comparative example, the counter electrodes 10a and 10b having the pattern shown in FIG. 5 are used instead of the counter electrodes 2a and 2b shown in FIG. 1A, and the floating electrode shown in FIG. A multilayer ceramic capacitor was manufactured in the same manner as described above in combination with No. 3 and used as a sample of a conventional product.

【0013】こうして得られた2種類の積層セラミック
コンデンサについて、直流での昇圧破壊試験を行い、絶
縁破壊電圧をサンプル数各100個について測定した。
その平均値と標準偏差の結果を(表1)に示す。
The two types of monolithic ceramic capacitors thus obtained were subjected to a DC breakdown test, and the dielectric breakdown voltage was measured for each 100 samples.
The results of the average value and standard deviation are shown in (Table 1).

【0014】[0014]

【表1】 [Table 1]

【0015】(表1)を見て明らかなように、本発明品
では絶縁破壊電圧のばらつきが非常に小さくなってお
り、かつレベルの向上も図られている。これについては
破壊後の試料の内部観察を行った結果、従来品では対向
電極10a,10bと浮遊電極3との間の誘電体層1で
3次元的に亀裂が走っていたのに対して、本発明品では
対向する電極2a,2bどうしの面内で破壊が集中して
いた。つまり、本発明による意図的な電界集中によっ
て、コンデンサを形成している誘電体層1よりも厚みの
大きい対向電極2a,2b間の面内で破壊を発生させる
ことに成功した結果、絶縁破壊電圧が向上したものと考
えられる。
As is apparent from Table 1, the product of the present invention has a very small variation in the dielectric breakdown voltage, and the level is improved. Regarding this, as a result of observing the inside of the sample after destruction, in the conventional product, a crack was running three-dimensionally in the dielectric layer 1 between the counter electrodes 10a and 10b and the floating electrode 3, whereas In the product of the present invention, the breakage was concentrated in the plane of the electrodes 2a and 2b facing each other. That is, by intentionally concentrating the electric field according to the present invention, it has succeeded in causing breakdown in the plane between the counter electrodes 2a and 2b having a larger thickness than the dielectric layer 1 forming the capacitor, and as a result, the breakdown voltage Is considered to have improved.

【0016】(実施例2)以下、本発明の第2の実施例
について図面を参照しながら説明する。第1の実施例で
は、対向電極2a,2b用パターンとして図1(a)に
示す形状を使用したが、この実施例では図2に示すよう
に、対向する辺の両側に図1(a)と同等の尖鋭部を対
称位置に設けている点が第1の実施例と異なっている。
尚、浮遊電極3の形状は図1(b)と同じである。また
積層セラミックコンデンサを作製するに至る製造方法お
よび比較のための試料は上記第1の実施例と同様であ
る。
(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the pattern shown in FIG. 1A was used as the pattern for the counter electrodes 2a and 2b, but in this embodiment, as shown in FIG. 2, the pattern shown in FIG. The difference from the first embodiment is that sharp points equivalent to the above are provided at symmetrical positions.
The shape of the floating electrode 3 is the same as that in FIG. The manufacturing method for manufacturing the laminated ceramic capacitor and the sample for comparison are the same as those in the first embodiment.

【0017】こうして得られた積層セラミックコンデン
サを用いて実施例1と全く同様にして絶縁破壊電圧を測
定した結果を(表2)に示す。
The results of measuring the dielectric breakdown voltage using the thus obtained monolithic ceramic capacitor in the same manner as in Example 1 are shown in Table 2.

【0018】[0018]

【表2】 [Table 2]

【0019】この場合も実施例1と同様に、絶縁破壊電
圧値の向上及びばらつきの低減が達成されていることが
わかる。また、破壊した試料の内部観察結果も第1の実
施例と同様の傾向を示していた。
In this case as well, it is understood that the improvement of the dielectric breakdown voltage value and the reduction of the variation are achieved as in the first embodiment. Further, the internal observation result of the destroyed sample also showed the same tendency as in the first embodiment.

【0020】(実施例3)以下、本発明の第3の実施例
について図面を参照しながら説明する。第1及び第2の
実施例では、対向する内部電極層用パターンとして図1
(a)及び図2に示すように対向する両辺に尖鋭部を設
けたが、この実施例では図3に示すように、対向する辺
の片方にのみこれまでと同等の尖鋭部を設けて不平等電
界を現出している点が異なっている。
(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings. In the first and second embodiments, the internal electrode layer patterns facing each other are shown in FIG.
As shown in (a) and FIG. 2, sharp portions are provided on both sides facing each other, but in this embodiment, as shown in FIG. 3, a sharp portion equivalent to the conventional one is provided on only one of the facing sides. They differ in that they show an equal electric field.

【0021】尚、浮遊電極3の形状、積層セラミックコ
ンデンサを作製するに至る製造方法および比較のための
試料はすべて上記第1の実施例と同様である。
The shape of the floating electrode 3, the manufacturing method for manufacturing the laminated ceramic capacitor, and the sample for comparison are all the same as those in the first embodiment.

【0022】こうして得られた積層セラミックコンデン
サを用いて実施例1と全く同様にして絶縁破壊電圧を測
定した結果を(表3)に示す。
The results of measuring the dielectric breakdown voltage using the thus-obtained monolithic ceramic capacitor in exactly the same manner as in Example 1 are shown in Table 3.

【0023】[0023]

【表3】 [Table 3]

【0024】この(表3)からも明らかなように、本発
明品では絶縁破壊電圧が向上し、そのばらつきを低減す
ることができた。
As is clear from this (Table 3), in the product of the present invention, the dielectric breakdown voltage was improved and its variation could be reduced.

【0025】なお、実施例1〜3においては、各対向電
極を形成したすべての層において少なくとも1個以上の
尖鋭部を設けたが、1層以上の対向電極において少なく
とも1個以上の尖鋭部を設けることにより、絶縁破壊電
圧値のばらつきを抑制し同時にレベルを向上させること
が可能である。
In each of the first to third embodiments, at least one sharp portion is provided in all layers in which each counter electrode is formed, but at least one sharp portion is provided in one or more layers of counter electrodes. By providing it, it is possible to suppress the variation in the dielectric breakdown voltage value and improve the level at the same time.

【0026】また、内部電極層において対向電極2a,
2bを形成した層が下部層5および上部層6側にくるよ
うに、対向電極2a,2bと浮遊電極3とを誘電体層1
を介して交互に積層する方が望ましい。
In the internal electrode layer, the counter electrodes 2a,
The counter electrodes 2a and 2b and the floating electrode 3 are connected to the dielectric layer 1 so that the layer on which the layer 2b is formed is located on the lower layer 5 and upper layer 6 sides.
It is preferable to alternately stack the layers.

【0027】[0027]

【発明の効果】以上のように本発明では、同一面内で一
定距離をおいて対向する内部電極の対向する辺上に尖鋭
部を設け、高電圧印加時にこの部分に電界集中を誘起さ
せ絶縁破壊が常にこの部位から発生するように特定して
やることで絶縁破壊電圧値のばらつきを抑制し、同時に
レベルの向上も達成することが可能となった。
As described above, according to the present invention, the sharp portions are provided on the opposite sides of the internal electrodes facing each other at a constant distance in the same plane, and when a high voltage is applied, electric field concentration is induced in these portions and insulation is performed. By specifying that the breakdown always occurs from this part, it is possible to suppress the variation in the dielectric breakdown voltage value and at the same time improve the level.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)本発明の第1の実施例における内部電極
の平面図 (b)本発明の第1の実施例における内部電極の平面図
FIG. 1A is a plan view of an internal electrode according to a first embodiment of the present invention. FIG. 1B is a plan view of an internal electrode according to a first embodiment of the present invention.

【図2】本発明の第2の実施例における内部電極の平面
FIG. 2 is a plan view of internal electrodes according to a second embodiment of the present invention.

【図3】本発明の第3の実施例における内部電極の平面
FIG. 3 is a plan view of internal electrodes according to a third embodiment of the present invention.

【図4】本発明の一実施例における積層形成体の分解斜
視図
FIG. 4 is an exploded perspective view of a laminated body according to an embodiment of the present invention.

【図5】従来の内部電極の平面図FIG. 5 is a plan view of a conventional internal electrode.

【図6】一般的な中高圧用積層セラミックコンデンサの
断面図
FIG. 6 is a cross-sectional view of a general medium / high voltage monolithic ceramic capacitor.

【符号の説明】[Explanation of symbols]

1 誘電体層 2a 対向電極 2b 対向電極 3 浮遊電極 4a 外部電極 4b 外部電極 1 Dielectric Layer 2a Counter Electrode 2b Counter Electrode 3 Floating Electrode 4a External Electrode 4b External Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1の内部電極層と第2の内部電極層と
を誘電体層を介して交互に対向するように積層した積層
体と、この積層体の端面に設けた外部電極とを備え、前
記第1の内部電極層は2つの内部電極からなり、この2
つの内部電極は前記誘電体層表面において距離をおいて
対向し、それぞれ一端側が前記外部電極に接続するよう
に形成されたもので、前記第1の内部電極層のうち少な
くとも1層において、2つの内部電極が対向する側の端
部に少なくとも1個以上の尖鋭部を有し、前記第2の内
部電極層は端部が前記外部電極に接続されずかつ前記誘
電体層の端部に至らないように設けた積層セラミックコ
ンデンサ。
1. A laminated body in which a first internal electrode layer and a second internal electrode layer are laminated so as to alternately face each other with a dielectric layer in between, and an external electrode provided on an end face of the laminated body. And the first internal electrode layer is composed of two internal electrodes.
Two internal electrodes are formed so as to face each other at a distance on the surface of the dielectric layer, and one end sides thereof are connected to the external electrode, and two internal electrodes are provided in at least one layer of the first internal electrode layers. The inner electrode has at least one sharp portion at the end on the opposite side, and the end of the second inner electrode layer is not connected to the outer electrode and does not reach the end of the dielectric layer. Multilayer ceramic capacitor provided in this way.
JP7169695A 1995-03-29 1995-03-29 Laminated ceramic capacitor Pending JPH08273971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7169695A JPH08273971A (en) 1995-03-29 1995-03-29 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7169695A JPH08273971A (en) 1995-03-29 1995-03-29 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH08273971A true JPH08273971A (en) 1996-10-18

Family

ID=13467975

Family Applications (1)

Application Number Title Priority Date Filing Date
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2478639A (en) * 2010-03-08 2011-09-14 Paul Lenworth Mantock High energy storage capacitor.
JP2012156472A (en) * 2011-01-28 2012-08-16 Murata Mfg Co Ltd Electronic component and substrate module
CN103531356A (en) * 2013-09-29 2014-01-22 广东风华高新科技股份有限公司 Preparation method for safety chip type multilayer ceramic capacitors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2478639A (en) * 2010-03-08 2011-09-14 Paul Lenworth Mantock High energy storage capacitor.
GB2478639B (en) * 2010-03-08 2014-11-05 Paul Lenworth Mantock An Interactive Electrostatic Field High Energy Storage AC Blocking Capacitor
JP2012156472A (en) * 2011-01-28 2012-08-16 Murata Mfg Co Ltd Electronic component and substrate module
CN103531356A (en) * 2013-09-29 2014-01-22 广东风华高新科技股份有限公司 Preparation method for safety chip type multilayer ceramic capacitors

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