JPH09305158A - Dot clock generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain video in which quality is not degraded by controlling a phase of a reference horizontal synchronizing signal and generating a dot clock with an appropriate phase for a video signal. SOLUTION: An output signal of a capacitor 11 to which DC voltage generated by a D/A converter 12 is given is inputted to a buffer 13, and a reference horizontal synchronizing signal is outputted. DC voltage varied continuously is given from the D/A converter 12, and a phase of the reference horizontal synchronizing signal is continuously varied by using a thrust level of the buffer. Next, the reference horizontal synchronizing signal and a horizontal pulse for comparison are inputted to a PLL circuit 14, the horizontal pulse for comparison is locked to the reference horizontal synchronizing signal, and a dot clock which is synchronized with the reference horizontal synchronizing signal and of which one horizontal period is frequencydivided with a frequency-division ratio set by a counter 15 is generated. Next, the number of dot clock of one horizontal period is set to the counter 15 as the frequency-division ratio, numbers are counted by a dot clock generated by the PLL circuit 14, and a horizontal pulse for comparison is generated for each frequency-division ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot clock generator which always generates a dot clock in an appropriate phase with respect to a video signal when A / D converting the video signal from a computer or the like and processing the signal. is there.

[0002]

2. Description of the Related Art A video signal from a computer or the like is subjected to digital signal processing and then D / A converted to obtain an analog RGB signal.
Is output. However, this RGB video signal is
Since it is an analog signal generated by A conversion, it is a signal whose signal level changes every dot clock used when digital signal processing is performed in the previous stage.

The present invention relates to a dot clock generator for generating a dot clock at an appropriate phase with respect to an analog video signal when the analog video signal of the computer or the like is again A / D converted and signal-processed. .

A conventional dot clock generator will be described below with reference to the drawings. FIG. 5 is a block diagram of a conventional dot clock generator, and FIG. 6 is an operation waveform diagram for explaining the operation of the conventional dot clock generator.

In FIG. 5, a reference numeral 51 inputs a horizontal synchronizing signal and a comparison horizontal pulse output from a counter 52, which will be described later, is phase-synchronized with the horizontal synchronizing signal, and has a frequency division ratio set by the counter 52 of 1 horizontal. It is a PLL circuit that generates a dot clock whose frequency is divided. 52 is a PLL circuit 51
It is a counter that counts the number with the dot clock generated in 1. and generates a comparison horizontal pulse for each set division ratio.

The operation of the dot clock generator will be described below. First, the horizontal synchronizing signal and the comparison horizontal pulse output from the counter 52 are input to the PLL circuit 51, the comparison horizontal pulse is locked to the horizontal synchronizing signal, and the counter 52 is set in phase synchronization with the horizontal synchronizing signal. A dot clock is generated by dividing one horizontal period by the division ratio. Next, the number of dot clocks in one horizontal period is set in the counter 52 as a frequency division ratio, the number is counted by the dot clock generated in the PLL circuit 51, and a horizontal pulse for comparison is generated for each frequency division ratio.

[0007]

However, in the above-described conventional configuration, the phase of the dot clock cannot be adjusted with respect to the video signal. Therefore, the video signal of a computer or the like is A / D-converted to obtain a signal. At the time of processing, there is a problem that a change point of a video signal is sampled, resulting in an image with many latch errors.

[0008]

In order to solve the above-mentioned problems, the dot clock generator of the present invention controls the phase of a reference horizontal synchronizing signal input to a PLL so that a dot is generated at an appropriate phase with respect to a video signal. It is characterized by generating a clock.

According to the present invention, since the dot clock is generated in an appropriate phase with respect to the video signal, when the video signal of a computer or the like is A / D converted and signal processed, proper sampling is performed to deteriorate the image quality. You can get images without.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a dot clock generator for generating a dot clock for various video signals when inputting various video signals, converting analog signals into digital signals, and performing signal processing, It is characterized in that the phase of the reference horizontal synchronizing signal is controlled and the dot clock is generated with respect to the video signal in a phase that does not sample the change point of the video signal. This has the effect that a dot clock can be generated.

According to the present invention, a capacitor for inputting a horizontal synchronizing signal to remove a DC voltage, a D / A converter for applying a DC voltage to the output signal of the capacitor, and a reference horizontal signal by shaping the output signal of the capacitor. A buffer for outputting a sync signal; a PLL circuit for inputting the reference horizontal sync signal and a comparison horizontal pulse to generate a dot clock;
A reference for operating a DC clock of a capacitor output signal by a D / A converter, which is provided with a counter that operates by the dot clock to generate the comparison horizontal pulse. It has an effect that the phase of the horizontal synchronizing signal can be adjusted and the PLL circuit can be adjusted to generate the dot clock at an appropriate phase.

According to the present invention, instead of the D / A converter in the above invention, a phase difference detection for inputting a horizontal synchronizing signal and a reference horizontal synchronizing signal and detecting a phase difference between the horizontal synchronizing signal and the reference horizontal synchronizing signal. And a reference horizontal synchronization input from the phase difference between the horizontal synchronization signal and the reference horizontal synchronization signal to the PLL circuit. Feedback is applied so as to control the DC voltage applied to the output signal of the capacitor so as to stabilize the phase of the signal, and the PLL circuit can generate a dot clock at an appropriate phase at all times.

An example of an embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a dot clock generator showing an embodiment of the present invention. FIG.
FIG. 6 is an operation waveform diagram for explaining the operation of the dot clock generator according to the embodiment of the present invention.

In FIG. 1, reference numeral 11 is a capacitor which receives the horizontal synchronizing signal, removes the DC voltage of the horizontal synchronizing signal, and extracts only the AC voltage. 12 is a capacitor 1
1 is a D / A converter for applying a DC voltage to the output signal of No. 1. Reference numeral 13 is a buffer that waveform-shapes the output signal of the capacitor 11 and outputs a reference horizontal synchronizing signal. 14 is
It is a PLL circuit that inputs a reference horizontal synchronizing signal and a horizontal pulse for comparison, which will be described later, and generates a dot clock. Fifteen
Is a counter that operates by the dot clock generated in the PLL circuit and generates a horizontal pulse for comparison.

The operation of the dot clock generator configured as described above will be described below with reference to FIGS. 1 and 2.

First, the horizontal synchronizing signal is input to the capacitor 11, the DC voltage of the horizontal synchronizing signal is removed, and only the AC voltage is taken out. Next, the D / A converter 12 gives a continuously varying DC voltage to the output signal of the capacitor 11. Next, the output signal of the capacitor 11 to which the DC voltage generated by the D / A converter 12 is applied is input to the buffer 13, and the output signal of the capacitor 11 is input to the buffer 13.
If the voltage is lower than the input slice level of, the reference horizontal synchronizing signal of the Low level is output, and if the voltage is higher than the input slice level, the reference horizontal synchronizing signal is output. A DC voltage that continuously changes is applied from the D / A converter 12, and the slice level of the buffer is used to continuously change the phase of the reference horizontal synchronization signal.

Next, the reference horizontal synchronizing signal and the comparison horizontal pulse are input to the PLL circuit 14, the comparison horizontal pulse is locked to the reference horizontal synchronizing signal, the phase is synchronized with the reference horizontal synchronizing signal and set by the counter 15. The dot clock is generated by dividing one horizontal period by the division ratio. Next, counter 1
The number of dot clocks in one horizontal period is set to 5 as the frequency division ratio, the number is counted by the dot clock generated in the PLL circuit 14, and the comparison horizontal pulse is generated for each frequency division ratio.

As described above, the phase of the dot clock is based on the phase of the reference horizontal synchronizing signal. In the present invention, by controlling the DC voltage of the input signal of the buffer 13 by the D / A converter 12, the rising and falling phases of the reference horizontal synchronizing signal are controlled, and the A / D conversion is performed in a phase in which the video signal is flat. It can be adjusted to generate a dot clock that

(Second Embodiment) FIG. 3 is a block diagram of a dot clock generator showing an embodiment of the present invention. In addition, FIG. 4 is an operation waveform diagram for explaining the operation of the dot clock generator according to the third embodiment of the present invention.

In FIG. 3, reference numeral 31 is a capacitor which receives the horizontal synchronizing signal, removes the DC voltage of the horizontal synchronizing signal, and extracts only the AC voltage. Reference numeral 32a is a phase difference detection circuit that receives a horizontal synchronization signal and a reference horizontal synchronization signal, which will be described later, and detects a phase difference between the horizontal synchronization signal and the reference horizontal synchronization signal. Reference numeral 32b is an integrating circuit that integrates the phase difference to generate a DC voltage and applies the DC voltage to the output signal of the capacitor. Reference numeral 33 is a buffer for shaping the output signal of the capacitor 31 and outputting a reference horizontal synchronizing signal. 34
Is a PLL circuit that receives a reference horizontal synchronizing signal and a comparison horizontal pulse output from a counter 35, which will be described later, and generates a dot clock. Reference numeral 35 is a counter that operates by the dot clock generated by the PLL circuit 34 and generates a horizontal pulse for comparison.

The operation of the dot clock generator configured as described above will be described below with reference to FIGS. 3 and 4.

The PLL circuit 34 locks the trailing edge of the comparison horizontal pulse with the trailing edge of the reference horizontal synchronizing signal.

First, the horizontal synchronizing signal is input to the capacitor 31, the DC voltage of the horizontal synchronizing signal is removed, and only the AC voltage is taken out.

Next, the horizontal synchronizing signal and the reference horizontal synchronizing signal are input to the phase difference detecting circuit 32a to detect the falling phase difference between the horizontal synchronizing signal and the reference horizontal synchronizing signal.

Next, the phase difference is input to the integrating circuit 32b and the phase difference is integrated to generate a DC voltage.
A DC voltage is applied to the 1 output signal. Next, the buffer 33
To the output signal of the capacitor 31 to which the DC voltage generated by the integrating circuit 32b is applied, and when the output signal of the capacitor 31 is a voltage lower than the input slice level of the buffer 33, a Low level, and a high voltage is a High level. It outputs a reference horizontal sync signal.

Next, the reference horizontal synchronizing signal and the comparison horizontal pulse output from the counter 35 are input to the PLL circuit 34, the comparison horizontal pulse is locked to the reference horizontal synchronizing signal, and the phase is synchronized with the reference horizontal synchronizing signal. Then, a dot clock obtained by dividing one horizontal period by the division ratio set by the counter 35 is generated.

Next, the number of dot clocks in one horizontal period is set in the counter 35 as a frequency division ratio, the number is counted by the dot clock generated in the PLL circuit 34, and a horizontal pulse for comparison is generated for each frequency division ratio. To do.

As described above, in the present invention, the phase difference detection circuit 32a and the integration circuit 32b integrate the phase difference between the horizontal synchronizing signal and the reference horizontal synchronizing signal to generate a DC voltage, and the DC signal of the input signal of the buffer 33 is generated. When the phase of the reference horizontal synchronizing signal is changed by controlling the voltage, feedback control is performed so as to return to the original phase, the temperature characteristic of the circuit is canceled, and the video signal is always in a flat phase. A dot clock for D / D conversion can be generated.

[0029]

As described above, according to the present invention, since the phase of the reference horizontal synchronizing signal is controlled and the dot clock is generated at an appropriate phase with respect to the video signal, the video signal of a computer or the like is A / D converted. Appropriate sampling can be performed during signal processing to obtain an image without latch errors.

[Brief description of drawings]

FIG. 1 is a block diagram of a dot clock generator showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram for explaining the operation of the circuit.

FIG. 3 is a block diagram of a dot clock generator showing an embodiment of the present invention.

FIG. 4 is an operation waveform diagram for explaining the operation of the circuit.

FIG. 5 is a block diagram of a conventional dot clock generator.

FIG. 6 is an operation waveform diagram for explaining the operation of the circuit.

[Explanation of symbols]

 31 capacitor 32a phase difference detection circuit 32b integration circuit 33 buffer 34 PLL circuit 35 counter

Claims (3)

[Claims] 1. A phase of a reference horizontal synchronizing signal in a dot clock generator for generating a dot clock for various video signals when inputting various video signals, converting analog signals into digital signals and processing the signals. And a dot clock is generated for the video signal in a phase that does not sample the change point of the video signal. 2. A capacitor for inputting a horizontal synchronizing signal to remove a DC voltage, a D / A converter for applying a DC voltage to the output signal of the capacitor, and a reference horizontal synchronizing signal for waveform shaping the output signal of the capacitor. A PLL circuit for inputting the reference horizontal synchronizing signal and the comparison horizontal pulse to generate a dot clock, and a counter for operating the dot clock to generate the comparison horizontal pulse. Characteristic dot clock generator. 3. A phase difference detection circuit for inputting a horizontal synchronizing signal and a reference horizontal synchronizing signal instead of the D / A converter and detecting a phase difference between the horizontal synchronizing signal and the reference horizontal synchronizing signal, The dot clock generator according to claim 2, further comprising an integrating circuit that integrates the phase difference to generate a DC voltage.