JPH10254422A - Circuit for restoring analog video signal to digital video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for restoring an analog video signal to a digital video signal capable of A/D converting using a stable clock signal. SOLUTION: A crystal oscillator 5 outputs the clock signal S4 having a frequency of four times of the dot clock of the analog video signal S1, and a clock generation part 6 generates eight clock signals S7 with the same frequency as and a phase different from the dot clock of the analog video signal S1 by shifting at the rise and the fall of the clock signal S4. A phase comparator 7 compares the phase of a horizontal synchronizing signal S3 with the phases of eight clock signals S7 to output these results, and a clock selector 3 outputs the optimum phase clock signals S6, S8. An A/D conversion part 1 restores a stable leveled analog signal S1 to the digital signal S5 by this A/D sampling clock S6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for restoring an analog video signal to a digital video signal, and more particularly to a circuit for restoring an analog signal output from a personal computer, a workstation or the like to a digital signal by an asynchronous clock. The present invention relates to a circuit for restoring an analog video signal to a digital video signal.

[0002]

2. Description of the Related Art Various circuits for restoring an analog video signal to a digital video signal are used in current image processing apparatuses and the like. Conventionally, when an analog video signal is restored to a digital video signal, a clock signal synchronized with the analog video signal is used as a sampling clock signal, and the input analog video signal is restored or converted into a digital video signal (hereinafter simply referred to as A / D). D conversion).

For example, as a sampling clock to be used, a dot clock signal synchronized with an analog video signal is generated from a horizontal synchronizing signal using a PLL oscillator, and this is used as a sampling clock for A / D conversion. FIG. 5 shows an example of a conventional restoration circuit for restoring an external analog video signal to a digital video signal.

The restoration circuit shown in FIG. 5 inputs a horizontal synchronizing signal S3 to a PLL oscillator 19, and the PLL oscillator 19 synchronizes with the horizontal synchronizing signal S3 in an A / D sampling clock (hereinafter, also simply referred to as a clock signal). ) S29
Is generated and output to the A / D converter 1 and the write controller 4. The A / D converter 1 converts the analog video signal S1 into a digital video signal S5 based on the clock signal S29, and outputs the digital video signal S5 to the buffer memory 2. Further, the write control unit 4 includes a horizontal synchronization signal S3 and a vertical synchronization signal S2.
And a video valid period based on the clock signal S29 and outputs a write control signal S10 to the buffer memory 2. The buffer memory 2 controls the writing of the digital video signal S5 based on the write control signal S10.

As a circuit for restoring an analog video signal to a digital video signal, see, for example,
As shown in the "image synthesizing circuit" disclosed in JP-A-213895, a clock signal is output to an external device such as a personal computer, the output analog video signal on the personal computer side is synchronized with an internal clock, and the analog video signal is output. A circuit for restoring a digital video signal has also been proposed.

[0006]

However, since a clock generator such as a PLL oscillator used in a conventional circuit for restoring an analog video signal into a digital video signal controls the oscillation frequency by voltage control, the power supply voltage is low. The frequency of the output clock signal responds very sensitively to a slight change in the ground voltage. Therefore, when a digital circuit is mixed on the same substrate as the PLL oscillator, the clock signal output from the PLL oscillator may be jittered by noise generated from the digital circuit. Therefore, when generating a dot clock signal using a PLL oscillator, it is difficult to design a printed circuit board mixed with other digital circuits, and it is easy to generate a stable clock signal without jitter using a PLL oscillator. However, there is a problem that it is not.

Further, since many personal computers cannot operate in synchronization with an external clock signal, it is difficult to synchronize an output video signal of the personal computer with an internal clock signal. Having.

[0008] The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a circuit for restoring an analog video signal to a digital video signal, which can perform A / D conversion using a stable clock signal without being affected by noise.

[0009]

According to the first aspect of the present invention,
A crystal oscillator that outputs a clock signal having a frequency N times higher than that of the input analog video signal as a first clock signal, and a clock having the same frequency as the analog video signal, shifted at rising and falling edges of the first clock signal And a clock generating means for outputting a clock signal group which is a group of one or more clock signals having different phases, and comparing each clock signal in the clock signal group with the phase of the input horizontal synchronization signal, Phase comparison means for outputting, as a clock selection signal, a signal representing a clock signal having the phase closest to the phase of the horizontal synchronization signal from the clock signals in the clock signal group; Clock selecting means for outputting one clock signal as a second clock signal from As a sampling clock the second clock signal, and having a conversion means for converting an analog video signal the input to the digital video signal.

Therefore, according to the present invention, a group of one or more clock signals having the same frequency and a different phase from the external analog signal is used by using a clock signal N times the external analog signal output from the crystal oscillator. A clock signal group is generated, and a clock signal having the closest phase to the input horizontal synchronizing signal is selected from the clock signal group, and is used as an A / D conversion sampling clock to reduce the influence of noise. A / D conversion can be performed using a stable clock signal which is hard to receive.

According to a second aspect of the present invention, in the first aspect of the present invention, the phase comparing means determines, for each input horizontal synchronizing signal, a clock signal in the clock signal group and an input horizontal synchronizing signal. The phase is compared, and a signal representing a clock signal having the phase closest to the phase of the horizontal synchronization signal from the group of clock signals is output as a clock selection signal.

Therefore, according to the present invention, the operation of the invention described in claim 1 can be obtained, and the phase of the clock signal in the clock signal group and the phase of the input horizontal synchronization signal can be determined for each input horizontal synchronization signal. The optimum clock signal is selected by comparing the phase of the external clock signal and the phase of the clock signal output from the clock generation means even if the phase of the clock signal is shifted. The phase shift can be corrected.

According to a third aspect of the present invention, in the first or second aspect, the circuit for restoring the analog video signal to a digital video signal includes a radar interface for receiving a signal from a radar device, and the radar. Coordinate conversion means for performing coordinate conversion so that the signal received by the interface is adapted to the scanning method of the display device.

Therefore, according to the present invention, the operation of the invention described in claim 1 or 2 can be obtained, and an image represented by a graphic video signal processed by an external device and a signal received from a radar device is used. Image processing.

According to a fourth aspect of the present invention, in the first aspect, the circuit for restoring the analog video signal to a digital video signal converts the input composite video signal into an analog video signal, Separating means for separating and outputting a horizontal synchronization signal and a vertical synchronization signal, respectively.

Therefore, according to the present invention, the effect of the invention described in any one of the first to third aspects is obtained, and image processing is performed on an image represented by a composite video signal output from an external device. It can be carried out.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention.

A circuit for restoring the analog video signal to a digital video signal (hereinafter, also simply referred to as a restoration circuit).
First, the crystal oscillator 5 outputs a clock signal S4 having a frequency n times the dot clock of the analog video signal S1 input from the outside to the restoration circuit to the clock generator 6. Here, in the present embodiment, it is assumed that n = 4, but the present invention is not limited to n = 4.

A clock generator 6 generates one or more clock signals having the same frequency as the input analog video signal S1 and different phases based on the clock signal S4 output from the crystal oscillator 5. Group S7
To the clock selector 3 and the phase comparator 7. In the present embodiment, eight clock signals are generated and output as a clock signal group S7.

The phase comparator 7 compares the phases of the horizontal synchronizing signal S3 and the eight clock signals in the clock signal group S7, and selects a clock signal having an optimum phase from the eight clock signals. Is generated as a clock selection signal S9 and output to the clock selector 3. Here, the phase closest to the phase of the horizontal synchronization signal may be selected as the optimum phase.

The clock selector 3 switches the clock signal to be output in accordance with the input clock selection signal S9, and outputs the clock signal S6 having the optimum phase from the eight clock signals to the A / D converter 1, A /
It outputs to the write control unit 4 as a D sampling clock S8.

The A / D converter 1 converts the input analog video signal S1 into a clock signal S having the above-described optimum phase.
6 is used as an A / D sampling clock, converted into a digital video signal S5, and output to the buffer memory 2.

The write control unit 4 includes a horizontal synchronizing signal S3,
Vertical synchronization signal S2 and A / D sampling clock S8
, A write control signal S10 for the buffer memory 2 is generated.

The buffer memory 2 stores a write control signal S
According to 10, the digital video signal S5 is temporarily stored.
The stored data is read out in accordance with the display timing by the buffer memory read signal S11 from the display timing generator 13.

The CPU 8 outputs a drawing command S14 to the graphic controller 9. The graphic control unit 9
The drawing data S15 is written into the frame memory 10. The display timing generator 13 includes a frame memory read signal S13, a buffer memory read signal S11 and a D /
An A-converted clock signal S12 is output. The data stored in the frame memory 10 is read at the display timing based on the frame memory read signal S13. The color pallet RAM 11 colors the data S16 read from the frame memory 10 and outputs the colored data S17 to the video synthesizing unit 12.

The video synthesizing unit 12 performs image processing such as synthesizing based on the data S20 stored in the buffer memory 2 and the colored data S17 output from the color pallet 11, and outputs digital data S18.
The D / A converter 14 converts the digital data S18 into an analog signal S19 based on the D / A conversion clock signal S12 output from the display timing generator 13, and outputs the analog signal S19 to the display device 15. The display device 15 performs display based on the input analog signal S19.

Next, the operation of the circuit for restoring an analog video signal into a digital video signal according to the first embodiment will be described in more detail with reference to FIGS.

Normally, an analog video signal output from a personal computer, a work station or the like is subjected to D / A conversion (digital / analog conversion) of digital video data based on a dot clock immediately before being output, and is output as an analog video signal. . Therefore, this analog video signal has a staircase waveform with the dot clock frequency as the minimum unit.

Therefore, when restoring the analog video signal having the staircase waveform to the digital video signal again, it is sufficient to sample the stable level of the staircase waveform with a clock having the same frequency as the dot clock and perform A / D conversion. It is not necessary that the analog video signal and the sampling clock for A / D conversion are synchronized.

Here, the crystal oscillator 5 outputs a clock signal S4 having a frequency four times the dot clock of the input analog video signal S1 (FIG. 2 (a)), and outputs this to the clock generator 6. . The clock generator 6 generates a clock signal having the same frequency as the dot clock of the external analog video signal S1 by dividing the frequency.
Further, this signal is applied to the clock signal S4 from the crystal oscillator 5.
The clock signal group S7, which is a group of eight clock signals having the same frequency and different phases as the dot clock of the analog video signal S1 output from the outside, is generated by shifting the clock signal at the rising and falling edges of the clock signal (FIG. 2). (B)). This clock generator 6 is preferably realized by a combination of a flip-flop, a shift register and the like.

The clock selector 3 receives a clock signal group S7, which is a group of eight clock signals having different phases from the horizontal synchronizing signal. Each time the horizontal synchronizing signal rises, the clock signal of the optimum phase is selected from the eight clock signals. And outputs it to the A / D converter 1 and the write controller 4. This can be realized by a combination of flip-flops, selectors, and the like. This input analog video signal S1 is
This is equivalent to selecting a clock signal having an optimal phase with respect to the input analog video signal S1 because the clock signal is always synchronized with the horizontal synchronization signal ((c) in FIG. 2).
(D)).

A crystal oscillator for outputting a dot clock incorporated in an external personal computer or the like, and a dot clock frequency of an external analog video signal and a clock generation unit based on the error accuracy of the crystal oscillator 5 provided in the present embodiment. 6 are not completely the same, and the phases of the two clocks may shift slightly over time. However, the horizontal synchronization signal S3
Since the clock signal having the optimum phase is selected for the input analog video signal S1 every time the rising edge of the clock signal rises, this error is corrected and does not cause a problem.

The A / D converter 1 samples the input analog video signal S1 with an A / D sampling clock S6, converts it into a digital video signal S5, and outputs this to the buffer memory 2. The write controller 4 controls the writing of video data in the effective range period based on the A / D sampling clock S8 from the clock selector 3 and the horizontal synchronizing signal S3 and the vertical synchronizing signal S2 from an external device such as a personal computer. Control signal S10
Is output to the buffer memory 2. The buffer memory 2 stores digital video data S5 based on a write control signal S10 from the write control unit 4. The buffer memory 2 is for reading data in accordance with the display timing of the display device 15, and a VRAM, a FIFO memory, or the like can be used. The video data S20 stored in the buffer memory 2 is output to the video synthesizing unit 12 in accordance with the read control timing S11 specified by the display timing generating unit 13.

In this manner, an analog video signal from a personal computer or the like can be converted into digital video by a clock signal generated from an asynchronous crystal oscillator and stored in a buffer memory.

Thereafter, the CPU 8 executes the drawing command S14
Is output to the graphic control unit 9. The graphic control unit 9 analyzes the drawing command S14 and generates drawing data S15.
Is written to the frame memory 10. Frame memory 10
Are read out in accordance with the display timing S13 from the display timing generator 13 and output to the color pallet RAM 11. Color palette RAM1
In step 1, the video data is colored, and the colored video data S17 is output to the video synthesizing unit 12.

The video synthesizing section 12 reads out the external video signal S from the personal computer or the like based on the read signal S11 output from the display timing control section 13.
20 is combined with the colored video data S17 output from the color palette RAM 11 and
Output to the A conversion unit 14. The D / A converter 14 converts the colored digital video data S17 into an analog video signal S19 suitable for the input interface of the display device 15 and executes display on the display device 15.

Therefore, according to the first embodiment, P
The clock signal S generated from the crystal oscillator 5 that is asynchronous with the analog video signal S1 without using the LL oscillator.
4 to a digital video based on the buffer memory 2
, The operation can be stabilized, and separately processed images can be combined and displayed on one display device 15.

Next, a second embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention. In this figure, FIG.
1 is that a radar interface 16 and a coordinate conversion unit 17 are provided instead of the CPU 8 and the graphic control unit 9 shown in FIG.
Other configurations are the same.

Therefore, the radar interface 16
The operation of the coordinate conversion unit 17 will be described. The radar interface 16 receives a radar video signal S23 output from an external radar device. The coordinate conversion unit 17 performs coordinate conversion on the radar video signal S23 received by the radar interface 16 so as to match the scanning method of the display device 15, and outputs the converted signal to the frame memory 10 as a conversion signal S22. For example, when the radar video signal S23 from an external radar device is polar coordinates represented by r and θ, and the display device 15 is a raster scan display, this is converted into rectangular coordinates represented by X and Y, Write to the frame memory 10. Subsequent operations are the same as those of the circuit for restoring an analog video signal into a digital video signal according to the first embodiment, and a description thereof will be omitted.

Therefore, according to the second embodiment, the same effects as those of the first embodiment can be obtained, and the radar video output from the radar device is combined with the graphic video processed by the personal computer or the like. Can be displayed.

Next, a third embodiment of the circuit for restoring an analog video signal to a digital video signal according to the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing a configuration of a third embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention. In this figure, FIG.
1 is that the signal S1 output from the external personal computer or the like shown in FIG. 1 is a composite video signal S25, and the composite video signal Synchronization separation unit 18 for processing S25
Is provided. Other configurations are the same.

Accordingly, the operation of the synchronization separating section 18 will be described. The input composite video signal S25 is separated into an analog video signal S1, a horizontal synchronization signal S3, and a vertical synchronization signal S2 in the synchronization separation section 18, and each is output. The analog video signal S1 is supplied to the A / D converter 1
The horizontal synchronization signal S3 is output to the write control unit 4 and the phase comparison unit 7, and the vertical synchronization signal S2 is output to the write control unit 4. Subsequent operations are the same as those of the circuit for restoring an analog video signal into a digital video signal according to the first embodiment, and a description thereof will be omitted.

Therefore, according to the third embodiment, the first
The same effect as the operation of the first embodiment can be obtained, and a personal computer or a workstation that outputs a composite video signal can also combine images processed separately as in the first embodiment and display one image. It can be displayed on the device 15.

In the above description, the first embodiment,
Although the second embodiment and the third embodiment have been described separately, it is clear that the present invention may appropriately combine the functions provided in the respective embodiments.

[0047]

As is apparent from the above description, according to the present invention, a crystal oscillator having a high operation stability is used as a clock signal output device without using a PLL oscillator, so that a clock signal having no jitter is used. It is possible to provide a circuit capable of performing / D conversion and restoring an analog video signal to a digital video signal with little deterioration in image quality when the analog video signal is restored to a digital video signal.

Further, since a crystal oscillator which is resistant to noise generated from a digital circuit is used, a circuit for restoring an analog video signal into a digital video signal, which makes it easy to design a printed circuit board even when mixed with a digital circuit, is provided. be able to.

Further, since the phase of the clock signal in the clock signal group is compared with the phase of the input horizontal synchronization signal for each input horizontal synchronization signal, the phase of the external clock signal and the output from the clock generation means are compared. Even if the phase of the clock signal is deviated, a circuit that can correct the deviation at each comparison and restore the analog video signal that can supply a stable clock signal to a digital video signal Can be provided.

Further, since it has a radar interface for receiving a signal from the radar device and coordinate conversion means for performing a coordinate conversion on the signal received by the radar interface so as to be adapted to a scanning method of the display device, an external device is provided. It is possible to provide a circuit for restoring an analog video signal, which can be subjected to image processing using a video represented by a signal received from a radar device to a graphic video signal processed by the device, to a digital video signal.

Further, since there is provided a separating means for separating the input composite video signal into an analog video signal, a horizontal synchronizing signal and a vertical synchronizing signal and outputting each of them, it can be represented by a composite video signal output from an external device. It is possible to provide a circuit for restoring an analog video signal, which can perform image processing on an image to be reproduced, into a digital video signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention.

FIG. 2 is a timing chart showing the operation of the circuit for restoring the analog video signal shown in FIG. 1 into a digital video signal.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention.

FIG. 4 is a block diagram showing a configuration of a third embodiment of a circuit for restoring an analog video signal to a digital video signal according to the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional circuit for restoring an analog video signal to a digital video signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 Buffer memory 3 Clock selector 4 Write control part 5 Crystal oscillator 6 Clock generation part 7 Phase comparator 8 CPU 9 Graphic control part 10 Frame memory 11 Color palette RAM 12 Video synthesis part 13 Display timing generation part 14 D / A conversion unit 15 display device 16 radar interface 17 coordinate conversion unit 18 synchronization separation unit

Claims (4)

[Claims] 1. A crystal oscillator for outputting a clock signal having a frequency N times higher than that of an input analog video signal as a first clock signal, and a clock signal shifted by rising and falling edges of the first clock signal. Clock generating means for outputting a clock signal group which is a group of one or more clock signals having the same frequency as the signals and having different phases; each clock signal in the clock signal group;
Phase comparison means for comparing the phase with the input horizontal synchronization signal and outputting a signal representing a clock signal having the phase closest to the phase of the horizontal synchronization signal from the clock signals in the clock signal group as a clock selection signal; Clock selecting means for outputting one clock signal from the group of clock signals as a second clock signal based on a clock selection signal; and digitally converting the input analog video signal using the second clock signal as a sampling clock. A circuit for converting an analog video signal into a digital video signal, the conversion circuit comprising: 2. The phase comparison means compares the phase of a clock signal in the clock signal group with the phase of the input horizontal synchronization signal for each input horizontal synchronization signal, and outputs a horizontal signal from the clock signal group. 2. The circuit for restoring an analog video signal to a digital video signal according to claim 1, wherein a signal representing a clock signal having a phase closest to the phase of the synchronization signal is output as a clock selection signal. 3. A circuit for restoring the analog video signal to a digital video signal, comprising: a radar interface for receiving a signal from a radar device; and a coordinate for adapting the signal received by the radar interface to a scanning method of a display device. The circuit for restoring an analog video signal to a digital video signal according to claim 1 or 2, further comprising a coordinate conversion means for performing conversion. 4. A circuit for restoring an analog video signal into a digital video signal, comprising: separating means for separating an input composite video signal into an analog video signal, a horizontal synchronizing signal, and a vertical synchronizing signal, respectively, and outputting the separated video signal. Claim 1 characterized by the following:
4. A circuit for restoring an analog video signal according to any one of items 1 to 3 into a digital video signal.