JP2606094B2 - Image sampling circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanner for reading image data, and more particularly to an image sampling circuit in the scanner.

[0002]

2. Description of the Related Art In recent years, various types of image processing for improving image quality have been used in scanner apparatuses using digital processing technology. In this case, when digitally processing the image data, it is necessary to perform sampling to obtain data in pixel units. Sampling is supplied from a clock generation source synchronized with one line, and is realized by latching image data using a flip-flop. On this occasion,
When the change point of the image data is located in the first half of one cycle of the sampling clock and in the latter half, a sampling position error close to a maximum of one pixel occurs, and so-called sampling jitter occurs in a line drawing image or the like. In particular, unevenness is conspicuous particularly on a line orthogonal to the scanning line.

Conventionally, as a method of reducing the sampling jitter, a plurality of timings of a sampling clock phase are prepared using a delay line or the like, a clock having the closest phase in one cycle is determined, and image data is output. There is a way. In the case of this method, since the sampling clock is used as it is for the pixel clock used after the sampling clock circuit, the phase of the clock changes depending on the image data, so that it is difficult to configure the image processing circuit at the subsequent stage.

[0004]

In this conventional sampling circuit, the circuit configuration is complicated and the pixel clock used after the sampling circuit uses the sampling clock as it is. Therefore, there is a problem that the configuration of the subsequent image processing circuit becomes complicated. The present invention has been made to solve such a problem, and an object of the present invention is to provide an image sampling circuit that reduces sampling jitter for one cycle of a sampling clock when sampling image data.

[0005]

An image sampling circuit according to the present invention comprises: a first flip-flop for latching image data at a rising phase of a sampling clock; and data from the first flip-flop for rising a sampling clock. A second flip-flop that latches at a downstream phase, a first exclusive-OR circuit that obtains an exclusive OR of outputs of the first and second flip-flops, and an operation at a rising phase of the sampling clock A third flip-flop that shifts the output of the flip-flop to be shifted by one pixel at the rising edge of the sampling clock, and takes the output of the third flip-flop shifted by one pixel as one input, and outputs the falling edge of the sampling clock. The exclusive OR of the output of the second flip-flop operating on A second exclusive OR circuit for calculating,
A selection logic generation circuit for generating a selection signal for determining whether the change point of the image data is the first half or the second half of one cycle of the sampling clock from the outputs of the first and second exclusive OR circuits, and the first flip-flop And a selection circuit for selecting one of the output of the third flip-flop and the output of the third flip-flop. Further, the selection circuit includes a first circuit.
Output of flip-flop and output of second flip-flop
And the output of the second flip-flop and the third
When the outputs of the flip-flops match, the first flip
The output of the flip-flop and the output of the second flip-flop
The output of the second flip-flop and the third flip-flop.
When the flip-flop outputs do not match and when the first
The output of the flip-flop and the output of the second flip-flop are
Mismatch and the output of the second flip-flop is
When the outputs of the flip-flops 3 do not match,
Select the output of the third flip-flop, and
The output of the flip-flop and the output of the second flip-flop are
Mismatch and the output of the second flip-flop is
When the outputs of the third flip-flops match,
This selects the output of one flip-flop.

[0006]

According to the present invention, the sampling timing is selected with reference to the image data before 1/2 pixel.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a flip-flop for latching image data at the rising phase of a sampling clock;
Is an flip-flop that latches the data from the flip-flop 1 at the falling phase of the sampling clock, 3 is an exclusive-OR circuit for obtaining the exclusive-OR of the output of the flip-flop 1 and the output of the flip-flop 2,
Is a flip-flop that shifts the output of the flip-flop 1 operating at the rising phase of the sampling clock by one pixel at the rising of the sampling clock, and 5 is 1
An exclusive-OR circuit for obtaining an exclusive-OR by using the output of the flip-flop 4 shifted by the pixel as one input and the output of the flip-flop 2 operating at the falling edge of the sampling clock as the other input, and 6 is an exclusive OR circuit A selection logic generation circuit that generates a selection signal for determining whether the change point of the image data is the first half or the second half of one cycle of the sampling clock based on the output of the OR circuit 3 and the output of the exclusive OR circuit 5; A selection circuit for selecting one of the output of the flip-flop 1 operating at the rising phase and the output of the flip-flop 4 shifting the output of the flip-flop 1 operating at the rising phase of the sampling clock by one pixel, and 8 is the sampling clock This is an inversion circuit that inverts SCK.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.
This will be described with reference to FIG. FIG. 2 is an explanatory diagram for explaining the operation of FIG. 1. In FIG. 2, SCK indicates a sampling clock, and iD indicates input image data. First, the input image data iD input from the terminal T ₁ is latched in the flip-flop 1 at the rising phase of the sampling clock SCK input from the terminal T ₂ . This is signal A. This signal A is further latched by the flip-flop 4 at the rising phase of the sampling clock SCK to become a signal C,
It is input to the exclusive OR circuit 5 and the selection circuit 7. Also,
The signal A is input to the flip-flop 2, which operates at the falling edge of the sampling clock SCK, the exclusive OR circuit 3, and the selection circuit 7.

Next, the exclusive OR circuit 3 determines whether or not the signal A and the signal B are coincident with each other.
Determines whether signal B and signal C match. Each output of the exclusive OR circuits 3 and 5 is input to the selection logic generating circuit 6. Then, the selection logic generation circuit 6 generates the selection signal SEL under the following conditions.

In case 1, if signal A = signal B and signal B = signal C, a signal for selecting signal C is input to selection circuit 7. In case 2, if signal A = signal B and signal B ≠ signal C, a signal for selecting signal C is input to selection circuit 7. In case 3, if signal A ≠ signal B and signal B = signal C, a signal for selecting signal A is input to selection circuit 7. In case 4, if signal A ≠ signal B and signal B ≠ signal C, a signal for selecting signal C is input to selection circuit 7.

FIG. 2 shows the case of Case 3, in which the change point of the input image data iD is in the first half of one cycle of the sampling clock SCK. In this case, by selecting the signal A without using the signal C as the output of the sampling circuit, the sampling jitter is reduced. The selection output from the selection circuit 7 is sent to the terminal T ₃ as the output image data oD.

[0012]

As described above, according to the present invention, the sampling timing is selected by referring to the pixel data before 1/2 pixel, so that the "jittering" so-called sampling jitter in the line drawing image or the like can be simplified. There is an effect that can be reduced by the configuration. Further, since the phase of the sampling clock is not changed, there is an effect that the configuration of the subsequent image processing circuit is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of FIG. 1;

[Explanation of symbols]

 1, 2 flip-flop 3 exclusive OR circuit 4 flip-flop 5 exclusive OR circuit 6 selection logic generation circuit 7 selection circuit

Claims (2)

(57) [Claims] 1. A first flip-flop for latching image data at a rising phase of a sampling clock, and a second flip-flop for latching data from the first flip-flop at a falling phase of the sampling clock. A first exclusive-OR circuit for obtaining an exclusive-OR of outputs of the first and second flip-flops;
A third flip-flop that shifts the output of the flip-flop operating at the rising phase of the sampling clock by one pixel at the rising edge of the sampling clock, and outputs the output of the third flip-flop shifted by one pixel to one A second exclusive OR circuit which takes an output of a second flip-flop operating at the falling edge of the sampling clock as the other input and obtains an exclusive OR, and the first and second exclusive logics A selection logic generation circuit for generating a selection signal for determining whether the change point of the image data is the first half or the second half of one cycle of the sampling clock from the output of the sum circuit, the output of the first flip-flop and the third flip-flop And a selection circuit for selecting any one of the above-mentioned outputs. 2. The circuit according to claim 1, wherein said selection circuit comprises an output of a first flip-flop and a second flip-flop.
The outputs of the flip-flops match and the output of the second flip-flop
When the output of the third flip-flop matches the output of the third flip-flop,
Output of the second flip-flop and the output of the second flip-flop
The outputs match, and the output of the second flip-flop and the
When the outputs of the third flip-flops do not match, and
Output of one flip-flop and second flip-flop
Are inconsistent, and the output of the second flip-flop is
When the output does not match the output of the third flip-flop
Selects the output of the third flip-flop respectively
And, the output of the first flip-flop and the second flip
The outputs of the flip-flops do not match and the second flip-flop
And the output of the third flip-flop match.
An image sampling circuit for selecting an output of the first flip-flop .