JP2642100B2 - Synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit for synchronizing a video signal and a sampling clock, and more particularly to a synchronization circuit suitable for quantizing a high-speed video signal.

[Prior art] The conventional method is described in Japanese Patent Application Laid-Open No. 58-16288.
A video signal and a sampling pulse signal are detected by detecting a synchronization signal between the supplied video signal, that is, a phase error between the horizontal synchronization signal and the supplied sampling pulse signal, and shifting the phase of the video signal according to the phase error. Had to be synchronized.

[Problems to be Solved by the Invention] In the above-mentioned conventional method, an error between a synchronization signal of a supplied video signal, that is, a horizontal synchronization signal, and a supplied sampling pulse signal phase is detected, and a video signal is detected in accordance with the phase error. Since the sampling pulse signal and the video signal are synchronized by shifting the phase of the signal, the phase error between the horizontal synchronization signal and the video signal needs to be constant.

Therefore, when implementing in a device in which the phase relationship between the horizontal synchronization signal and the video signal is different, it is necessary to set the delay amount of the video signal in each device in consideration of the phase error between the horizontal synchronization signal and the video signal. Was.

As described above, an object of the present invention is to synchronize a video signal with a sampling pulse signal, that is, a sampling clock, regardless of a phase error between the horizontal synchronization signal and the video signal.

[Means for Solving the Problems] To achieve the above object, the present invention provides a synchronization circuit for synchronizing an input video signal and a sampling clock, comprising: Delay means for outputting a signal; phase detection means for detecting a phase relationship between the plurality of video signals having different delay amounts and the sampling clock; outputting a predetermined determination result according to a detection result of the detection means Phase determination means, sampling clock supply means for generating two sampling clocks having different phases, and sampling clock selection means for selecting and outputting one of the two sampling clocks as the sampling clock according to the determination result. It is characterized by being provided.

In one embodiment of the present invention, the delay means has two delay circuits connected in series, and outputs both delayed video signals of the two delay circuits together with the non-delayed video signal.

As another embodiment of the present invention, the phase detecting means includes:
It has a plurality of flip-flops each of which latches the plurality of video signals in accordance with the sampling clock.

As still another embodiment of the present invention, the phase difference between the two sampling clocks having different phases is 180 °.

[Operation] The phase shift between the sampling clock and the video signal is determined by detecting the phase shift between the sampling clock and the horizontal synchronization signal in the above-described conventional technique. Since a plurality of different video signals are created and directly obtained based on the phase relationship between these signals and two sampling clocks having different phases, regardless of the phase error between the horizontal synchronization signal and the video signal in each device, Therefore, the phase of the video signal and the phase of the sampling clock can be surely matched.

That is, in the present invention, the delay circuit delays the video signal, generates a signal equivalent to three types of video signals having different delay amounts, and outputs the signal to the phase detection unit.

The phase detector detects a phase state of the three types of equivalent signals output from the delay circuit with a sampling clock,
The detection result is output to the phase determination unit.

The phase determination unit makes a determination to determine the phase of the next sampling clock based on the detection result input from the phase detection unit, and outputs the determination result to the sampling clock selection unit.

The sampling clock supply unit supplies a sampling clock having a frequency shifted by a half cycle and equal to the pixel clock of the video signal to the sampling clock selection unit.

The sampling clock selection unit switches between the two samplings supplied from the sampling clock supply unit according to the determination result input from the phase determination unit.

As described above, from these operations, the phase error between the video signal and the sampling clock is detected at each rising edge of the sampling clock, and when the phase error exceeds a certain amount,
By changing the timing at which the output sampling clock is switched, the phase error between the video signal and the sampling clock is corrected and synchronization is achieved.

Although the detection timing is limited to every rising here for convenience of explanation, it may be at the falling time or both.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of a synchronization circuit according to the present invention.

1 includes an oscillator 1, a sampling clock generation circuit 2, delay circuits 3 and 4, flip-flops (hereinafter abbreviated as FFs) 5 to 7, a phase determination circuit 8, and a sampling clock selection circuit 9. . In this embodiment, the video signal 20 has a dot frequency of 52.914 MHz.
, And a monochrome black-and-white monochrome image is represented by high-level and low-level signal values. The dot cycle of the video signal is 18.90 ns at 1 / 52.914 MHz, and 16.60 ns in each cycle.
It is assumed that the video signal effectively represents the dot color (white or black) for a period of 68 ns.

The delay circuits 3 and 4 constitute delay means 60, and FF5 to FF7
Constitutes the phase detecting means 80. The oscillator 1 and the sampling clock generation circuit 2 constitute a sampling clock supply unit 70. Further, the phase judgment circuit 8 constitutes a phase judgment means, and the sampling clock selection circuit 9 constitutes a sampling clock selection means.

The oscillator 1 oscillates a basic clock having a frequency of 105.828 MHz. The sampling clock generation circuit 2 generates a sampling clock CK1 and a sampling clock CK2 from the basic clock of the oscillator 1. The sampling clock CK1 and the sampling clock CK2 have a frequency of 52.91, respectively.
It is a clock signal with a duty ratio of 1: 3 at 4 MHz, and both are 180 degrees apart from each other. However, setting the duty ratio to 1: 3 is an example.
It may be 1: 1.

The delay circuit 3 outputs a signal LVIDEO obtained by delaying the video signal input from the input terminal 20 by 4.17 ns. The delay circuit 4 receives the LVIDEO output from the delay circuit 3 and outputs a signal BVIDEO obtained by delaying this signal by 4.17 ns.
That is, the delay circuit 3 and the delay circuit 4 give the video signal a delay corresponding to 1/4 of the 16.68 ns period in which the value of the video signal 20 effectively represents the color of the dot in each dot cycle.

FF5 latches BVIDEO which is the output of the delay circuit 4, and
F6 latches LVIDEO, which is the output of the delay circuit 3, and FF7 latches FVIDEO that has not performed any processing on the video signal. FF5, FF6, and FF7 receive the sampling clock, respectively, and receive FVIDEO, LVIDEO, BVID
EO phase is detected and the detection result is BDATA, LDATA, FDAT
A is output to the phase determination circuit 8 as A.

The output terminal 21 outputs a signal LDATA equivalent to the input video signal and synchronized with the sampling clock.

The three signals BDATA, LDATA, and FDATA take only six patterns as shown in FIG.

The phase determination circuit 8 outputs B from the FF5, FF6, and FF7.
In response to DATA, LDATA, and FDATA, one of the B, F, and N determinations is made in accordance with the six patterns and determination results shown in FIG. 3, and when the B determination is made, a B signal is output, and the F determination is made. At the time of F, the F signal is output.

The sampling clock selection circuit 9 switches between the sampling clock CK1 and the sampling clock CK2 when the B signal or the F signal is output from the phase determination circuit 8. For example, when the B signal is output, the sampling clock CK1 or CK2 selected by the sampling clock selection circuit 9 is not selected at the falling edge of the unselected sampling clock CK1 or CK2. The sampling clock is switched to the sampling clock, which is output to the output terminal 22 and input to FF5, FF6 and FF7. When the F signal is input, the sampling clock CK1 or the sampling clock CK2 selected by the sampling clock selection circuit 9 is switched to an unselected sampling clock at the falling edge of the signal, and is output to the output terminal 22. Output and FF5, F
Input to F6 and FF7.

The operation of this embodiment will be described with reference to FIGS.

FIG. 2 is a timing chart of a synchronization circuit showing a time relationship between a video signal and a sampling clock;
FIG. 3 is an explanatory diagram showing determination conditions and results of the phase determination circuit.

First, the supplied video signal is given a 4.17 ns delay by the delay circuit 3 with the FVIDEO input to the FF7 as it is.
BVIDEO input to FF6 and BVIDEO input to FF5 after a total delay of 8.34 ns given by delay circuit 3 and delay circuit 4
And the phase relationship is as shown in FIG.

Next, BVIDEO and LVIDE latched by FF5, FF6, FF7
O and FVIDEO are sampling clocks previously output from the sampling clock selection circuit 9 at the time T1 shown in FIG.
Is selected), the phase state is detected at the rising edge 30.

That is, the phase state of the sampling clock
Since this is the same as the case of the arrow 42 in the figure and corresponds to the case of the arrow 43, the BDATA is “0”, the LDATA is “0”, and the FDATA is “1”, which are input to the phase determination circuit 8.

Next, in the phase determination circuit 8, the input BDATA, FDAT
F determination is made from A and LDATA according to the determination relationship shown in FIG. 3, and an F signal is output to the sampling clock selection circuit 9.

In the sampling clock selection circuit 9, the input F
The signal causes the sampling clock to change from the sampling clock CK1 to the sampling clock CK2 at the falling edge 31 at the time T1 of the sampling clock CK1 shown in FIG.
Switch to 32 and set sampling clock CK2 to output terminal 22
(Fig. 1) and input to FF5, FF6 and FF7.

Similarly, as shown in FIG. 2, at the rising edge 33 of the sampling clock T2 switched to the sampling clock CK2, the BVIDEO latched at FF5, FF6 and FF7.
Detects the phase status of O, LVIDEO, and FVIDEO. That is,
The sampling clock and the phase state of BVIDEO, LVIDEO, and FVIDEO are the same as the case of arrow 46 in FIG. 3 and correspond to arrow 47, so that BDATA is “1”, LDATA is “1”,
A becomes “1”.

Therefore, in the next phase determination circuit 8, the input BDAT
According to the determination relationship shown in FIG. 3 based on A, LDATA, and FDATA, N determination is made and nothing is output, so the next stage sampling clock selection circuit 9 does not perform the switching operation.

At time T10 in FIG. 2, BVIDEO, LVIDEO, and FVIDEO latched at FF5, FF6, and FF7 are the rising edge of the sampling clock (here, sampling clock CK2) output from the sampling clock selection circuit 9.
At 4, a phase condition is detected. That is, since the phase state of the sampling clock is the same as that of the arrow 44 in FIG. 3 and corresponds to the arrow 45, BDATA is “0” and L
DATA is “1”, FDATA is “1”, and input to the phase determination circuit 8.

Next, in the phase determination circuit 8, the input BDATA, LDA
Based on TA and FDATA, B determination is made according to the determination relationship shown in FIG. 3, and a B signal is output to the sampling clock selection circuit 9.

Therefore, the sampling clock selection circuit 9 sets the sampling clock to the sampling clock at the falling edge 35 at the time T11 of the unselected sampling clock CK1 shown in FIG. Switching to CK1, the sampling clock CK1 is output to the output terminal 22 in FIG. 1, and is input to FF5, FF6, and FF7.

As described above, all of the above operations are performed even if the sampling clocks CK1 and CK2 are exchanged, and are repeated every time the sampling clock rises.

As described above, according to the present embodiment, it is possible to synchronize a video signal having an extremely high frequency with a sampling clock substantially equal to the frequency regardless of the phase error between the horizontal synchronization signal and the video signal.

According to the circuit for synchronizing a video signal with a sampling clock according to the present invention, the video signal and the sampling clock can be synchronized without considering the phase error between the horizontal synchronization signal and the video signal. Therefore, even in a device in which the phase error between the horizontal synchronization signal and the sampling clock is different, there is an effect that there is no need to change the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of each signal on the block diagram of the present invention, and FIG.
The figure is an explanatory diagram for explaining the phase relationship between BVIDEO, LVIDEO, FVIDEO and the sampling clock. 1 ... oscillator, 2 ... sampling clock generation circuit,
3,4 delay circuit, 5,6,7 FF, 8 phase determination circuit
9: sampling clock selection circuit, 20: input terminal, 21: output terminal, 22: output terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Okazawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Yoshihiro Yokoyama 292 Yoshida-cho, Totsuka-ku, Yokohama Stock (72) Inventor Kensuke Oyu 292 Yoshida-cho, Totsuka-ku, Yokohama-shi In-house Microelectronics Device Development Laboratory, Hitachi, Ltd. (56) References JP-A-58-16288 (JP, A) JP-A-54-38718 (JP, A)

Claims (3)

(57) [Claims] 1. A synchronizing circuit for synchronizing a sampling clock with a video signal sampled by the sampling clock, a clock supply means for generating two clocks having different phases, and one of the two clocks being sampled by the sampling circuit Sampling clock selecting means for selecting and outputting as a clock; delay means for delaying an input video signal by different delay amounts and outputting a plurality of video signals having different delay amounts; latching the plurality of video signals in accordance with the sampling clock, respectively A value set in advance as a combination of a plurality of flip-flops and a value of a video signal latched by each flip-flop is obtained when the phase of the sampling clock is ahead of the phase of the video signal to be sampled. Pair of In this case, it is determined that the phase of the sampling clock is ahead of the phase of the video signal to be sampled, and the combination of the values of the video signals latched by the flip-flops indicates that the phase of the sampling clock is If the combination of values set in advance as a combination of values obtained when the phase is delayed from the phase of the sampled video signal, the phase of the sampling clock is delayed from the phase of the sampled video signal. Determining means for determining, wherein the sampling clock selecting means, when it is determined that the phase of the sampling clock is ahead of the phase of the video signal to be sampled, switching of a clock selectively output as the sampling clock After the clock switch, The phase of the sampling clock is delayed with respect to the phase of the sampling clock before the clock switching, and when it is determined that the phase of the sampling clock is behind the predetermined phase, A switching circuit for switching a clock to be selectively output, at a timing such that the phase of the sampling clock advances after the clock switching with respect to the phase of the sampling clock before the clock switching. 2. The delay means according to claim 1, wherein said delay means has two delay circuits connected in series, and outputs both delayed video signals of said two delay circuits together with said non-delayed video signal. Synchronization circuit. 3. The synchronization circuit according to claim 1, wherein the phase difference between the two sampling clocks having different phases is 180 °.