JP2932409B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for a video signal such as a computer.

[0002]

2. Description of the Related Art In recent years, digital signal processing technology has been remarkably developed, and attention has been paid to A / D conversion for converting an analog signal to a digital signal and D / A conversion for converting a digital signal to an analog signal. Generally, the AC signal is A
When performing the / D conversion, it is important how the frequency component of the input signal can be transmitted correctly, and the basic Nyquist sampling theorem indicates that sampling must be performed at twice or more the maximum frequency to be handled. . On the other hand, in order to A / D convert video signals from personal computers, workstations, and graphics stations as accurately as possible,
It is optimal to sample with the dot clock itself that constitutes the screen. Hereinafter, a conventional A / D converter for a video signal such as a computer will be described with reference to the drawings. FIG. 6 shows a schematic configuration example. In FIG. 6, 81 is a video signal, 82 is a horizontal synchronization signal, 83 is a digital signal, 84 is a dot clock signal,
Reference numeral 85 denotes an A / D converter, 86 denotes a phase-locked loop (hereinafter referred to as PLL) unit, 87 denotes a variable delay, 88 denotes a delay amount control unit, and 89 denotes manual adjustment. FIG. 7 shows the timing. In FIG. 7, reference numeral 91 denotes a video signal, 92 denotes a sampling clock signal, 93 denotes the width of one dot on a screen, 94 denotes sampling timing, and 95 denotes a sampling period (T). A video signal from a computer or the like contains a frequency component higher than the dot clock frequency constituting the screen, and it is desirable to use the dot clock signal as a sampling clock signal for A / D conversion. However, in many cases, actual computer equipment does not output the dot clock signal to the outside. In this case, the output horizontal synchronization signal 82 is multiplied by the PLL unit 86 as shown in FIG. Then, the dot clock signal 84 is reproduced. The video signal 81 is converted into a digital signal 83 by the A / D converter 85 by using the signal as a sampling clock signal. In this way, when performing A / D conversion with the dot clock signal itself of the video signal or the reproduced clock signal of the same frequency, it is necessary to consider the sampling clock signal and the phase of the video signal. is there. Even if this phase is for the same standard video signal of the same model computer,
Subtle deviations due to individual variations, etc., and if the deviation exceeds the allowable range, noise will occur in the subsequent processing system, and if it is reproduced as a video, it will be a factor of deteriorating the image quality. Therefore, as shown in FIG. 6, a variable delay 87 is applied to the dot clock signal 84 in order to capture each dot appropriately and stably.
To adjust the phase with the video signal 81 to be A / D converted. At this time, the adjustment of the delay amount is performed through the delay amount control unit 88 by manual adjustment 89 by visual observation of the output screen or the like.

[0003]

However, in the above-mentioned conventional method, the sampling clock signal of the A / D conversion, which changes each time the video signal of the input computer device changes or changes with the passage of time, is used. The user has to manually adjust the phase shift of the video signal each time by visually checking the output screen or the like every time, which has a problem that a very troublesome operation is required. The present invention solves the above-mentioned conventional problems, and changes each time the input video signal of the computer device changes,
Alternatively, even if a phase shift occurs between the sampling clock signal of the A / D conversion and the video signal, which fluctuates due to aging,
It is an object of the present invention to provide an A / D converter that does not require a troublesome operation such as a manual adjustment by a user or the like by visually checking an output screen each time.

[0004]

In order to achieve this object, an A / D converter according to the present invention comprises a variable delay for shifting a sampling clock signal by an arbitrary time, and a variable delay for shifting the sampling clock signal by a predetermined minute time. First and second fixed delays for shifting ΔT, a first A / D converter for A / D converting an input video signal with the sampling clock signal to obtain a sample value, and A second A / D converter for A / D converting the input video signal with a clock signal shifted by a predetermined minute time ΔT by the first fixed delay to obtain a sample value; and the first fixed delay. in a predetermined minute time ΔT staggered clock signals further second third by a clock signal obtained by shifting a predetermined minute time ΔT at a fixed delay to obtain the sample value of the input video signal is a / D converted in the a / D conversion When the first and second and third A
The absolute value of the difference between each sampled value from the / D converter is calculated for each sampling cycle.
A / D of the calculated second in the absolute value and the second difference between the sample value from the third A / D calculator in the third A / D converter
The first and second A / s one sampling period after the conversion
Phase detection means for comparing the absolute value of the difference between each sample value from the D converter and outputting a comparison signal, and controlling the delay amount of the variable delay according to the comparison signal output detected by the phase detection means And a delay amount control means for outputting a control signal for detecting a phase shift between a video signal and a sampling clock signal as a comparison signal output of the phase detection means. The output control signal controls the delay amount of the variable delay to automatically adjust the phase shift between the video signal and the sampling clock signal. In addition, the present invention
A / D conversion device converts sampling clock signal into arbitrary time
A variable delay, and the sampling clock signal
The first fixed delay that is shifted by ΔT / 2, which is half of the minute time ΔT
A, and the sampling clock signal is shifted for a predetermined short time ΔT.
A second fixed delay and a sampling clock for the input video signal.
1st and 2nd for obtaining the sample value by A / D conversion with the
2 A / D converter and the sampling clock from the variable delay.
A lock signal and a sampling clock from the first fixed delay.
The second fixed signal is switched every one sampling cycle.
To the constant delay and the first A / D converter, respectively.
Switching means for switching the sampling clock signal.
The first fixed delay shifts by a predetermined minute time ΔT.
The input video signal is A / D converted by a lock signal and
Said second A / D converter for obtaining said value, and said switching means.
The first and second stages are switched according to the switching of the stage every sampling period.
Calculate the absolute value of the difference between each sample value from the A / D converter and
The first and second switching means in one switching state of the switching means.
The absolute value of the difference between the sample values from the A / D converter 2 and the second
One sample from the time of A / D conversion by the first and second A / D converters
Switching state of the other switching means after the switching cycle
Samples from the first and second A / D converters in a state
Phase detection that compares the absolute value of the
Output means and a comparison signal output detected by the phase detection means.
Controlling the delay amount of the variable delay according to
A delay amount control means for outputting a signal;
The video signal and the sampling clock
Detecting the phase shift of the reference signal and outputting the comparison signal.
Control signal output from delay amount control means according to force
To control the amount of delay of the variable delay
Automatically adjust phase shift of sampling clock signal
It was made.

[0005]

With this configuration, even if a phase shift occurs between the sampling clock signal for A / D conversion and the video signal, which changes each time the video signal of the input computer device changes, or fluctuates due to aging, etc. In each case, the video signal can be sampled at an appropriate timing without a troublesome operation such as a manual adjustment performed by a user or the like by visually checking an output screen.

[0006]

FIG. 1 shows an A / D converter according to a first embodiment of the present invention.
1 shows a schematic configuration of a conversion device. In FIG. 1, 1 is a video signal, 2 is a horizontal synchronizing signal, 3 is a digital signal, 4 is a dot clock signal, 5 is a PLL unit, 6 is a variable delay, 7, 8, and 9 are A / D converters, 11 and 12 are flip-flops (hereinafter referred to as FF), 13 and 14 are delays of a small time ΔT, 15 is a sample value Y (n · T + ΔT), 16 is an original sample value Y (n · T), and 17 is a sample. Value Y (nT-Δ
T) and 18 are a phase detector and 19 is a delay amount controller.
Here, T is a sampling period, and n is an integer. The same applies to the following. FIG. 2 shows the timing of FIG. 1, and FIG. 2A shows an example of a state where sampling is performed at an appropriate timing, and FIG. This is an example. In FIG. 2, 21 is a video signal, 22 is an original sample value Y (n · T), and 23 is a sample value Y
(n · T + ΔT), 24 is a sample value Y ((n + 1) · T−ΔT),
25 is the original sample value Y ((n + 1) .T). The operation of the A / D converter configured as described above will be described. As shown in FIG. 1, a video signal 1 such as a computer
First, the horizontal synchronizing signal 2 is multiplied by the PLL unit 5 to reproduce the dot clock signal 4, and the dot clock signal 4 is converted into a variable delay 6 by the A / D converter 8. And through a fixed ΔT delay 14 as a sampling clock signal. Further, before and after the time, the video signal 1 is sampled by the A / D converter 9 by a clock signal obtained by passing the dot clock signal 4 through the variable delay 6, and the dot clock signal 4 is further converted by the variable delay 6. The video signal 1 is converted to an A / D signal by a clock signal passing through the fixed ΔT delay 14 and the fixed ΔT delay 13.
Sampled by the D converter 7 and sampled values Y (n · T) 16, Y (n · T-ΔT) 17, Y (n
・ T + ΔT) 15 is obtained. FIG. 2 shows the timing of the sampled values and the video signal obtained in this manner. When the sampled values are sampled at appropriate timings as shown in FIG. The absolute value of the difference between the sample value 23 delayed by 22 and the minute time ΔT and the absolute value of the difference between the original sample value 25 and the sample value 24 advanced by the minute time ΔT are substantially the same. However, when the sampling is performed at a slightly shifted timing as shown in FIG. 2 (b), one of the two absolute values is larger than the other, and the absolute value is determined in accordance with which is larger or smaller. , It is possible to detect a phase shift between the video signal and the sampling clock signal. In FIG. 1, the phase shift is detected by a phase detector 18 which controls the variable delay 6 by a delay amount controller 19 in accordance with the detected phase shift, so that the video signal can be detected at an appropriate timing. Can be sampled. FIG. 3 shows a schematic configuration of an A / D converter according to a second embodiment of the present invention. In FIG. 3, 27 is a video signal, 28 is a horizontal synchronization signal, 29 is a digital signal, 30 is a dot clock signal, 31 is a PLL unit, 32 is a variable delay,
33 and 34 are A / D converters, 35 and 36 are FFs, 37 is a minute time Δ
T delay, 38 switcher, 39 minute time ΔT / 2
, 40 is a sample value Y {nT + (ΔT / 2)} (or Y (nT + ΔT)), 41 is a sample value Y {nT− (ΔT /
2)} or the original sample value Y (n · T), 42 is a phase detector,
43 is a delay amount control unit. FIG. 4 shows the timing. FIG. 4 (a) shows a state in which sampling is performed at an appropriate timing in a normal state, and FIG. 4 (b) shows a state when sampling is performed at an appropriate timing. FIG. 4C shows a state in which sampling is performed at a timing shifted from normal time, and FIG.
(d) This is an example of the state at the time of phase detection when sampling is performed at a deviated timing. In FIG. 4, 45 is a video signal,
46 is the original sample value Y (n · T), 47 is the original sample value Y {(n
+1) .T}, 48 are sample values Y {nT-([Delta] T / 2)}, and 49 are sample values Y {nT + ([Delta] T / 2)}. The operation of the A / D converter configured as described above will be described. As shown in FIG. 3, a video signal from a computer or the like is normally used.
In order to convert 27 into a digital signal 29 by an A / D converter 34, first, a horizontal synchronizing signal 28 is multiplied by a PLL unit 31 to reproduce a dot clock signal 30, and this dot clock signal 30 is variable-delayed. The signal is used as a sampling clock signal through a fixed .DELTA.T / 2 delay 39 at normal times by a switch 38. When the video signal of the input computer device is changed, or when the sampling clock signal of the A / D conversion and the video signal are shifted in phase due to aging or the like, and it is desired to match the phases, the switching unit 38 is used.
Is switched to the phase detection mode, the dot clock signal 30 is sampled by the A / D converter 34 by the clock signal passed through the variable delay 32, and the dot clock signal 30 is Fixed ΔT delay
The video signal 27 is sampled by the A / D converter 33 by the clock signal passed through 37, and sampled values Y {nT- (ΔT / 2)} 41 and Y {n · T + (ΔT / 2)}
Get 40. FIG. 4 shows the timing of the sample value and the video signal obtained in this manner.
In the case where sampling is performed at an appropriate timing as in (b), the difference between the sampled value 48 and the sampled value 49 which are shifted from the original sampled value by a very short time ΔT / 2 is small. However,
4C and 4D, the difference between the sample value 48 and the sample value 49 becomes large, and the video signal is changed according to the magnitude. And the phase shift between the sampling clock signal and the sampling clock signal. In FIG. 3, a phase detector 42 detects the degree of the phase shift, and the video signal is sampled by controlling the variable delay 32 by a delay amount controller 43 according to the detected phase shift. It is possible to appropriately control the timing of the execution.

FIG. 5 shows A / A in a third embodiment of the present invention.
1 shows a schematic configuration of a D conversion device. In FIG. 5, reference numerals 51, 52, and 53 denote respective color signals (red signal, blue signal, and green signal) of the video signal, 54, 55, and 56 represent digital signals, and 57
Is the original sample value clock signal, 58, 59, 60 are phase detection clock signals, 61, 62, 63, 64, 65 are switchers, 66, 67, 68 are A / D converters, 69, 69 70 and 71 are FF, 7
2, 73 and 74 are sample values for phase detection. The operation of the A / D converter configured as described above will be described. Generally, video signals from computers and the like are red,
It consists of blue and green color signals. As shown in FIG. 5, in normal times, the color signals 51, 52, and 53 of the video signal are converted by the switches 61, 62, 63, 64, and 65 using the original sample value clock signal 57 into A / The signals are sampled by the D converters 66, 67, 68 and converted into digital signals 54, 55, 56. When the video signal of the input computer device is changed, or when a phase shift occurs between the sampling clock signal of the A / D conversion and the video signal due to aging or the like, and it is desired to combine the phases, the switching units 61, 62, 63, 64, 65 are switched to the phase detection mode. For example, for the green signal 53 of the video signal, the A / D converters 66, 67 are respectively used by using the clock signals 58, 59, 60 for phase detection. , 68, and sample values 7 for phase detection by FF69, 70, 71
2, 73, 74 can be obtained. With this configuration,
Hereinafter, by using the same means as in the first embodiment or the second embodiment, it is possible to realize an A / D converter capable of sampling at an appropriate timing, and to realize a phase shift between the video signal and the sampling clock signal. It is not necessary to separately provide an A / D converter that is necessary for detecting.

[0008]

As described above, according to the present invention, the A /
According to the D converter, a phase shift occurs between the sampling clock signal of the A / D conversion and the video signal, which changes each time the video signal of the input computer device changes, or fluctuates due to aging. However, there is an effect that the video signal can be sampled at an appropriate timing without a troublesome operation such as a manual adjustment performed by the user or the like by visually checking the output screen each time.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the sampling of FIG. 1;

FIG. 3 is a schematic configuration diagram of an A / D converter according to a second embodiment of the present invention.

FIG. 4 is a timing chart of the sampling of FIG. 3;

FIG. 5 is a schematic configuration diagram of an A / D conversion device according to a third embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a conventional A / D converter.

FIG. 7 is a timing chart of the sampling of FIG. 6;

[Description of Signs] 1, 21, 27, 45, 81, 91: Video signal, 2, 28, 82: Horizontal synchronization signal, 3, 29, 54, 55, 56, 83: Digital signal, 4, 30, 84 … Dot clock signal, 5, 31, 86
… Phase locked loop (PLL) part, 6,32,87…
Variable delay, 7, 8, 9, 33, 34, 66, 67, 68, 85 ...
A / D converter, 10, 11, 12, 35, 36, 69, 70, 71 ... flip-flop (FF), 13, 14, 37 ... ΔT delay,
15, 23,..., Sample value Y (nT + ΔT), 16, 22, 46,
Sample value Y (n · T), 17 ... sample value Y (n · T−ΔT),
18, 42: phase detection unit, 19, 43, 88: delay amount control unit, 24: sample value Y {(n + 1) .T-ΔT}, 25, 47 ...
Sample value Y {(n + 1) .T}, 38, 61, 62, 63, 64, 65
... Switcher, 39 ... ΔT / 2 delay, 48 ... Sample value Y {nT- (ΔT / 2)}, 49 ... Sample value Y {nT + (Δ
T / 2)}, 51: red signal, 52: blue signal, 53: green signal, 57: clock signal for original sample value, 57,
58, 59: Clock signal for phase detection, 72, 73, 74: Sample value for phase detection, 89: Manual adjustment, 92: Standardized clock signal, 93: 1-dot width on screen, 94: Timing of standardization , 95 ... sampling period.

Continuation of front page (72) Inventor Takaaki Gyoten 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. , A1) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 1/00-1/88 H04N 5/14 H04N 7/00 H04N 11/04

Claims (2)

(57) [Claims] 1. A variable delay shifting the sampling clock signal to any time, the sampling clock signals, respectively predetermined minute time ΔT
First and second fixed delays to be shifted; a first A / D converter for A / D converting an input video signal with the sampling clock signal to obtain a sample value; A second A for A / D converting the input video signal by a clock signal shifted by a predetermined minute time ΔT by a first fixed delay to obtain a sample value
A / D converter, and A / D-converts the input video signal by a clock signal shifted by a predetermined minute time ΔT by the first fixed delay and further by a clock signal shifted by a predetermined minute time ΔT by the second fixed delay. A third A / D converter for obtaining a sample value from the first A / D converter, and an absolute value of a difference between each sample value from the first, second, and third A / D converters is calculated for each sampling period. And the second and third A
/ D The absolute value of the difference between the sample values from the arithmetic unit and the second and
1 sampling period from the time of A / D conversion in A / D converter 3
A phase detection means for outputting first and a comparison signal by comparing the absolute value of the difference between each sample value from the second A / D converter after, the comparison signal output detected by said phase detecting means Delay amount control means for outputting a control signal for controlling the delay amount of the variable delay in response to the detection of a phase shift between a video signal and a sampling clock signal as a comparison signal output of the phase detection means. The phase shift between the video signal and the sampling clock signal is automatically adjusted by controlling the delay amount of the variable delay by a control signal output from the delay amount control means according to the signal output. A / D converter. 2. The sampling clock signal can be shifted by an arbitrary time.
Variable delay, and the sampling clock signal is reduced to a half of a predetermined minute time ΔT.
A first fixed delay for shifting ΔT / 2, and a first fixed delay for shifting the sampling clock signal by a predetermined minute time ΔT.
2 fixed delay and A / D conversion of the input video signal with the sampling clock signal
First and second A / D converters for obtaining this value, the sampling clock signal from the variable delay and the first
Sampled clock signal from fixed delay
The second fixed delay and the first fixed delay are switched every cycle.
Switching means for supplying to each A / D converter
And the sampling clock signal is supplied by the first fixed delay.
The input is made by a clock signal shifted by a predetermined minute time ΔT.
A / D conversion of the video signal to obtain a sample value.
The D converter and the switching means are switched according to the switching for each sampling cycle.
The absolute value of the difference between each sample value from the first and second A / D converters
Calculate the value to switch to one of the switching means
The difference between each sampled value from the first and second A / D converters in
Absolute value and A / D conversion in the first and second A / D converters
Other than the switching means one sampling cycle after the time point
The first and second A / D conversion in the switching state
The comparison signal by comparing the absolute value of the difference between each sampled value from the
A phase detecting means for outputting the signal, and
Outputs a control signal to control the delay amount of the variable delay
Means for controlling the amount of delay, and a video signal and a sample as a comparison signal output of the phase detection means.
Detecting the phase shift of the normalized clock signal,
Output from the delay amount control means according to the comparison signal output
Controlling the delay amount of the variable delay with a control signal
Automatically adjusts phase shift between image signal and sampling clock signal
An A / D conversion device characterized in that the A / D conversion is performed.