JPH04291822A - A/d converter - Google Patents

Abstract

PURPOSE:To realize an A/D converter relieving the load of a DSP with simple constitution and for which a function is easily added. CONSTITUTION:An analog signal is converted into a digital data by an A/D converter section 111, the data is demodulated by the demodulation section 112 of a DSP 102 and a timing component is extracted by a timing extraction section 113. Then a lead/lag detection section 114 detects whether or not a reception operation timing is led to a modulation timing, and an up/down counter 115 makes count-up or count-down according to the result, a frequency division ratio setting section 116 adds or subtracts a basic frequency division ratio and an adjustment frequency division ratio according to the result, the result is given to a variable frequency divider section 117, from which an operating clock of the A/D converter section is outputted to the A/D converter section 111 to control the timing synchronization.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A/D converter that converts input analog signals into digital signals.

0002

2. Description of the Related Art FIG. 3 is a schematic block diagram showing the configuration of a conventional modem.

[0003] In the following, reception from the line side, particularly reception timing extraction and control, will be explained.

In the figure, reference numeral 301 is an A/D converter that converts an input analog signal into a digital signal, and reference numeral 302 is a digital signal processor (D) that performs digital signal processing including phase error detection processing.
SP).

First, an analog signal is sent to an A/D converter 301.
The signal is input to the A/D converter 311 of the DSP 302, converted into digital data, and then input to the demodulator 312 of the DSP 302. Next, a timing extractor 313 extracts a timing component based on the demodulated data, and a phase error detector 314 detects a phase error according to the extracted timing component. On the other hand, the variable frequency dividing section 316 which inputs the result of the phase error detecting section 314 can be finely adjusted, and its frequency division ratio is set in the frequency division ratio setting section 315.

Therefore, timing synchronization is performed by increasing/decreasing the frequency division ratio of the variable frequency divider 316 according to the phase difference between the modulation timing and the reception operation timing.

[0007]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, in order to set the frequency division ratio according to the amount of timing phase error in the frequency division ratio setting section 315, the digital signal processor (DSP) requires a complicated A timing phase error detection process is required, which increases the amount of DSP calculations and hinders the addition of functions.

The present invention was made to solve the above problems, and aims to provide an A/D converter that has a simple configuration, reduces the burden on the DSP, and can easily add functions. do.

[0009]

Means and Effects for Solving the Problems In order to achieve the above object, the A/D converter of the present invention has the following configuration.

[0010] That is, in an A/D converter that converts an input analog signal into a digital signal, an A/D conversion means that converts the input analog signal into a digital signal, and a conversion by the A/D conversion means. and control means for controlling timing based on lead/lag signals from the digital signal processor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an A/D converter 1 in this embodiment.
01 and digital signal processor (DSP) 1
FIG. 2 is a block diagram showing the configuration of 02.

First, the line interface is connected to the input of the A/D converter 111, its output is connected to the input of the demodulator 112 of the DSP 102, the output of the demodulator 112 is output to the timing extractor 113, and its output is connected to the input of the demodulator 112 of the DSP 102. Output advances/
It becomes an input to the delay detection section 114. Advance/delay detection section 11
4 is connected to the input of the up/down counter 115 of the A/D converter 101, and its output is connected to the input of the up/down counter 115 of the A/D converter 101.
There are 16 inputs. The output of the frequency division ratio setting section 116 becomes the input of the variable frequency division section 117, and the output of the variable frequency division section 117 is A
/D converter 111.

Next, the operation of this embodiment having the above configuration will be explained.

First, an analog signal is sent to the A/D converter 101.
The data is input to the A/D converter 111 of the A/D converter 111 and converted into digital data. The data is sent to the demodulator 11 of the DPS 102.
2 and is demodulated, the timing extractor 113
and the timing components are extracted. Then, the lead/lag detection section 114 detects whether the receiving operation timing is ahead or behind the modulation timing, and the result is input as binary information to the up/down counter 115 of the A/D converter 101. Ru. This up/
The down counter 115 counts up with a lead signal and counts down with a delay signal. When the count value reaches the upper or lower threshold, a phase control signal corresponding to the advance or delay is generated, and the counter is reset at the same time. The frequency division ratio setting unit 116 has a basic frequency division ratio and an adjustment frequency division ratio set in advance, and adds or subtracts the basic frequency division ratio and the adjustment frequency division ratio according to the input phase control signal, and the result is is output to the variable frequency divider 117 as a frequency division ratio. Then, in the variable frequency dividing section 117, timing synchronization is achieved by outputting the operating clock of the A/D converting section to the A/D converting section 111 according to the input frequency dividing ratio.

Here, for example, the reference clock is set to 1228.
8KHz, sampling clock 9.6KHz,
The initial value of the 4-bit up/down counter 115 is set to “1”.
000'', the upper threshold is ``1100'', and the lower threshold is ``1100''.
0100'' will be described below with reference to the timing chart shown in FIG.

When the count value of the up/down counter 115, which counts up by the lead signal from the lead/lag detector 114 of the DSP 102 and counts down by the delay signal, reaches the upper or lower threshold, the lead or lag is detected. Adv. as a corresponding phase control signal. signal or R
et. The signal is output to frequency division ratio setting section 116. On the other hand, if the basic frequency division ratio is set to 128 and the adjustment frequency division ratio is set to 2 in the frequency division ratio setting section 116, then the variable frequency division section 11
The frequency division ratio of Adv. 7 is normally 128. When a signal is input, its frequency division ratio is 128-2=126, and Ret. When a signal is input, its frequency division ratio is 128
+2=130.

By repeating the above operations, the A/D
Synchronizes the timing of the conversion operation reference clock.

The present invention may be applied to a system made up of a plurality of devices, or to a device made up of one device. It goes without saying that the present invention can also be applied to cases where the present invention is achieved by supplying a program to a system or device.

As described in detail above, according to this embodiment, when converting an input analog signal into a digital signal, the A/D converter, which can adjust the timing, adjusts the advance/delay of the timing of the reception operation. By providing averaging means for signals, the DSP only needs to detect whether the receiving operation timing is ahead or behind the modulation timing, eliminating the need for complex timing phase error detection processing, and reducing the DSP's This has the effect of reducing the burden and making it easier to add functions.

[0021]

[Effects of the Invention] As explained above, according to the present invention,
With a simple configuration, excellent effects can be obtained in that the burden on the DSP can be reduced and functions can be easily added.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an A/D converter and a DSP in this embodiment.

FIG. 2 is a timing chart showing the operation of FIG. 1;

FIG. 3 is a block diagram showing the configuration of a conventional A/D converter and DSP.

Claims (1)

[Claims] Claim 1: An A/D converter that converts an input analog signal into a digital signal, comprising: A/D conversion means for converting the input analog signal into a digital signal; and conversion by the A/D conversion means. Digital timing
An A/D converter comprising: control means for controlling based on a lead/lag signal from a signal processor.