JPS6170864A - Digital synchronizing separation clamp circuit - Google Patents

Abstract

PURPOSE:To reduce malfunction even with much noise by keeping the peak clamp operation when a difference between values before and after a pedestal level signal during one horizontal period so as to avoid the pedestal clamp mode. CONSTITUTION:An analog video signal 100 is digitized via an adder 1 and an A/D converter 3 and a synchronizing signal 300 is separated by a synchronizing separator circuit 5. The end of peak clamp is discriminated by a peak clamp end discrimination 13 by using a zero level detection signal 900 from a peak clamp control circuit 10 or an initializing signal 1500 from a pedestal level difference detection circuit 18. The pedestal level difference detection circuit 18 inputs a signal 1200 outputted from a pedestal level detection circuit 15 to detect the quantity of the difference between the present value and the value before one horizontal period and when the difference is large, the initializing signal 1500 is outputted to initialize the circuit 13.

Description

[Detailed Description of the Invention] [Technical Background of the Invention] Conventionally, in this type of digital synchronous separation clamp circuit (see Jibun Sho 57-124980), in order to effectively utilize the dynamic range of the A/D converter, , the DC component of the non-analog video signal is reproduced so as to match the dynamic range of the A/D converter.

However, when the analog video signal is not within the dynamic range of the A/D converter, peak clamping is performed digitally, and then when the analog video signal is within the dynamic range, the control loop is changed to pedestal clamping rather than peak clamping. By changing l/J to
ID strange pJ! This allows effective direct current reproduction even for analog video signals that exceed the dynamic range of the device.

At this time, the control loop 1. ? J switching is performed depending on whether a normal synchronization signal is obtained or not.

FIG. 3 is a block diagram showing an example of the conventional digital one-town separation circuit. The analog video signal 100 led from the input terminal is input to an analog adder circuit 41, added to the output of the D/A converter 42, and then inputted to the A/D converter 43. This A/D converter 43 receives a sampling clock (a) supplied from a clock generation circuit 44.
"i, the analog video signal 1oO is digitally converted. The output 200 of the A/D converter 43 is supplied to a predetermined next-stage circuit via an output terminal, and is also supplied to a synchronous separation circuit 45 and a comparison circuit. The circuit 46 and the pedestal extraction circuit 47 are each supplied with a digital signal of a predetermined level generated by the peak clamp level generation circuit 48, and the comparison circuit 46 compares this digital signal with the digital signal 200 and makes a determination. The output is given to one terminal of the switching circuit 49.Here, the level of the digital signal generated by the peak clamp level generating circuit 48 is A.
/[) is set near the minimum value of the dynamic range of the converter 43. Therefore, the determination output of the comparison circuit 46 supplied to the switching circuit 49 serves as a stop signal for peak clamp control, which will be described in detail later, and causes the integration circuit 56 to stop operating. Furthermore, a predetermined timing signal generated by a timing generation circuit 50 which operates in response to the synchronization signal separated by the synchronization separation circuit 45 is inputted to the other terminal of the switching circuit 49. This timing signal is supplied to the integration circuit 56 as a clock.

Now, the synchronization separation circuit 45 separates the synchronization signal t! from the input digital video signal 200. At the same time, it is determined whether the separated signal 11'l is normal or not. When the synchronization signal is not normal, the synchronization separation circuit 45 issues a signal to the switching control circuit 55. Switching control circuit 5
5 controls the switching of the switching circuits 49 and 53 and supplies the relet signal to the integrating circuit 56 depending on the presence or absence of this signal, and switches the control mode of the circuit into two as follows.

In other words, if the analog video signal output from the analog adder circuit 41 is out of the dynamic range of the A/D converter 43, a normal synchronization signal cannot be extracted from the output of the A/D converter 43. Since it is not possible, the synchronous separation circuit 4
5 supplies a signal to a switching control circuit 55. After receiving this signal, it was 1.7J! pj! The control circuit 55 resets the product 0 minute circuit 56, and the switching circuit 53 resets the constant value generation circuit 5.
The switching circuit 49 performs switching control so that the output of the comparing circuit 46 is selected for the integrating circuit 56. Therefore, when the synchronization signal is not separated normally, the A/D converter 43, the peak clamp level generation circuit 48, the comparison circuit 46, the constant value generation circuit 54, the integration circuit 56, the [)/A converter 42, and the addition A kind of peak clamp control loop is formed by the circuit 41, which clamps the leading level of the horizontal synchronization signal.

However, in the peak clamp state, the integration circuit 56
integrates the output of the constant value generation circuit 54 using the output of the comparison circuit 46 as a clock, and the integrated value increases with the passage of time. This integral output is converted to [)/A and added to the adder circuit 4.
1, so the A/D converter 431. : The level of the 1111th low wing tip of the 7J log video Ini bow is raised. The top level of the synchronization signal of the digitally converted video signal is the peak clamp level generation circuit 48.
The integration circuit 56 continues to integrate a constant digital signal until the output level exceeds the output level of the peak clamp level generation circuit 48. circuit 5
6 is stopped and the peak clamp control is stopped.

Next up is Jiil! After the IJI signal is peak-clamped, the synchronization signal is normally separated by the synchronization separation circuit 45. The correctly separated synchronization signal is given to a pestal extraction circuit 47. Pedestal extraction circuit 47
extracts the pedestal portion of the digital signal 200 output from the A/[) converter 43 in response to this synchronization signal,
Detecting the pedestal level. The pedestal level thus detected is led to a pedestal level error computation circuit 51, and is compared with the pair 8 quasi-level generated by the reference level generation circuit 52 to calculate the error. As a result, the error of the pedestal level,
That is, a level error is determined, and this level error is supplied to the switching circuit 53. In a state where the synchronization signal is normally separated, the synchronization separation circuit 45 does not supply a signal to the switching system 00 circuit 55. At this time, the switching control circuit 55 causes the switching circuit 53 to selectively output the level error, and the switching FA circuit 49 causes the timing generation circuit 5o to selectively output the level error.
Switching control is performed so that the output of 1 is supplied to the integrating circuit 56. Therefore, a pedestal clamp control loop is formed such that the pedestal level is clamped to the reference level that is the output of the reference level generation circuit 52 when the synchronization signal is normally divided. As a result, the DC component lost in the video signal 100 is compensated for by the output of the D/A converter 42, and the pedestal level of the video signal 200 matches the reference level. In other words, direct current is regenerated.

[Problems in the Background Art] As mentioned above, in the conventional separation clamp circuit, switching between the peak clamp & lJ all mode and the pedestal clamp control mode is performed depending on whether a correct synchronization signal is obtained, and the peak clamp At the start of control, the integrating circuit 56 is reset. Further, the termination of the peak clamp control is determined based on whether the leading edge level of the synchronization signal of the digital video signal exceeds a predetermined value.

By the way, if the analog video signal 100 is received by weak electric field broadcasting or the like and contains many noise components as shown in FIG.
It becomes difficult to perform correct synchronization separation in the synchronization separation circuit 45. Therefore, if peak clamp control is performed and the synchronization signal leading edge level of the digital video signal exceeds a predetermined value, and after peak clamp control is stopped, a video signal containing many noise components as described above arrives, the synchronization separation circuit 45 Since synchronous separation cannot be performed correctly, peak clamp control is started via the re-1 attenuation switching control circuit 55 even though peak clamping has ended. At this time, the integrating circuit 56 is reset again as described above. For this reason, the video signal output from the analog adder circuit 41 has a crowded DC component, and
It had a drawback that made it very unsightly for art dealers.

OBJECT OF THE INVENTION In view of the above drawbacks, an object of the present invention is to provide a digital synchronous clamp circuit that can be expected to operate with high reliability without malfunction even with noisy video signals.

[Summary of the Invention J The present invention first applies a peak clamp to bring the input analog video signal within the A/D conversion dynamic range, and then uses a pedestal clamp to bring the pedestal level of the analog video signal to a target level. A digital synchronization separation clamp circuit 15 separates the same signal from the digital video signal output from the A/D converter in accordance with the current value of the pedestal level signal one horizontal frame ago. Compare the pedestal level signal value and
If the difference between the two is large, it initializes the peak clamp end judgment circuit, maintains the peak clamp operation, and prevents the transition to the pedestal clamp operation by providing a basic level difference detection circuit. It is something to be achieved.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the digital synchronous separation clamp circuit of the present invention. analog video signal 1
00 is D/A changed 4I! by analog adder circuit 1! ! The DC component from device 2 is processed and this is A/D conversion 4! The iQ unit 3 converts it into a digital video signal @20°. The synchronization separation circuit 5 manually inputs the digital video signal 200 and separates the composite synchronization signal 300. At this time, the horizontal synchronization detection and timing generation circuit 6 generates a composite 761 period signal 30.
The horizontal direction 11] signal 400 detected from 0 is input to the synchronization establishment signal generation circuit 7, where it is determined by the synchronization separation circuit 5 whether or not the 1i''11 period separation is normally performed. 7 operates the 7-mode switching circuit 8 by the 1./J switching low signal 500 when synchronization separation is not performed, and the data selector 11 operates the peak clamp control signal 700 from the peak clamp control circuit 10. The control loop is switched to select and output this.This causes the A/D converter 3, zero level detection circuit 9.Peak clamp control circuit 10.Data selector 11.Error integration circuit 12.D/A conversion !a2. A peak clamp aI11 control loop is formed by the analog addition Q circuit 1, and a peak clamp operation similar to that described in the conventional example is performed.

The peak clamp end determination circuit 13 determines whether the peak clamp i
,! The peak clamp end is determined based on both the zero level detection signal 9()0 from the 160 circuit 10 and the initialization signal 15(M) output from the pedestal level difference detection circuit 18, and the peak clamp end signal i ooo is set to the mode. Output to switching circuit 8. In addition, the pedestal level difference detection circuit 1
8 inputs the pedestal level detection signal 1200 output from the pedestal level detection circuit 15, and calculates the difference between the current value of this pedestal level detection signal 120 () and the value of the same signal detected one horizontal m interval ago. The magnitude is detected, and if the difference is large, initialization (S) 31500 is outputted to the peak clamp end determination circuit 13 (this circuit 13 is initialized).

The peak clamp end determination circuit 8 is a peak clamp end determination circuit 8.
/) Receives the peak clamp end signal 100G from X and others, and receives the switching signal 500 from the synchronization establishment signal generation circuit 7
is a signal for switching to the pedestal clamp 1 side), the switching signal 800 is output to the data selector 1, and this data selector 11 outputs the difference signal that the error calculation circuit 14 outputs via the time constant switching circuit 17. 1300 and switches the data selector 11 to output it to the error integration circuit 12. As a result, the A/D converter 3, the pedestal level detection circuit 15. Error calculation circuit 1
4. Data selector 11. Error integration circuit 12゜1)/A
A pedestal clamp loop fl1 control system is formed by the converter 2, 7, 9 circuit 1, and the pedestal clamp operation similar to the conventional example is performed.

Next, the operation of this embodiment will be explained in more detail with reference to FIG. Normally, at the initial stage when the analog video signal 100 starts to be input to the analog adder Q circuit 1, the analog video signal output from the adder Q circuit 1 is as shown in Figure M2 (A). <A/[) may deviate from the dynamic range (oooooooo~11111111) of the converter 3. In such a state, the period separation circuit 5 detects the digital video signal converted by the A/D converter 3. When the same il1 separation is performed from 200, the compound direction!#J 8300 becomes as shown in Fig. 2 <13>. That is,
For an analog video signal (A) whose IIJ(, i @ part is lower than the lowest level of the dynamic range of the A/D converter 3), the width is wider than the actual periodic signal like (A). A wide pulse signal is obtained, and the A/D
For the analog video signal (b) in which 51 portions are above the highest level of the dynamic range of the converter 3, no signal is detected as shown in (b). If the synchronization separation circuit 5 does not perform normal synchronization separation as described above, the synchronization establishment signal generation circuit 7 determines that the normal f, 1st period signal is not obtained, as described above, and disconnects 4'iE! (V is used as a signal to switch 5H500 to the peak cranno lube side. This I and receive this 1) The mode switching circuit 8 transfers the switching signal 800 to the data level getter 1.
1 to form a peak clamp υ control loop.

When the peak clamp starts operating, for the analog video signal shown in (a) of FIG. 2(A).

h-i trt Since the tip of No. 1g is at F below the lowest level of the dynamic range of A/l) converter 3, the addition Q
Control is performed to add the C DC component to the circuit 1, thereby raising the level of the signal. In the case of the analog video signal shown in (B) of Figure 2 (A>), the leading edge of the IfJ signal is above the lowest level of the dynamic range, so the analog adder circuit 1 is controlled to subtract the DC component. The level of this analog video signal is lowered.By performing such a peak clamp operation, a state as shown by (C) in M2 diagram (C) is obtained in the peak clamp convergence state.

In such a state, the tongue level detection signal 900 output from the peak clamp m control circuit 10 alternately crosses the zero level to 4Et#'J. The peak clamp end determination circuit 13 counts the number of images of the manually input zero level detection signal 900, and when this count reaches 15, peak clamp ends (341000 is output to the mode switching circuit 8. , in the state f& of (c) in FIG.
In the J-frame separation circuit 5, normal synchronization separation is performed. Therefore, the synchronization establishment signal generation circuit 7 outputs the switching signal 500 to the pedestal clamp loop side. Therefore, the ~[-tri switching circuit 8 outputs the switching signal 800 to the data selector 11, causes the data selector 11 to select the error signal 130G from the error calculation circuit 14, and outputs this to the error integration circuit 12. The pedestal clamp loop is formed as described above, and the pedestal clamp operation is started.

This pedestal clamp operation is performed so that the error signal 1300Ifi output from the error calculation circuit 14 becomes zero.
Control is performed so that the pedestal level of the analog video signal matches the target pedestal level P1-. The state shown in (d) of FIG. 2(C) is such a state, in which the pedestal level of the analog video signal matches the target pedestal level PL.

However, when transitioning from the e1 peak clamp operation to the pedestal clamp operation, if the noise component of the analog video signal 100 is large, as described in the conventional example, even if the peak clamp end determination circuit 13 outputs the peak clamp end signal 100G. Even if the synchronization establishment signal generation circuit 7 determines that the synchronization separation is normal, the accurate pedestal level may not be detected due to the detection of the picture part of the analog video signal 8 or noise, etc. is expected.

However, in this embodiment, the pedestal level difference detection circuit 18
The current value of the pedestal level signal 120G and the pedestal level signal 1 detected one horizontal period FM ago are calculated by
The values of 2GO are compared, and the peak clamp end signal 1000 is output from the peak clamp end determination circuit 13 only when the difference is small. That is, if the difference is large, the pedestal level difference detection circuit 18 initializes (outputs No. 8 1500 to the peak clamp end determination circuit 13, initializes the h counter in the peak clamp end determination circuit 13, and returns it to zero level. The colors of the detection signal 900 are redone.Therefore, the peak clamp end signal 1()()() is not output to the mode switching circuit 8.

Here, the operating principle of the pedestal level detection circuit 18 will be explained. That is, when the pedestal level detection signal 120G output from the pedestal level detection circuit 15 is normal, the time constant of the clamp is much larger than one horizontal period, so the pedestal level detection signal 120G within one horizontal period is Level changes are very small.

Therefore, if the level difference between the pedestal level detection signals 120G is small within one horizontal frame, it can be determined that the pedestal level detection signals 1200 are normal.

According to this embodiment, when the pedestal level difference detection circuit 18 detects that the pedestal level detection circuit 15 does not detect a normal pedestal level, such as when the analog video signal 100 has many noise components, the peak clamp end determination is made. In order to initialize the circuit 13 and prevent the generation of the peak clamp end signal 1000, the peak clamp operation is continued and the transition to the pedestal clamp operation is prevented even though the synchronization signal is not normally separated. It can be done. Therefore, in the present embodiment, highly reliable operation without malfunction can be expected even for video signals with a large number of Xi ffl.

F Effect of the Invention J As described above, according to the digital synchronous separation clamp circuit of the present invention, the current value of the pedestal level signal is compared with the value of the same signal detected one horizontal period ago, and the difference between the two is determined. If this is large, the peak clamp end judgment circuit is initialized and the peak clamp operation is continued in the I8 configuration, so that reliable operation without malfunction can be expected even for video signals with many miscellaneous components. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the -I digital synchronous separation clamp circuit of the present invention, Fig. 2 is an operating waveform diagram of the small k circuit in Fig. 1, and Fig. 3 is a conventional digital synchronous separation clamp circuit. FIG. 4 is a block diagram showing an example of a clamp circuit, and a waveform diagram showing an example of an analog video signal with many noise components. 1--Analog addition circuit 2--D/A converter 3-
- AID converter 5 - Synchronization separation circuit 7 Synchronization establishment signal generation circuit 8 Mode switching circuit 10 Peak clamp control circuit 11 Data selector 12 Error integration circuit 13 ...Peak clamp termination circuit 14...Error calculation circuit

Claims (1)

[Claims] Apply peak clamp to the input analog video signal
After placing the analog video signal within the dynamic range of the D converter, a pedestal clamp is applied to converge the pedestal level of the analog video signal to a target level while synchronously separating the synchronization signal from the digital video signal output from the A/D converter. A digital synchronization separation clamp circuit separated by a circuit includes a peak clamp end determination circuit that generates a peak clamp end signal that stops peak clamping when the number of times the leading edge of the synchronization signal crosses a reference level reaches a predetermined value, and The current value of the pedestal level signal detected from the digital video signal is compared with the value of the same signal detected one horizontal period ago, and if the difference between the two is large, the counting operation of the peak clamp end determination circuit is initialized. 1. A digital synchronous separation clamp circuit characterized in that a pedestal level difference detection circuit is provided to prevent peak clamp end signals from being generated and to maintain peak clamp operation.