JPH05276038A - A/d converter device - Google Patents

Abstract

PURPOSE:To sample a video signal by using a clock of a same frequency as a dot clock frequency of the video signal even when the dot clock information of the video signal is not clear. CONSTITUTION:A video signal 1 is sampled by using a clock signal through a variable delay circuit 6 and a fixed DELTAT delay circuit 11, and a phase difference detection section 14 detects a state of a phase shift between the video signal and a sampling clock signal over one horizontal period by using the obtained sampling values Y(n.T)13, Y(n.T+DELTAT)12. A multiple factor control section 15 sets a proper multiple factor in response to the detected phase difference. Then the video signal is sampled by using a clock signal having the same frequency as that of a dot clock signal of the video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for processing a video signal of a computer or the like.

[0002]

2. Description of the Related Art In recent years, the progress of digital signal processing technology has been remarkable, and interest in A / D conversion for converting an analog signal into a digital signal and D / A conversion for converting a digital signal into an analog signal is high.

Generally, when an analog signal is A / D converted, it is important how the frequency component of the input signal can be correctly transmitted. The basic Nyquist sampling theorem is at least twice the maximum frequency to be handled. Indicates the need to sample. On the other hand, in order to A / D convert a video signal in a personal computer, a work station, a graphic station, or the like as accurately as possible, it is optimal to sample with the dot clock itself that constitutes the screen.

A conventional A / D converter for a video signal of a computer or the like will be described below with reference to the drawings.

FIG. 5 shows an example of a schematic structure thereof. In FIG. 5, reference numeral 51 is a video signal, 52 is a horizontal synchronizing signal, 53 is a digital signal, 54 is a dot clock signal, 55 is an A / D converter, 56 is a multiplier, 57 is a variable delay, and 58 is a multiplication rate setting unit. , 59 indicates analogy of an input video signal or manual setting.

FIG. 6 shows the timing. In FIG. 6, 61 is a video signal, 62 is a sampling clock signal, 63 is the width of one dot on the screen, 64 is a sampling timing, and 65 is a sampling period T.

In order to A / D convert a video signal of a computer or the like, it is desirable to use the dot clock signal as a sampling clock signal. However, actual computer devices often do not output this dot clock signal to the outside. In that case, as shown in FIG.
The output horizontal synchronizing signal 52 is multiplied by a multiplier 56 to reproduce a dot clock signal 54, and the dot clock signal 54 is sampled and used as a clock signal. The video signal 51 is digital signal 53 by an A / D converter 55. Convert to. At this time,
The multiplication rate is set by analogy with the input video signal using an input synchronizing signal or the like, or by manual setting 59 via the multiplication rate setting unit 58.

Another problem that must be taken into consideration when performing A / D conversion with a clock signal having the same frequency as the dot clock signal of the video signal is the phase of the sampling clock signal and the video signal. This phase is slightly deviated due to individual variations, even for video signals of the same standard of the same type of computer, and if it exceeds the allowable range, it becomes noise for the processing system in the subsequent stage, and if reproduced as a video, the image quality will be It causes deterioration. Therefore, in order to properly and stably take in one dot and one dot, as shown in FIG. 5, a method of providing a variable delay 57 for the dot clock signal 54 and adjusting the phase with the video signal 51 to be A / D converted. Is taken.

[0009]

However, in the above-mentioned conventional method, when the video signal of the computer device which does not output the dot clock signal is A / D converted, the information regarding the dot clock must be known in advance. However, if this is not known, an accurate multiplication factor cannot be set, so one dot cannot be properly captured, and the user must manually set the multiplication factor by visually checking the output screen. It had a very difficult problem.

The present invention solves the above-mentioned conventional problems, and provides an A / D converter capable of sampling with a clock of the same frequency even when there is no information about the dot clock of the video signal of the input computer device. The purpose is to do.

[0011]

To achieve this object, an A / D converter according to the present invention comprises a multiplier for reproducing a sampling clock signal from a horizontal synchronizing signal, and a fixed delay for shifting the sampling clock signal by a minute time. And an A / D converter that obtains a sample value shifted by a minute time by a fixed delay, and a phase shift of the sampling clock signal and the video signal over one horizontal period from the sample value shifted by a minute time and the original sample value. It has a configuration including a phase difference detection unit for detecting a state and a multiplication rate control unit for controlling the frequency of the sampling clock signal according to the detected state of the phase difference.

[0012]

With this configuration, even when there is no information about the dot clock of the video signal of the input computer device, the clock signal having the same frequency as the dot clock signal of the video signal can be reproduced and sampled.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a schematic configuration of the first embodiment. 1 is a video signal, 2 is a horizontal synchronizing signal, 3 is a digital signal, 4 is a dot clock signal, 5 is a multiplier, 6 is a variable delay, 7 and 8 are A / D converters, 9 and 10 are flip-flops (hereinafter FF), 11 is a delay of a minute time ΔT, 12 is a sample value Y
(N · T + ΔT), 13 is the original sample value Y (n · T),
Reference numeral 14 is a phase difference detection unit, and 15 is a multiplication rate control unit. Here, T is a sampling period, n is an integer, and the same applies below.

FIG. 2 shows the timing of sampling, FIG. 2 (a) shows an example of a state in which sampling is performed at almost proper timing, and FIG. 2 (b) shows a considerable deviation. This is an example of a state in which sampling is performed at different timings. Figure 2
, 21 is the video signal, 22 is the original sampled value Y (n
.T), 23 is the sample value Y (n.T + .DELTA.T), 24 is the original sample value Y ((n + 1) .T), and 25 is the sample value Y ((n
+1) · T + ΔT).

FIG. 3 shows the state of the phase shift between the sampling clock signal and the video signal over one horizontal period. FIG. 3 (a) shows the same frequency as the dot clock signal of the video signal. Sampling with the clock signal of Fig. 3
FIG. 3B is a sampling with a clock signal having a frequency higher by one clock than the dot clock signal of the video signal, FIG.
Is an example of a state in which sampling is performed with a clock signal having a frequency higher by 2 clocks than the dot clock signal of the video signal.

With respect to the A / D converter including the above-mentioned respective constituent elements, the relation and operation of the respective constituent elements will be described.

As shown in FIG. 1, in order to convert a video signal 1 from a computer or the like into a digital signal 3 by an A / D converter 8, first, a horizontal synchronizing signal 2 is multiplied by a multiplier 5 to generate a dot clock. Regenerate signal 4. However, the dot clock signal 4 is not always reproduced as a clock signal having the same frequency as the dot clock signal of the video signal 1. This dot clock signal 4 is changed to a variable delay 6
The video signal 1 is sampled by the A / D converter 8 by the clock signal passed through the A / D converter 8 and the video signal 1 is converted by the A / D converter 8 through the variable delay 6 and the fixed ΔT delay 11. Sampling is performed by the / D converter 7, and the sampled value Y (n
・ T) 13 and Y (n · T + ΔT) 12 are obtained.

FIG. 2 shows the timing of the sampled value and the video signal obtained in this way, but when sampling is performed at almost proper timing as shown in FIG. 2 (a), The difference between the original sampled value 22 and the sampled value 23 delayed by the minute time ΔT becomes small. However, when sampling is performed at timings that are considerably deviated from each other as shown in FIG. 2B, the difference between the two sample values becomes large. Therefore, the difference between the sample values causes the difference between the video signal and the sampling value. It is possible to detect the phase shift state of the clock signal.

In FIG. 1, the phase difference detecting section 14 detects the phase shift state, and FIG. 3 shows an example in which the phase difference is shown over one horizontal period.

FIG. 3A shows an example of sampling with a clock signal having the same frequency as the dot clock signal of the video signal, and the phase difference between the video signal and the sampling clock signal is 1.
It has a constant value α over the horizontal period. In this case, by controlling the variable delay 6 in FIG. 1 to adjust the phases of the video signal and the sampling clock signal, it is possible to perform sampling in which one dot is properly captured.

FIG. 3B shows an example of sampling with a clock signal having a frequency higher by one clock than the dot clock signal of the video signal. In FIG. 3B, at point A of one horizontal period. The phase difference between the video signal and the sampling clock signal is the smallest, and the phase difference is the largest at point B in one horizontal period, and changes by one cycle in one horizontal period.

FIG. 3C shows an example of sampling with a clock signal having a frequency higher by 2 clocks than the dot clock signal of the video signal. In FIG. 3C, a point C of one horizontal cycle and The phase difference between the video signal and the sampling clock signal is the smallest at point E, and the phase difference is the largest at points D and F in one horizontal cycle, and changes by two cycles in one horizontal cycle.

As described above, according to the present embodiment, the horizontal synchronizing signal 2 is multiplied by the multiplier 5 depending on how many cycles the phase difference changes in the positive direction or the negative direction in one horizontal cycle. It is possible to know how many clocks the frequency of the obtained dot clock signal 4 is set higher or lower than the frequency of the dot clock signal of the video signal 1. Therefore, the phase difference detection unit 14 detects the video signal 1 The phase shift state between the sampling clock signal and the sampling clock signal can be detected over one horizontal period, and an appropriate multiplication factor can be set by the multiplication factor control unit 15 from the result.

When the frequency of the dot clock signal 4 is about one half of the frequency of the dot clock signal of the video signal 1, if the frequency of the dot clock signal 4 is increased or decreased by one clock, the video signal 1 in one horizontal cycle. When the frequency of the dot clock signal 4 is twice as high as the frequency of the dot clock signal of the video signal 1, the above phase difference is 1 for each sampling point.
If the frequency of the dot clock signal 4 is changed by 80 degrees and the frequency of the dot clock signal 4 is increased / decreased by one clock, the phase difference with the video signal 1 in one horizontal cycle changes in half cycle units. Is also possible.

(Embodiment 1) A second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a schematic structure of the second embodiment. Reference numerals 31, 32, and 33 denote color signals (red signal, blue signal, green signal) of video signals, and 34, 35, and 36.
Is a digital signal, 37 is an original sampling clock signal, 38 is a phase difference detection clock signal, 39 and 40 are sample values for phase difference detection, 41 and 42 are switchers, 4
3, 44 and 45 are A / D converters, and 46 and 47 are FFs.

With respect to the A / D conversion device composed of the above components, the relationship and operation of the components will be described.

Generally, a video signal of a computer or the like is
It is composed of red, blue, and green color signals. As shown in FIG. 4, under normal conditions, the color signals 31, 32, and 33 of the video signal are switched by the switchers 41 and 42 by using the clock signal 37 for the original sample value and the A / D converter 43, Four
Sampled at 4,45 and digital signals 34,35,
Converted to 36.

When the dot clock of the video signal of the input computer device is unknown and proper sampling cannot be performed, the switching devices 41 and 42 are switched to the phase difference detection mode, for example, with respect to the green signal 33 of the video signal. , A / D converters 45 and 44 using the original sample value clock signal 37 and the phase difference detection clock signal 38.
And sampled values 39 and 40 for phase difference detection can be obtained from the FFs 47 and 46.

With this configuration, if the same means as in the first embodiment is used, the same as the dot clock signal of the video signal, even if the information about the dot clock of the video signal of the input computer device is not known. An A / D converter capable of reproducing and sampling the frequency clock signal can be realized, and this embodiment also detects the phase shift between the video signal and the sampling clock signal as in the first embodiment. It is not necessary to separately provide the required A / D converter.

[0032]

As is apparent from the above embodiments, according to the present invention, a multiplier for reproducing a sampling clock signal from a horizontal synchronizing signal, a fixed delay for shifting the sampling clock signal by a minute time, and a minute delay by a fixed delay. An A / D converter that obtains sample values that are shifted in time, and a phase difference that detects the state of phase shift between the sampling clock signal and the video signal over one horizontal period from the sample values that are minutely offset and the original sample values A detection unit and a multiplication rate control unit that controls the frequency of the sampling clock signal according to the detected phase difference state are provided.The multiplication unit is operated via the multiplication rate control unit, and the dot clock signal of the video signal and Since the clock signal of the same frequency is reproduced and sampled, even if you do not know the information about the dot clock of the video signal of the input computer device, you can use it. Without the cumbersome difficult operation of manually setting the multiplication factor but by including visual output screen can be sampled by reproducing the clock signal having the same frequency as the dot clock signal of the video signal A / D
A converter can be provided.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an A / D conversion device according to an embodiment of the present invention.

FIG. 2A is a schematic diagram showing a state in which sampling is performed at almost appropriate timing, and FIG. 2B is a schematic diagram showing a state in which sampling is performed at a timing that is considerably shifted.

FIG. 3A is a schematic diagram showing a phase difference when sampling is performed with a clock signal having the same frequency as the dot clock signal of the video signal, and FIG. 3B is a clock signal having a frequency higher by one clock than the dot clock signal of the video signal. Schematic diagram showing the phase difference when sampled in (c) Schematic diagram showing the phase difference when sampled with a clock signal having a frequency that is two clocks higher than the dot clock signal of the video signal

FIG. 4 is a schematic block diagram of an A / D conversion device according to a second embodiment of the present invention.

FIG. 5 is a schematic block diagram of a conventional A / D conversion device.

FIG. 6 is a schematic diagram for explaining sampling timing.

[Explanation of symbols]

 5 Multiplier 6 Variable delay 7,8 A / D converter 9,10 FF 11 Minute time ΔT delay (fixed delay) 14 Phase difference detection unit 15 Multiplication ratio control unit

Claims (2)

[Claims] 1. A multiplier for reproducing a sampling clock signal from a horizontal synchronizing signal, a fixed delay for shifting the sampling clock signal by a minute time, and an A / D converter for obtaining a sample value displaced by a minute time by the fixed delay. A phase difference detecting means for detecting a phase shift state of the sampling clock signal and the video signal over one horizontal period from the sample value shifted by the minute time and the original sample value; and the detected phase difference state. According to the above, a multiplication rate control unit for controlling the frequency of the sampling clock signal is provided, and the multiplication unit is operated via the multiplication rate control unit to reproduce a clock signal having the same frequency as the dot clock signal of the video signal. A / D conversion device adapted for sampling. 2. An A / D converter which is provided with a switching device for switching a video signal and a clock signal at the time of normal phase detection and phase difference detection, and which is an A / D converter for obtaining an original sample value in normal time The A / D conversion device according to claim 1, wherein the A / D conversion device is used by switching for obtaining.