JPH04263534A - Phase control circuit - Google Patents

Abstract

PURPOSE:To automatically correct the phase deviation of plural data signals without troubling human labor. CONSTITUTION:This circuit is provided with a phase comparator 18 detecting the phase deviation of respective clock waveforms reproduced by a clock reproducing circuit 14, and a level converter 20 outputting a control voltage is proportion to the phase deviation. Then, a continuous variable phase shifter 21 corrects the clock phase for retiming of the data signal by the above-mentioned control voltage.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit that performs phase control processing on a plurality of data signals such as baseband signals of digital radio equipment. [0002] FIG. 4 is a block diagram showing a conventional phase control circuit. In the figure, 1 and 2 are flip-flops for retiming, 3 and 4 are data input terminals, and 5 is a retiming flip-flop. clock input terminals, 6 and 7 are DC amplifiers, 8,
9 is a low-pass filter, 10 is a phase shifter, 11 and 12 are data output terminals, and 13 is a phase shifter adjustment terminal. Next, the operation will be explained. First, the flip-flops 1 and 2 retime the two systems of baseband signals input from the data input terminals 3 and 4 using the clock input from the clock input terminal 5. The DC amplifiers 6 and 7 offset the DC potential of these retimed baseband signals to bring the DC potential to zero volts. The baseband signal thus subjected to DC offset is band-limited by low-pass filters 8 and 9 and output from data output terminals 11 and 12. In this case, it is the person who determines the phase shift between the output baseband signals of these two systems, who monitors the waveform of the output baseband signal on an oscilloscope and makes sure that the phase shift becomes zero while looking at the waveform. In addition, a correction signal for adjustment is artificially input to the phase adjustment terminal 13 of the phase shifter 10. [0004] Since the conventional phase control circuit is configured as described above, the phase shift can be determined by the human eye on an oscilloscope, and the phase shift can be corrected manually. This poses problems, such as not only not being able to perform highly accurate adjustments, but also not being able to respond to changes in the external environment, and requiring human intervention. The present invention was made to solve the above-mentioned problems, and it is possible to perform a phase correction operation of a data signal without the need for human intervention, and also to adjust the phase shift of a plurality of data signals with high precision. The purpose of this invention is to obtain a phase control circuit that can compensate for [Means for Solving the Problems] A phase control circuit according to the present invention includes a phase comparator that detects a phase shift of each clock waveform reproduced by a clock regeneration circuit, and a control voltage proportional to the phase shift. The continuously variable phase shifter is configured to correct the clock phase for retiming the data signal using the control voltage. [Operation] The phase control circuit according to the present invention regenerates the clock of the baseband signal as a data signal, detects the phase difference between the respective clocks, obtains an output proportional to the phase difference, and uses the output to obtain an output proportional to the phase difference. Control a continuously variable phase shifter. Thereby, the clock phase for retiming of one baseband signal is changed to correct the phase shift of the output baseband signal obtained from the data output terminal. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 14 and 15 are full-wave rectifier circuits as clock regeneration circuits that rectify the output baseband signals from the low-pass filters 8 and 9 to regenerate clock components;
17 is a bandpass filter that band-limits the rectified output to remove jitter; 18 is a phase comparator that compares the phases of two band-limited clocks; 19 is a low-pass filter; and 20 is a low-pass filter 1.
A level converter 9 converts the level of the output signal to obtain a control voltage, and 21 is a continuously variable phase shifter that is controlled based on the level converted output. Note that other blocks that are the same as those in FIG. 4 are given the same reference numerals, and redundant explanation thereof will be omitted. Next, the operation will be explained. First, the two systems of baseband signals retimed by flip-flops 1 and 2 are sent to DC amplifiers 6 and 7 and low-pass filters 8 and 9.
pass through each. At this time, variations in characteristics occur due to temperature changes in these circuits, variations in component parts, etc., resulting in a phase shift of the output baseband signal. Therefore, each of these output baseband signals is converted into a full-wave rectifier circuit 1.
4 and 15 to reproduce the clock component of the baseband signal. Next, the recovered clock is passed through a bandpass filter 16.
, 17, a jitter-free clock is regenerated. The clock that has passed through these low-pass filters 16 and 17 is input to the phase comparator 18.
8 detects the phase difference between the respective clock waveforms and generates an output proportional to the phase difference. The output of the phase comparator 18 thus obtained passes through a low-pass filter 19 and becomes a DC voltage at a certain level. This DC voltage is level-converted by a level converter 20 into a control voltage that can control the continuously variable phase shifter 21 . This continuously variable phase shifter 21 is shown in FIG.
The voltage-phase characteristic is as shown in the level converter 20.
The retiming phase of one of the baseband signals is adjusted by the control voltage generated by the output baseband signal, so that the phase difference between the output baseband signals is eliminated. Another embodiment of the invention will be described with reference to FIG. The difference between this embodiment and FIG. 1 is that instead of the phase comparator 18, low-pass filter 19, and level converter 20, an exclusive OR gate circuit 22, an AND gate circuit 23, and a counter are used as the phase comparator 22. circuit 25,
This is because a reset counter 26 and a digital/analog converter 27 are used. According to this, first, the exclusive OR gate circuit 22 detects the phase difference signals of the clocks from the bandpass filters 16 and 17, respectively, and the high-speed signal input from the sample pulse input terminal 34 is detected by this phase difference signal. Sample pulse, AND gate circuit 2
Gate at 3. As a result, the AND gate circuit 23 passes the sample pulse by the pulse width of the phase difference signal. The counter circuit 25 counts the number of sample pulses that have passed through and outputs the number of pulses. Further, this counter circuit 25 is reset by a reset counter 26 at a timing N times the sample pulse. The phase difference is quantitatively determined based on the number of pulses output from the counter circuit 25. In this case, the number of pulses is a digital quantity and needs to be converted into a controllable analog quantity. Therefore, the digital/analog converter 27 converts the number of pulses into an analog quantity proportional to this, and further inputs it to the level converter 28. The level converter 28 transfers the analog signal to the continuously variable phase shifter 21.
The continuously variable phase shifter 21 adjusts the clock phase for retiming of one baseband signal based on the control voltage, and as a result, the phase difference between the output baseband signals disappears. control to operate. As described above, according to the present invention, there is provided a phase comparator that detects the phase shift of each clock waveform reproduced by a clock regeneration circuit, and a level that outputs a control voltage proportional to the phase shift. converter and a continuously variable phase shifter,
Since the above control voltage is configured to correct the clock phase for data signal retiming, it is possible to correct the phase shift of multiple output data signals without human intervention, and this phase shift correction can be performed with high efficiency. This has the effect of being able to be implemented with precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a phase control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a phase control circuit showing another embodiment of the invention.

FIG. 3 is a characteristic diagram showing voltage-phase characteristics of the continuously variable phase shifter in FIG. 1;

FIG. 4 is a block diagram showing a conventional phase control circuit.

[Explanation of symbols]

14 Clock regeneration circuit 15 Clock regeneration circuit 18 Phase comparator 20 Level converter 21 Continuously variable phase shifter

Claims (1)

[Claims] 1. A clock regeneration circuit that extracts clock components from two or more systems of data signals, a phase comparator that detects a phase shift of each clock waveform regenerated by the clock regeneration circuit, and a phase comparator that detects the phase shift of each clock waveform reproduced by the clock regeneration circuit. a phase control circuit comprising: a level converter that outputs a control voltage proportional to the phase shift; and a continuously variable phase shifter that uses the control voltage from the level converter to correct a clock phase for retiming the data signal. .