JPH11167365A - Image processor, method of processing image, and storage medium readable by computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust with precision a phase of a sampling clock used for an A/D conversion of an image signal. SOLUTION: An ideal waveform Vt of an image signal along dot clock Cs is distorted like a waveform Vp during transmission. Moreover, A sampling clock Cr1 generated from a horizontal synchronous signal contains jitters Δt, and if VP of such a waveform is processed by A/D conversion, variations of ΔV1 occur. Therefore, if the waveform VP is decreased in offset and increased in gain, a maximum variation part of Vp is processed by A/D conversion to be developed as B of the point Z of the waveform Vc1. It is possible to reduce the variations as ΔV2 by averaging the first and last large variation parts like the point Z in one line, obtaining Cr2 by phase-adjusting the above Cr1 according to the average value, and using it as a sampling clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, an image processing method, and a computer-readable storage medium suitable for use in a display control device for controlling display by a dot matrix display or the like.

[0002]

2. Description of the Related Art At present, a raster scan type so-called CRT display device is widely used as a display device of a host computer such as a personal computer and a workstation. In these host computer devices, the image data to be displayed is D / A converted based on a dot clock generated in the computer to form an analog signal,
Further, a vertical or horizontal synchronization signal is generated based on the dot clock, and the analog signal and the synchronization signal are combined and output as a so-called video signal.

[0003] These video signals have a very large number of specifications, and in particular, a personal computer may have a plurality of resolutions. For example, in a PC compatible machine of IBM Corporation, 320 * 200, 640 * 400, 720 * 4
00, 640 * 350, 640 * 480, 800 * 60
There are devices that can display each of 0, 1024 * 768, 1280 * 1024, and the like. Also, one resolution has various standards for each company, and there are very many specifications for parameters such as a dot clock and a frequency of a synchronization signal.

[0004] A CR for displaying these video signals is used.
As a T display device, there is a so-called multi-sync CRT display device, which measures a synchronizing signal of each video signal, and adjusts a driving period and a swing width of a scanning line to the synchronizing signal of the video signal. It can be displayed even if a video signal of the specification is input. This is possible because the pitch of the shadow mask that determines the minimum display pixel of the CRT display device is smaller than the pixel pitch derived from the display resolution of the video signal.

However, dot matrix display devices such as a liquid crystal panel and a plasma panel, which have recently attracted attention in terms of space saving, energy saving, ergonomics, and the like, have "one pixel is larger than a CRT shadow mask" in performance. Displaying in the same manner as a CRT display device causes a problem in image quality. In addition, since “control is suitable for digital”, the input analog video signal is synchronized with the input resolution (dot clock) by A /
A method of performing D-conversion, then performing interpolation processing in accordance with the output resolution of the dot matrix display in both the horizontal and vertical directions and displaying the result is performed.

[0006]

However, the above C
A video signal for an RT display device usually does not include a dot clock, and a sampling clock for A / D conversion uses a PLL / V signal from a horizontal synchronization signal in the display device.
It is produced using CO. However, PLL / VC
The dot clock obtained from O has a phase shift with respect to the original dot clock, and it is difficult to automatically adjust the dot clock to the best value. Finally, the user manually adjusts while looking at the display device. I often did.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and can automatically adjust the phase of a sampling clock with high accuracy. This simplifies the adjustment work by the user, is easier to use, and has higher quality. The purpose is to obtain image quality.

[0008]

An image processing apparatus according to the present invention comprises: generating means for generating a sampling clock in synchronization with a synchronizing signal included in an analog image signal; adjusting means for adjusting the phase of the sampling clock; A / D converting the analog image signal to a digital image signal based on the phase-adjusted sampling clock
D conversion means, setting means for setting the range in which the A / D conversion of the analog image signal is possible, and controlling the setting means so that the range is set to be smaller than usual, and a digital image signal obtained at this time. And control means for determining the amount of phase adjustment by the adjusting means based on a large part of the change in.

An image processing method according to the present invention comprises: a generating step of generating a sampling clock in synchronization with a synchronizing signal included in an analog image signal; an adjusting step of adjusting a phase of the sampling clock; An A / D conversion procedure for A / D converting the analog image signal into a digital image signal based on a clock, a setting procedure for setting the A / D convertible range of the analog image signal, A control procedure for controlling the setting procedure so as to be narrowly set, and determining a phase adjustment amount by the adjustment procedure based on a large change in the digital image signal obtained at this time.

[0010] A computer-readable storage medium according to the present invention comprises: a generation process for generating a sampling clock in synchronization with a synchronization signal included in an analog image signal; an adjustment process for adjusting a phase of the sampling clock;
An A / D conversion process of A / D converting the analog image signal into a digital image signal based on the phase-adjusted sampling clock;
A setting process for setting a range in which D conversion can be performed; and a setting process for controlling the setting process so that the range is set to be narrower than usual, and a phase by the adjustment process based on a large change in the digital image signal obtained at this time. A program for executing a control process for determining an adjustment amount is stored.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a display control device according to the first embodiment of the present invention. The display control device is a device for inputting and receiving an analog computer signal from a PC (personal computer), WS (workstation), or the like, and controlling it so that it can be displayed on a dot matrix display.

In FIG. 1, reference numeral 11 denotes an image processing unit for processing an analog image signal of a host computer such as a PC (personal computer), WS (workstation), etc.
It comprises a synchronization signal separation unit 111, a synchronization signal measurement unit 112, an analog adjustment unit 113, an A / D conversion unit 114, and a clock generation unit 115.

Next, the above components will be described in detail. The synchronization signal separation unit 111 receives the RGB image signal s112 from the host computer or the like and the composite sync, horizontal and vertical synchronization signals s111, and separates synchronization signals. Further, the horizontal and vertical signals cs113 and the synchronization signal polarity signal cs114 of the negative polarity are separated from the separated synchronization signals.
Is output. Then, the image signal s112 is input to the analog adjustment unit 113. In addition, the synchronization signal cs113 is input to the synchronization signal measurement unit 112, the clock generation unit 115, the interpolation processing unit 12, and the system control unit 191 described below.
The synchronization signal polarity determination signal cs114 indicates the polarity of the input synchronization signal s111, and is input to the synchronization signal measurement unit 112 and the system control unit 191.

The synchronization signal measuring section 112 receives the horizontal and vertical synchronization signals cs113 and the synchronization signal polarity discrimination signal cs114, and outputs the measurement results to the system control section 191 through the control bus cs191. Analog adjustment unit 113
Is the offset of the input RGB image signal s112,
Perform gain adjustment and waveform shaping. The A / D conversion unit 114
The analog RGB signal s113 adjusted by the analog adjustment unit 113 is sampled by the dot clock cs116 from the clock generation unit 115, and the digital signal s113 is sampled.
It is converted to 121 and output to the interpolation processing unit 12.

A clock generator 115 converts the analog image signal into a digital signal, and a clock cs for the operation of the interpolation processor 12 immediately thereafter.
116 is a PLL / VCO synchronized with the input horizontal synchronization signal.
Generated by the circuit. The clock cs 116 is the number of dot clocks in one horizontal line (VCO frequency division ratio of PLL) set in the control register of the clock generation unit 115 after the system control unit 191 determines the model and display mode of the video signal, It is controlled by various parameters such as the number of horizontal display start dots. Also, this clock cs11
In addition to 6, control of the horizontal and vertical display start position signals is also performed.

Reference numeral 12 denotes an interpolation processing unit, which is a digitized RGB image signal s obtained from the A / D conversion unit 114.
A line memory unit 121 for speed conversion using a FIFO for reducing a horizontal blanking period of 121 and delaying a dot clock of an image signal, followed by a vertical interpolation operation unit 12
3. A horizontal interpolation calculator 125 is provided, and a clock generator 122 for generating an output of the line memory 121 and an input clock of the vertical interpolation calculator 123, an output clock of the vertical interpolation calculator 123, and a horizontal The clock generator 12 for generating the input clock of the interpolation calculator 125
4. Horizontal interpolation operation unit 125 and OSD control unit 1 described later
Clock generator 12 for generating an input clock 93
6 are provided.

Reference numeral 13 denotes an OSD data adding unit,
Switching between the image data s124 after the interpolation processing and the OSD display data S195 is performed by a control signal cs196 from the D control unit 193, and data s131 is output. A digital image processing unit 14 performs various processes and controls for displaying the digital image data s124 from the interpolation processing unit 12 on a dot matrix panel of a display unit 15 described later.

Next, the configuration and processing of the digital image processing section 14 will be described in detail with reference to FIG. The digital R, G, and B image signals s124 interpolated and output by the interpolation processing unit 12 become data s131 via the OSD data addition unit 13, and are subjected to gamma correction processing and gradation adjustment processing in the contrast adjustment unit 501. The gamma-corrected and gradation-adjusted data s501 is supplied to the halftone processing unit 5
02, a halftone process such as an ED (error diffusion) method or a dither method is performed.

The motion detector 504 steals the display data before being subjected to halftone processing, detects a horizontal line that has changed by a certain value or more, and uses the result as a system controller 191.
(The system control unit 191 in FIG. 1), and the system control unit 191 only displays the motion-detected line display data among the frame display data stored in the frame buffer 503 together with the line address data. Output to the 15 display control units 505.

Referring again to FIG. 1, reference numeral 15 denotes a display unit which performs a so-called dot matrix display using liquid crystal or the like for displaying images, and a display control unit 50 as shown in FIG.
5. The image signal s 503 is composed of a dot matrix panel 506 and processed by the digital image processing unit 14. That is, the display control unit 505 shown in FIG. 3 displays the line display data at the vertical position specified by the line address data on the dot matrix panel 506.

A power supply 18 supplies power to the display control device. Reference numeral 191 denotes a system control unit which includes a so-called microcomputer and the like.
Through the control buses cs191 to cs194, each part in FIG. Reference numeral 192 denotes a key input unit, which will be described later.
The system control unit 191 has operation keys and the like for operating each unit adjustment function performed in step 3.

193 is an OSD (on screen display)
The control unit is controlled by the system control unit 191 through the control bus cs194, outputs the OSD signal s195, and switches to the image signal s124 by the data adding unit 13. 194 is a nonvolatile memory unit,
System control 191 through system control bus cs191
And a display mode table of various parameters such as a synchronization signal of the various host devices, initial data of various functions performed by an OSD operation described later, user preset data, and the like.

Reference numeral 200 denotes a ROM constituting a storage medium according to the present invention, which stores a program for executing processing shown in a flowchart of FIG. As the storage medium, a semiconductor memory, an optical disk, a magneto-optical disk, a magnetic medium, or the like can be used.

Next, a part of the image processing unit 11 directly related to the present invention will be described in detail with reference to FIG. The synchronization separation unit 111 is exactly the same as in FIG. The analog adjustment unit 113 is composed of three components, 1311, 1132, and 1133. Reference numeral 1131 denotes a video amplifier, which amplifies for buffering and level adjustment of the input video signal s112 and an output cs1 of a clamp unit 1132 described later.
13b and the output s112a of the HPF 1133 to the input s1
12 and output as s113. The video amplifier 1131 is connected to a control signal cs191c described later.
To change the amplification factor.

Reference numeral 1132 denotes a DC reproducing clamp unit which converts the output s113 of the video amplifier and an offset value signal cs191a described later into a clamp pulse cs1.
Clamp level output cs based on the timing of 14a
Output as 112b. Reference numeral 1133 denotes a high-pass filter (HPF) that amplifies only the high-frequency component of the video input signal s112 and adds the amplified signal to the video amplifier 1131 to correct the high-frequency component of the video signal.
The video waveform is being shaped.

The clock generator 115 includes 1151, 11
52. Reference numeral 1151 denotes a PLL / VCO circuit which outputs an integer multiple clock phase-synchronized with the horizontal synchronizing signal (HD) cs113 as cs116p.
The multiplied value is used as a division ratio of the PLL / VCO as the control bus c.
It is controlled through s191c. 1152 is a delay unit (De
lay line), the clock cs116p is delayed and output as cs116. This delay value can be digitally variably controlled by the control microcomputer 1911 through the control bus cs191c, and a delay of one cycle or more of the sampling clock can be made. This output is output from the A / D converter 11
4 sampling clocks.

The A / D converter 114 is exactly the same as in FIG. The line memory unit 121 is the same as that shown in FIG. 1 and has a capacity capable of storing the number of data of one horizontal synchronization period output from the A / D converter 114 or more.

Next, the control unit 191 includes 1911 and 191
Consists of two. Reference numeral 1911 denotes a control microcomputer, whose control bus includes a synchronization signal measuring unit 112.
Control line cs 119 d for controlling the control of the line data, transferring the measurement data, controlling the line memory unit 121, and collecting the video data and the like stored in the line memory unit 121, the video amplifier 1131, the PLL / VCO circuit 1152, and the delay unit 11.
52, a control bus cs1 for transferring various control data to
There are two systems 91c.

Next, the outline of waveforms and timings related to video signals of each section of the apparatus and a host computer connected to the apparatus will be described with reference to FIG. The waveform Cs in FIG.
This is a dot clock of the video signal of the host computer, and has a relatively high quality with little jitter or the like. The lower waveform Vt shows an ideal waveform immediately after the D / A conversion of the analog image signal output from the D / A converter in synchronization with the rise of the dot clock Cs. When this waveform Vt is lost in a high frequency band by a noise filter, a cable, or the like, and is input to the apparatus as s112 in FIG. Although not shown on the illustrated waveform Vp, some noise and jitter are added thereto.

On the other hand, horizontal and vertical synchronizing signals are generated and transmitted in the form of dividing the dot clock Cs.
This also adds some noise and jitter. Therefore, the sampling clock for the A / D converter 114 reproduced by the PLL / VCO circuit 1151 based on the horizontal synchronization signal also includes the jitter Δt as shown by the waveform Cr1, and the phase is the same as the above-described image. It is shifted from the signal waveform Vp.

Therefore, if the A / D conversion is performed with the sampling clock as it is, the side of the blunt waveform Vp is sampled, and even if the same image input is performed, Δv
1 and the display quality is degraded. However, even if the sampling clock has some jitter like Cr2 by adjusting the phase of the waveform Cr1, if the phases are matched, the image is improved by the variation of Δv2.

Next, the flow of the automatic phase adjustment directly related to the present invention will be described with reference to FIG. FIG.
First, in step st401, the microcomputer of the system control unit 191 controls the synchronization signal measurement unit 112 so as to control the frequency of the horizontal and vertical synchronization signals,
The number and the like of the horizontal synchronization signal in the vertical synchronization signal are measured, and the polarities of both synchronization signals are determined.

Next, in st402, a table search is performed based on the measurement result in st401. And st4
At 03, it is determined whether or not the display mode can be determined. If the mode can be determined, the process proceeds to st404, where the vertical and horizontal resolutions of the input video signal, the image start position, and the PL
The frequency division value of the L / VCO circuit 1151 and other control parameters are determined by referring to the table, and the process proceeds to st450.

If the mode cannot be completely determined, st
Proceed to 405 to set the resolution and an appropriate frequency division value. In this case, too, there are not so many types of resolutions, and thus can be determined from the above measurement results. The start positions of the vertical and horizontal images of the video signal and the frequency division values of the PLL / VCO circuit 1151 corresponding to this have a very large number of types, and cannot be completely determined in consideration of variations and the like. Therefore, the mode closest to the above measurement result is set as the temporary mode, and the mode including the other control parameters is temporarily determined with reference to the table.
Next, the control microcomputer 1911 controls the control bus cs191d,
Through the cs 191c, the tentatively determined value is converted to a PLL / VCO
The data is transferred to each unit including the circuit 1151, and the A / D conversion operation is started.

Then, the process proceeds to st 406, and the digital video data that has been A / D converted for each horizontal synchronization signal is read from the line memory unit 121 via the control bus 191 d into the microcomputer. At this time, the number of valid data from the point where non-black data first appears to the last point where non-black data appears within one horizontal synchronization period is remembered.
In the case of a normal display, it is highly possible that some lines on the screen have the first and last dots not at the black level. Counting, the maximum number of valid data, and this is the horizontal resolution.

Next, proceeding to st407, if the maximum number of valid data is equal to the determined resolution, it is determined that the tentatively determined values are correct, and other control parameters are also determined from these, and the process proceeds to st405 as these are officially determined values. On the other hand, when the maximum effective data number is different from the determined resolution, first, if the maximum effective data number is larger than the tentatively determined horizontal resolution, the sampling clock frequency of A / D conversion is larger than the original video signal dot clock. In other words, if it is smaller, the sampling clock frequency of A / D conversion is smaller than the original dot clock of the video signal.

In the former case, the PL tentatively determined in st405
The frequency division value of the L / VCO is reduced, and in the latter case, st40
Increase the frequency division value of the PLL / VCO temporarily determined in step 5
Returning to t406, the data of the A / D conversion is read again.
In st407, this is continued until the maximum number of valid data becomes equal to the determined resolution, and if they are equal, the process proceeds to st450 as the officially determined value.

At st450, the microcomputer reads the A / D-converted digital video data again according to the formal determination value. First, an appropriate dot is selected, and the delay unit 11
52, the delay amount is changed, and the delay amount is provisionally determined so that the level of the dot is maximized. Next, black-white-black and 1
Detect where the dots change as greatly as possible.

Then, in st451, two dots, that is, the dot where the change first appears in the line and the white dot where the change finally appears in the line are set as phase adjustment dots. At this time, if the white-black-white level changes, a point where one of R, B, and G changes from 0 to near the maximum value is found.

Then, the process proceeds to st452, where the clamp unit 11
32, the input video signal is shifted in the negative direction, and the gain of the video amplifier 1131 is increased. Now, assuming that the point Z in FIG. 4 is the above-mentioned dot for phase adjustment, the input image waveform is Vp, and the waveform when this is shifted in the negative direction and the gain is increased as described above is Vc1. By doing so, as is clear from FIG. 4, the level change of the image signal when the phase of the sampling clock is changed by Δd at the point Z increases from A to B. Here, the delay unit 1
The set value of 152 is returned to 0.

Then, the program proceeds to st453, in which the levels of the two determined dots for phase adjustment are measured, and these are temporarily stored in a memory section in the microcomputer. Next, proceed to st454,
The control microcomputer 1911 changes the delay amount by one step. Then, in st455, it is determined whether the delay amount is within one cycle of the sampling clock, and if it is within one cycle, the process returns to st453, and the level of the dot for phase adjustment is measured again and read into the microcomputer.

When the delay amount becomes equal to or more than one cycle of the sampling clock, the process proceeds to st456, where the delay amount of the two measured dots for phase adjustment at the point where the level change is small is obtained at each of the two adjustment points, and the average of the two is obtained. Is adopted as the optimal phase. Then proceed to st457,
The control voltage to the clamp unit 1132 and the gain of the video amplifier 1131 changed in st452 are returned to the original values.

Next, the image processing unit 1 according to the second embodiment
1 is shown in FIG. In FIG. 6, the synchronization separation unit 111,
The synchronization signal measuring section 112 is the same as in the first embodiment shown in FIG. In addition, the video amplifier 1131, the clamp unit 1
132 is a microcomputer for controlling the gain and the clamp level.
It is the same as FIG. 2 except that control is not started from 1.

The delay section 1152 receives the horizontal synchronizing signal (HD) cs 113 output from the synchronization separating section 111,
By controlling the delay amount through the control microcomputer 1911 and the D / A converter 1912, the PLL / VCO circuit 115
1 controls the phase of the sampling clock (dot clock) cs116 for the A / D converter, which is output from 1.

Reference numerals 1141, 1142, and 1143 denote detailed structures of the A / D converter 114, which are so-called parallel A / D converters.
It is a D converter. Reference numeral 1142 denotes a comparator group for comparison. In the case of an N-bit output, 2 n comparators are required.
1 and cs191a1, cs191a
2, a voltage between two reference voltages is input, and A / D conversion is performed within this voltage. A latch encoding unit 1143 latches the result compared by the 1142 comparator with the sampling clock cs116, encodes the result, and outputs the result as s121.

In the second embodiment, the gain and the offset of the analog amplifier are not adjusted to adjust the gain and the offset as in the first embodiment. The gain and offset are adjusted by changing the reference voltage of the reference voltage of the / D converter 114.

Further, in the first embodiment, the phase of the sampling clock itself of the A / D converter is adjusted by the delay unit 1152, but in the second embodiment, FIG.
, The HD (horizontal synchronization signal) cs113 input to the phase comparison input terminal of the PLL / VCO circuit 1151
Is also adjusted by the delay unit 1152.

In FIG. 1, a ferroelectric liquid crystal panel (FLCD) is used for the display unit. However, other dot matrix type panels (TFT liquid crystal panel, A plasma display panel or the like may be used. Further, the present invention can be applied to a device that more accurately samples an analog video signal as digital data. Further, the above-described automatic phase adjustment is performed by changing the phase of a certain dot and sampling, and setting a point having a small change among a plurality of levels as an optimum phase. It is also possible to consider a method in which a point that becomes a peak of a mountain is determined as an optimum point, instead of a method in which a point having a small level is obtained or a point in which a level change is small.

[0049]

As described above, according to the present invention, the video signal at the time of phase adjustment is appropriately level-shifted and amplified, and the level change in the vicinity of the detection section is largely adjusted, thereby automatically adjusting the accuracy. Phase adjustment can be performed, thereby simplifying a user's adjustment work.
It is easier to use and can perform high-quality image display.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire display control device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an image processing unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a digital image processing unit.

FIG. 4 is a timing chart of waveforms showing an operation.

FIG. 5 is a flowchart illustrating a flow of an operation.

FIG. 6 is a block diagram of an image processing unit according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 image processing section 111 sync separation section 1131 video amplifier 1132 clamp section 114 A / D conversion section 121 line memory section 1151 PLL / VCO circuit 1152 delay section 1141 resistor group 1142 comparator 1143 latch & encoder section 1911 control microcomputer

Claims (12)

[Claims] A generating means for generating a sampling clock in synchronization with a synchronization signal included in an analog image signal; an adjusting means for adjusting a phase of the sampling clock; and an analog circuit based on the phase adjusted sampling clock. A / D conversion means for A / D converting an image signal into a digital image signal, setting means for setting the A / D convertible range of the analog image signal, and setting the range to be narrower than usual An image processing apparatus comprising: a control unit that controls the setting unit and determines a phase adjustment amount by the adjustment unit based on a large change in the digital image signal obtained at this time. 2. The method according to claim 1, wherein the setting means sets the offset and gain of the analog image signal by the control means.
2. The image processing apparatus according to claim 1, wherein the gain is increased while the offset level is reduced. 3. The image processing apparatus according to claim 1, wherein said setting means sets a reference voltage applied to said A / D conversion means by said control means. 4. An image processing apparatus according to claim 1, wherein said control means uses a plurality of said portions having large changes, and determines said phase adjustment amount based on an average value thereof. 5. A generating procedure for generating a sampling clock in synchronization with a synchronizing signal included in an analog image signal, an adjusting procedure for adjusting a phase of the sampling clock, and the analog based on the phase adjusted sampling clock. An A / D conversion procedure for A / D converting an image signal into a digital image signal, a setting procedure for setting the A / D convertible range of the analog image signal, and a setting so that the range is narrower than usual. A control procedure of controlling the setting procedure, and determining a phase adjustment amount by the adjustment procedure based on a large change in the digital image signal obtained at this time. 6. In the setting procedure, the offset and gain of the analog image signal are set by the control procedure. When the range is set narrower than usual,
6. The image processing method according to claim 5, wherein the gain is increased while lowering the offset level. 7. The image processing method according to claim 5, wherein in the setting procedure, a reference voltage applied to the A / D conversion procedure is set by the control procedure. 8. The image processing method according to claim 5, wherein in the control procedure, a plurality of the portions having large changes are used, and the phase adjustment amount is determined based on an average value thereof. 9. A generation process for generating a sampling clock in synchronization with a synchronization signal included in an analog image signal, an adjustment process for adjusting a phase of the sampling clock, and an analog process based on the phase-adjusted sampling clock. A / D conversion processing for A / D converting an image signal into a digital image signal, setting processing for setting the A / D convertible range of the analog image signal, and setting the range to be narrower than usual A computer-readable storage medium storing a program for controlling the setting procedure and executing a control process of determining a phase adjustment amount by the adjustment process based on a large part of a change in a digital image signal obtained at this time. . 10. In the setting process, the offset and gain of the analog image signal are set by the control process. When the range is set smaller than usual, the offset level is reduced and the gain is increased. 10. The computer-readable storage medium according to claim 9, wherein: 11. The computer-readable storage medium according to claim 9, wherein in the setting processing, a reference voltage to be applied to the A / D conversion processing is set by the control processing. 12. The computer-readable storage according to claim 9, wherein the control process uses a plurality of the large-change portions and determines the phase adjustment amount based on an average value thereof. Medium.