JPH09283932A - Multilayer printed wiring board manufacturing method - Google Patents

Multilayer printed wiring board manufacturing method

Info

Publication number
JPH09283932A
JPH09283932A JP11191796A JP11191796A JPH09283932A JP H09283932 A JPH09283932 A JP H09283932A JP 11191796 A JP11191796 A JP 11191796A JP 11191796 A JP11191796 A JP 11191796A JP H09283932 A JPH09283932 A JP H09283932A
Authority
JP
Japan
Prior art keywords
forming
interlayer insulating
hole
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11191796A
Other languages
Japanese (ja)
Inventor
Shinji Adachi
真治 安達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP11191796A priority Critical patent/JPH09283932A/en
Publication of JPH09283932A publication Critical patent/JPH09283932A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board manufacturing method capable of roughening the inner walls of open holes for forming vias and surface of an interlayer insulation layer to provide an interlyer insulation layer superior indurability. SOLUTION: Hole forming posts 1 having a releasing agent at least ion their surface are disposed at via-forming positions on a first conductor circuit layer 51. An interlayer insulation layer 6 is formed on the surface of the first layer 51 with an exposed tops 17 of the posts 1. After removing the posts 1, an anchor-forming powder 4 is laid on the upper face of this layer 6, pressed and heated to bury the powder in the surface of the insulation layer 6 and inner walls of the open holes. The powder is removed to roughen the surface of the insulation layer 6 and inner walls of the holes and these surfaces are covered with a metal layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【技術分野】本発明は,導体回路層と層間絶縁層とを交
互に積層することにより,多層プリント配線板を製造す
る,多層プリント配線板の製造方法に関する。
TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, which comprises manufacturing a multilayer printed wiring board by alternately laminating conductor circuit layers and interlayer insulating layers.

【0002】[0002]

【従来技術】従来,図15に示すごとく,導体回路層9
0と層間絶縁層93とを交互にビルトアップしてなる多
層プリント配線板9がある。上記多層プリント配線板を
製造する方法としては,従来,例えば,特開平5─10
2669号公報に示す方法がある。
2. Description of the Related Art Conventionally, as shown in FIG.
There is a multilayer printed wiring board 9 in which 0s and interlayer insulating layers 93 are alternately built up. As a method of manufacturing the above-mentioned multilayer printed wiring board, there is a conventional method, for example, Japanese Patent Laid-Open No.
There is a method disclosed in Japanese Patent No. 2669.

【0003】即ち,まず,図13に示すごとく,絶縁基
板91の表面に導体回路層90を形成し,その表面にバ
イアホール形成用のホール成形用柱92を形成する。次
いで,絶縁基板91の表面を層間絶縁層93により被覆
する。次いで,ホール成形用柱92の頂部を被覆する層
間絶縁層93をバフ研磨することにより,除去する。次
いで,導体回路層90から除去して,図14に示すごと
く,導体回路層90に達する開口穴95を形成する。
That is, first, as shown in FIG. 13, a conductor circuit layer 90 is formed on the surface of an insulating substrate 91, and hole forming columns 92 for forming via holes are formed on the surface. Next, the surface of the insulating substrate 91 is covered with the interlayer insulating layer 93. Next, the interlayer insulating layer 93 covering the tops of the hole forming columns 92 is removed by buffing. Then, the conductor circuit layer 90 is removed to form an opening hole 95 reaching the conductor circuit layer 90 as shown in FIG.

【0004】次いで,酸化剤等によって層間絶縁層93
の表面粗化処理を行う。これにより,層間絶縁層93に
含まれるフィラーだけが溶解して,層間絶縁層93の表
面が粗化される。次いで,図15に示すごとく,絶縁基
板91を貫通する貫通穴98を穿設する。その後,層間
絶縁層93の表面には導体回路層96を,また開口穴9
5,貫通穴98の内壁面には金属層97を形成する。こ
れにより,多層プリント配線板9を得る。
Next, an interlayer insulating layer 93 is formed with an oxidizing agent or the like.
Surface roughening treatment is performed. As a result, only the filler contained in the interlayer insulating layer 93 is dissolved and the surface of the interlayer insulating layer 93 is roughened. Next, as shown in FIG. 15, a through hole 98 penetrating the insulating substrate 91 is formed. After that, the conductor circuit layer 96 is formed on the surface of the interlayer insulating layer 93, and the opening hole 9 is formed.
5. A metal layer 97 is formed on the inner wall surface of the through hole 98. Thereby, the multilayer printed wiring board 9 is obtained.

【0005】この製造方法においては,ホール成形用柱
92は,感光性樹脂層の露光,現像により形成されるた
め,穴あけ精度が良い。また,層間絶縁層の表面粗化処
理により,層間絶縁層93の表面及び開口穴95の内壁
面に微細な窪み930が形成される。この窪み930に
よって,導体回路層96及び金属層97のアンカー効果
が高められ,両者の密着強度が向上する。
In this manufacturing method, since the hole forming pillar 92 is formed by exposing and developing the photosensitive resin layer, the hole forming accuracy is good. Further, by the surface roughening treatment of the interlayer insulating layer, fine recesses 930 are formed on the surface of the interlayer insulating layer 93 and the inner wall surface of the opening 95. The recess 930 enhances the anchor effect of the conductor circuit layer 96 and the metal layer 97, and improves the adhesion strength between them.

【0006】[0006]

【解決しようとする課題】しかしながら,上記従来の多
層プリント配線板の製造方法においては,バイアホール
形成用のホール成形用柱を除去するに当たって,図13
に示すごとく,その頂部927を被覆する外側導体93
を研磨除去しなければならない。そして,その研磨厚み
は数十μm程度と薄いものの,平行に研磨しないと,絶
縁基板91上の導体回路層90が露出したり,断線する
おそれがある。そのため,精度の高い平行研磨装置を必
要とし,コスト高となる。また,層間絶縁層93の上面
を数十μm程度に平行に研磨することは困難である。
However, in the conventional method for manufacturing a multilayer printed wiring board described above, when removing the hole forming pillars for forming the via holes, as shown in FIG.
The outer conductor 93 covering the top portion 927 as shown in FIG.
Must be removed by polishing. Although the polishing thickness is as thin as several tens of μm, the conductor circuit layer 90 on the insulating substrate 91 may be exposed or the wire may be broken unless it is polished in parallel. Therefore, a highly accurate parallel polishing device is required, resulting in high cost. Further, it is difficult to polish the upper surface of the interlayer insulating layer 93 in parallel to about several tens of μm.

【0007】また,層間絶縁層93の表面粗化処理によ
って,その表面部分に含まれるフィラーは除去される
が,層間絶縁層93の内部に含まれるフィラーは除去さ
れない。そのため,多量のフィラーが層間絶縁層93の
中に残存したまま,多層プリント配線板が使用に供され
る。すると,使用中の加熱冷却等,過酷な環境に晒され
た場合には,層間絶縁層93とフィラーとの熱膨張係数
の相違により,層間絶縁層93が劣化する場合がある。
By the surface roughening treatment of the interlayer insulating layer 93, the filler contained in the surface portion is removed, but the filler contained in the interlayer insulating layer 93 is not removed. Therefore, the multilayer printed wiring board is used while a large amount of the filler remains in the interlayer insulating layer 93. Then, when exposed to a harsh environment such as heating and cooling during use, the interlayer insulating layer 93 may deteriorate due to the difference in thermal expansion coefficient between the interlayer insulating layer 93 and the filler.

【0008】本発明はかかる従来の問題点に鑑み,バイ
アホール形成用の開口穴の内壁及び層間絶縁層の表面を
容易かつ低コストで粗化することができ,層間絶縁層の
耐久性に優れた,多層プリント配線板の製造方法を提供
しようとするものである。
In view of the above conventional problems, the present invention can easily and inexpensively roughen the inner wall of the opening hole for forming a via hole and the surface of the interlayer insulating layer, and has excellent durability of the interlayer insulating layer. Another object is to provide a method for manufacturing a multilayer printed wiring board.

【0009】[0009]

【課題の解決手段】請求項1に記載の発明は,絶縁基板
上に導体回路層と層間絶縁層とを交互にビルトアップし
て,バイアホールを有する多層プリント配線板を製造す
るに当たり,上記絶縁基板に第1導体回路層を形成し,
次いで,該第1導体回路層におけるバイアホール形成位
置に,少なくとも表面に離型剤を含有するホール成形用
柱を配置し,次いで,上記ホール成形用柱の頂部を露出
させた状態で,上記ホール成形用柱の側壁を取り巻くよ
うにして,上記第1導体回路層の表面に上記層間絶縁層
を形成し,次いで,上記ホール成形用柱を取り去って第
1導体回路層に達する開口穴を形成し,次いで,上記層
間絶縁層の上面及び上記開口穴内にアンカー形成用粉末
を配置し,次いで,押圧,加熱して,上記アンカー形成
用粉末を層間絶縁層の表面及び上記開口穴の内壁面に埋
設し,次いで,溶剤を用いて上記アンカー形成用粉末を
溶解除去することにより,層間絶縁層の表面を粗化表面
となすと共に上記開口穴の内壁面を粗化内壁面となし,
その後,層間絶縁層の粗化表面及び開口穴の粗化内壁面
を金属層により被覆して,第2導体回路層及びバイアホ
ールを形成することを特徴とする多層プリント配線板の
製造方法である。
According to a first aspect of the present invention, when a conductive circuit layer and an interlayer insulating layer are alternately built up on an insulating substrate to manufacture a multilayer printed wiring board having a via hole, the insulation is provided. Forming a first conductor circuit layer on the substrate,
Next, a hole forming column containing a release agent on at least the surface is arranged at a via hole forming position in the first conductor circuit layer, and then the hole forming column is exposed with the top of the hole forming column exposed. The interlayer insulating layer is formed on the surface of the first conductor circuit layer so as to surround the side wall of the forming pillar, and then the hole forming pillar is removed to form an opening hole reaching the first conductor circuit layer. Then, the anchor forming powder is placed on the upper surface of the interlayer insulating layer and in the opening hole, and then pressed and heated to embed the anchor forming powder on the surface of the interlayer insulating layer and the inner wall surface of the opening hole. Then, the anchor forming powder is dissolved and removed using a solvent to make the surface of the interlayer insulating layer a roughened surface and the inner wall surface of the opening hole to be a roughened inner wall surface.
Thereafter, the roughened surface of the interlayer insulating layer and the roughened inner wall surface of the opening hole are covered with a metal layer to form a second conductor circuit layer and a via hole, which is a method for manufacturing a multilayer printed wiring board. .

【0010】本発明において最も注目すべきことは,第
1導体回路層の表面に,ホール成形用柱の側壁を取り巻
くようにして層間絶縁層を形成すること,及びホール成
形用柱を取り去った後にその抜け跡である開口穴の中及
び層間絶縁層の表面にアンカー形成用粉末を配置し,押
圧,加熱することによって,開口穴の内壁面及び層間絶
縁層の表面を粗化することである。
What is most noticeable in the present invention is that the interlayer insulating layer is formed on the surface of the first conductor circuit layer so as to surround the side wall of the hole forming pillar, and after the hole forming pillar is removed. This is to roughen the inner wall surface of the opening hole and the surface of the interlayer insulating layer by arranging the anchor forming powder in the opening hole which is the escape trace and on the surface of the interlayer insulating layer and pressing and heating.

【0011】次に,本発明の作用効果について説明す
る。本発明の多層プリント配線板の製造方法において
は,第1導体回路層の表面に,ホール成形用柱の側壁を
取り巻くようにして層間絶縁層を形成している。そのた
め,ホール成形用柱の頂部は層間絶縁層により被覆され
ず,露出している。それ故,層間絶縁層を研磨すること
なく,ホール成形用柱を取り去ることができ,多層プリ
ント配線板の製造が容易となる。
Next, the function and effect of the present invention will be described. In the method for manufacturing a multilayer printed wiring board according to the present invention, the interlayer insulating layer is formed on the surface of the first conductor circuit layer so as to surround the side wall of the hole-forming pillar. Therefore, the top of the hole forming pillar is not covered with the interlayer insulating layer and is exposed. Therefore, the hole forming pillars can be removed without polishing the interlayer insulating layer, which facilitates the production of the multilayer printed wiring board.

【0012】また,ホール成形用柱を取り去った跡であ
る開口穴の内壁,及び層間絶縁層の表面には,アンカー
形成用粉末を埋設し,その後アンカー形成用粉末を溶解
除去している。そのため,開口穴には粗化表面が,層間
絶縁層には粗化表面が形成されて,これらの表面にはア
ンカー形成用粉末が残らない。また,層間絶縁層の内部
にも異物が存在しない。従って,層間絶縁層が,異物と
の熱膨張差によって劣化することはなく,耐久性に優れ
ている。
Further, anchor forming powder is embedded in the inner wall of the opening hole and the surface of the interlayer insulating layer, which are the traces of the hole forming pillar removed, and then the anchor forming powder is dissolved and removed. Therefore, a roughened surface is formed in the opening hole and a roughened surface is formed in the interlayer insulating layer, and no anchor forming powder remains on these surfaces. Also, no foreign matter exists inside the interlayer insulating layer. Therefore, the interlayer insulating layer does not deteriorate due to the difference in thermal expansion from the foreign matter, and has excellent durability.

【0013】また,層間絶縁層の表面及び開口穴の内壁
に対して,アンカー形成用粉末を配置し,これを押圧,
加熱している。そのため,層間絶縁層の表面及び開口穴
の内壁に,均一な厚みにアンカー形成用粉末が埋設され
る。そのため,アンカー形成用粉末の除去により,層間
絶縁層の表面には粗化表面が,また開口穴の内壁面には
粗化内壁面が,均一に形成される。
Further, anchor forming powder is arranged on the surface of the interlayer insulating layer and the inner wall of the opening hole, and the powder is pressed,
It is heating. Therefore, the anchor forming powder is embedded in the surface of the interlayer insulating layer and the inner wall of the opening hole with a uniform thickness. Therefore, by removing the anchor forming powder, a roughened surface is uniformly formed on the surface of the interlayer insulating layer, and a roughened inner wall surface is uniformly formed on the inner wall surface of the opening hole.

【0014】従って,層間絶縁層の粗化表面と金属層と
の間,及び開口穴の粗化内壁面と金属層との間に,アン
カー効果によって,均一な密着力が得られ,金属層が剥
離するおそれはない。また,従来のごとく,上記平行研
磨装置は必要としないため,低コストで多層プリント配
線板を製造することができる。
Therefore, a uniform adhesion can be obtained by the anchor effect between the roughened surface of the interlayer insulating layer and the metal layer, and between the roughened inner wall surface of the opening hole and the metal layer, and the metal layer is formed. There is no risk of peeling. Further, unlike the conventional case, the parallel polishing apparatus is not required, so that the multilayer printed wiring board can be manufactured at low cost.

【0015】また,上記ホール成形用柱は,感光性樹脂
で作製されていることが好ましい。これにより,感光性
樹脂を露光,現像することにより,ホール成形用柱の形
成位置精度が良い。そのため,0.1mm程度の径の小
さいバイアホールであっても正確に形成することができ
る。
Further, it is preferable that the hole forming column is made of a photosensitive resin. As a result, by exposing and developing the photosensitive resin, the forming accuracy of the hole forming columns is good. Therefore, even a via hole having a small diameter of about 0.1 mm can be accurately formed.

【0016】また,ホール成形用柱には,少なくともそ
の表面に離型剤を含有している。離型剤は,ホール成形
用柱の中に混合されていることが好ましい。これによ
り,ホール成形用柱全体が,層間絶縁層に対して優れた
離型性を発揮し,ホール成形用柱を層間絶縁層から取去
し易くなり,開口穴を損傷させない。また,ホール成形
用柱の成形と同時にその表面に離型剤を含有させること
ができ,ホール成形用柱の作製が容易である。また,離
型剤は,上記ホール成形用柱の表面に塗布されていても
よい。これにより,離型剤の使用量の減少化を図ること
ができる。
Further, the hole forming column contains a release agent at least on its surface. The release agent is preferably mixed in the hole forming column. As a result, the hole forming column as a whole exhibits excellent releasability from the interlayer insulating layer, the hole forming column is easily removed from the interlayer insulating layer, and the opening hole is not damaged. In addition, a mold release agent can be contained on the surface of the hole forming column at the same time when the hole forming column is formed, which facilitates the production of the hole forming column. Further, the release agent may be applied to the surface of the hole forming column. As a result, the amount of release agent used can be reduced.

【0017】そして,離型剤は,フッ素系離型剤である
ことが好ましい。これにより,ホール成形用柱が開口穴
の壁面から,一層剥がれやすくなり,ホール成形用柱の
除去が容易となる。上記フッ素系離型剤としては,例え
ば,アニオン系,カチオン系,ノニオン系,又は両性の
フッ素界面活性剤,低分子量四フッ化エチレン樹脂があ
る。これらの離型剤は,ホール成形用柱の表面の滑り性
を一層良くする。
The release agent is preferably a fluorine-based release agent. As a result, the hole forming pillar is more easily peeled from the wall surface of the opening hole, and the hole forming pillar is easily removed. Examples of the fluorine-based releasing agent include anionic, cationic, nonionic, or amphoteric fluorosurfactants and low molecular weight tetrafluoroethylene resins. These release agents further improve the slipperiness of the surface of the hole forming column.

【0018】上記アニオン系フッ素系界面活性剤として
は,フルオロアルコキシポリフルオロアルキル硫酸エス
テル,フルオロカーボンスルホン酸塩,フルオロカーボ
ンカルボン酸塩等がある。上記カチオン系フッ素系界面
活性剤としては,N−フルオロアルキルスルホンアミド
アルキルアミン第4級アンモニウム塩,N−フルオロア
ルキルスルホンアミドアルキルアミン塩等がある。
Examples of the above-mentioned anionic fluorine-based surfactant include fluoroalkoxy polyfluoroalkyl sulfate, fluorocarbon sulfonate, fluorocarbon carboxylate and the like. Examples of the above-mentioned cationic fluorosurfactants include N-fluoroalkylsulfonamidoalkylamine quaternary ammonium salts and N-fluoroalkylsulfonamidoalkylamine salts.

【0019】上記ノニオン系界面活性剤としては,フル
オロカーボンスルホアミド,フルオロカーボンアミノス
ルホアミド等がある。上記両性フッ素系界面活性剤とし
ては,ベタイン型フルオロカーボンスルホアミド結合を
有するアルキルアミン,ベタイン型フルオロカーボン酸
アミド結合を有するアルキルアミン等がある。
Examples of the nonionic surfactants include fluorocarbon sulfamide and fluorocarbon aminosulfoamide. Examples of the amphoteric fluorine-based surfactant include alkylamines having a betaine-type fluorocarbon sulfamide bond and alkylamines having a betaine-type fluorocarbon acid amide bond.

【0020】また,上記溶剤は酸化剤であり,上記アン
カー形成用粉末は該酸化剤によって溶解可能な粉末であ
ることが好ましい。これにより,アンカー形成用粉末の
溶解除去が容易となり,層間絶縁層の粗化表面にアンカ
ー形成用粉末が残るおそれはない。かかるアンカー形成
用粉末としては,例えば,炭酸カルシウム微粉末,エポ
キシ系樹脂微粉末,銅微粉末シリカ超微粉末等を用いる
ことができる。上記酸化剤としては,クロム酸,塩酸等
がある。
It is preferable that the solvent is an oxidizing agent and the anchor forming powder is a powder that can be dissolved by the oxidizing agent. This facilitates dissolution and removal of the anchor-forming powder, and there is no risk of the anchor-forming powder remaining on the roughened surface of the interlayer insulating layer. As the anchor forming powder, for example, calcium carbonate fine powder, epoxy resin fine powder, copper fine powder, silica ultrafine powder, or the like can be used. Examples of the oxidizing agent include chromic acid and hydrochloric acid.

【0021】また,請求項2に記載のように,上記ホー
ル成形用柱を配置する際に,少なくとも表面に離型剤を
含有し,電子部品搭載用凹部を形成するためのキャビテ
ィ形成部材を,上記電子部品搭載用凹部の形成位置に配
置し,該キャビティ形成部材は上記金属層形成後に取り
去ることが好ましい。これにより,多層プリント配線板
に電子部品搭載用凹部を容易に形成することができる。
また,キャビティ形成部材の表面は離型剤を含有してい
るため,キャビティ形成部材の電子部品搭載用凹部から
の除去が容易である。また,電子部品搭載用凹部の仕上
がりもよい。
Further, as described in claim 2, when arranging the hole forming columns, a cavity forming member containing a release agent on at least a surface and forming a recess for mounting electronic parts, It is preferable that the cavity forming member is disposed at a position where the electronic component mounting recess is formed, and the cavity forming member is removed after the metal layer is formed. This makes it possible to easily form the recess for mounting an electronic component on the multilayer printed wiring board.
Further, since the surface of the cavity forming member contains the release agent, it is easy to remove the cavity forming member from the recess for mounting electronic parts. In addition, the recess for mounting electronic parts has a good finish.

【0022】[0022]

【発明の実施の形態】本発明の実施形態例にかかる多層
プリント配線板の製造方法について,図1〜図12を用
いて説明する。本例により製造される多層プリント配線
板8は,図1に示すごとく,絶縁基板3上に第1導体回
路層51と層間絶縁層6と第2導体回路層52とを交互
にビルトアップしたものである。層間絶縁層6には,第
1導体回路層51に達するバイアホール53が設けられ
ている。また,層間絶縁層6には,電子部品を搭載する
ための電子部品搭載用凹部65が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer printed wiring board according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the multilayer printed wiring board 8 manufactured according to the present example is one in which first conductor circuit layers 51, interlayer insulating layers 6 and second conductor circuit layers 52 are alternately built up on an insulating substrate 3. Is. The interlayer insulating layer 6 is provided with a via hole 53 reaching the first conductor circuit layer 51. Further, the inter-layer insulating layer 6 is provided with an electronic component mounting recess 65 for mounting an electronic component.

【0023】次に,上記多層プリント配線板の製造方法
について,図2〜図12を用いて説明する。まず,図2
に示すごとく,絶縁基板3の表面に第1導体回路層51
を形成する。絶縁基板3としては,例えば,ガラスエポ
キシ等の樹脂基板を用いる。第1導体回路層51は,銅
箔等を用いて,サブトラクティブ法等により形成する。
次いで,図3に示すごとく,第1導体回路層51におけ
るバイアホール形成位置に,ホール成形用柱1を配置す
る。
Next, a method for manufacturing the above-mentioned multilayer printed wiring board will be described with reference to FIGS. First, FIG.
As shown in FIG. 1, the first conductor circuit layer 51 is formed on the surface of the insulating substrate 3.
To form As the insulating substrate 3, for example, a resin substrate such as glass epoxy is used. The first conductor circuit layer 51 is formed by a subtractive method using copper foil or the like.
Next, as shown in FIG. 3, the hole forming pillar 1 is arranged at the via hole forming position in the first conductor circuit layer 51.

【0024】ホール成形用柱1は,図11に示すごと
く,平滑面10を有する,直径0.2mmの円柱であ
る。ホール成形用柱1は,アクリル系樹脂等の感光性樹
脂と離型剤との混合物を,絶縁基板3の上に供給し,こ
れを露光,現像することによって形成する。離型剤とし
ては,低分子量四フッ化エチレン樹脂を用いる。
As shown in FIG. 11, the hole forming column 1 is a cylinder having a smooth surface 10 and a diameter of 0.2 mm. The hole forming pillar 1 is formed by supplying a mixture of a photosensitive resin such as an acrylic resin and a release agent onto the insulating substrate 3 and exposing and developing the mixture. A low molecular weight tetrafluoroethylene resin is used as a release agent.

【0025】また,図3に示すごとく,絶縁基板3上に
おける電子部品搭載用凹部の形成位置に,電子部品搭載
用凹部を形成するためのキャビティ形成部材2を配置す
る。キャビティ形成部材2は,図12に示すごとく,離
型剤230を有する耐熱再剥離フィルムNT75(商品
名,パナック株式会社製,厚み75μm程度)を用い
て,電子部品搭載用凹部の形状に加工したものである。
Further, as shown in FIG. 3, the cavity forming member 2 for forming the electronic component mounting recess is arranged at the position where the electronic component mounting recess is formed on the insulating substrate 3. As shown in FIG. 12, the cavity forming member 2 was processed into a shape of a recess for mounting electronic parts by using a heat-resistant re-peeling film NT75 (trade name, manufactured by Panac Co., about 75 μm) having a release agent 230. It is a thing.

【0026】次いで,図4に示すごとく,ホール成形用
柱1の側壁を取り巻くようにして,第1導体回路層51
の表面に層間絶縁層6を形成する。ホール成形用柱1の
頂部17は,層間絶縁層6の表面より突出させる。
Then, as shown in FIG. 4, the first conductor circuit layer 51 is formed so as to surround the side wall of the hole forming pillar 1.
The interlayer insulating layer 6 is formed on the surface of the. The top portion 17 of the hole forming column 1 is projected from the surface of the interlayer insulating layer 6.

【0027】上記層間絶縁層6を形成するに当たって
は,フェノールノボラック型エポキシ樹脂100重量
部,イミダゾール5重量部からなる原材料を混練し,ブ
チルセロソルブアセテートを10重量%添加する。そし
て,この混合物をホモディスバーにより攪拌した後,3
本ローラで混練する。この樹脂混練物を絶縁基板3の表
面全体に塗布・硬化する。この際,ホール成形用柱1の
頂部17を露出させるようにする。
In forming the interlayer insulating layer 6, a raw material consisting of 100 parts by weight of a phenol novolac type epoxy resin and 5 parts by weight of imidazole is kneaded, and 10% by weight of butyl cellosolve acetate is added. After stirring this mixture with a homodisbar, 3
Knead with this roller. This resin kneaded material is applied and cured on the entire surface of the insulating substrate 3. At this time, the tops 17 of the hole forming columns 1 are exposed.

【0028】次いで,図5に示すごとく,ホール成形用
柱1を取り去って,層間絶縁層6に第1導体回路層51
に達する開口穴60を形成する。ホール成形用柱1を取
り去るに当たっては,超音波振動をかけながら,上記絶
縁基板3を,感光性樹脂溶解液(塩化メチル溶液)に3
分間浸漬する。これにより,ホール成形用柱が除去され
て,内径0.2mmの開口穴60が形成される。
Next, as shown in FIG. 5, the hole forming pillar 1 is removed, and the first conductor circuit layer 51 is formed on the interlayer insulating layer 6.
An opening hole 60 reaching to In removing the hole forming pillar 1, while applying ultrasonic vibration, the insulating substrate 3 is immersed in a photosensitive resin solution (methyl chloride solution)
Soak for a minute. As a result, the hole forming pillar is removed, and the opening hole 60 having an inner diameter of 0.2 mm is formed.

【0029】次いで,図6に示すごとく,層間絶縁層6
の上面及び開口穴の中に,アンカー形成用粉末4を載置
し,その上方から押圧板45により押圧し,加熱する。
これにより,層間絶縁層6を軟化させて,アンカー形成
用粉末4を層間絶縁層6の表面に埋設する。
Next, as shown in FIG. 6, the interlayer insulating layer 6
The anchor forming powder 4 is placed on the upper surface and the opening hole of the, and pressed by the pressing plate 45 from above and heated.
As a result, the interlayer insulating layer 6 is softened and the anchor forming powder 4 is embedded in the surface of the interlayer insulating layer 6.

【0030】アンカー形成用粉末4は,溶剤によって溶
解可能な炭酸カルシウム微粉末である。次いで,図7に
示すごとく,押圧板45を取り去った後,層間絶縁層6
に埋設しなかったアンカー形成用粉末4を除去する。
The anchor forming powder 4 is a fine powder of calcium carbonate which can be dissolved by a solvent. Then, as shown in FIG. 7, after removing the pressing plate 45, the interlayer insulating layer 6 is removed.
The anchor-forming powder 4 not buried in is removed.

【0031】次いで,溶剤である塩酸水溶液に,上記絶
縁基板3を浸漬する。これにより,アンカー形成用粉末
4を溶解除去して,図8に示すごとく,層間絶縁層6に
粗化表面62を形成するとともに,開口穴60の粗化内
壁面61を形成する。なお,かかる粗化処理が施された
絶縁基板には,ドリル等により,必要に応じて貫通スル
ーホール形成用の貫通穴を穿設する。
Next, the insulating substrate 3 is immersed in an aqueous solution of hydrochloric acid which is a solvent. As a result, the anchor forming powder 4 is dissolved and removed to form a roughened surface 62 on the interlayer insulating layer 6 and a roughened inner wall surface 61 of the opening hole 60, as shown in FIG. If necessary, a through hole for forming a through through hole is formed in the roughened insulating substrate by a drill or the like.

【0032】次いで,図9に示すごとく,スクリーン印
刷法により,感光性樹脂を塗布し,層間絶縁層6の表面
における第2導体回路層を形成しない部分を露光し,硬
化させることにより,無電解めっき用のレジスト膜7を
形成する。次いで,上記絶縁基板3をパラジウム─スズ
コロイド触媒溶液で処理して,層間絶縁層6におけるレ
ジスト非形成部分に触媒核を形成する。
Then, as shown in FIG. 9, a photosensitive resin is applied by a screen printing method, and a portion of the surface of the interlayer insulating layer 6 where the second conductor circuit layer is not formed is exposed and cured, thereby electroless A resist film 7 for plating is formed. Next, the insulating substrate 3 is treated with a palladium-tin colloidal catalyst solution to form catalyst nuclei on the non-resist forming portion of the interlayer insulating layer 6.

【0033】次いで,図10に示すごとく,層間絶縁層
6の粗化表面62及び開口穴60の粗化内壁面61に,
無電解銅めっき法により,金属層5を形成する。これに
より,層間絶縁層6の表面には第2導体回路層52を,
開口穴60にはバイアホール53を形成する。なお,金
属層5は,めっき法の他に,スパッタリング,蒸着,ペ
ースト塗布によっても形成できる。その後,キャビティ
形成部材2及び不要であれば感光性レジスト膜7を除去
する。以上により,図1に示す多層プリント配線板8を
得る。
Then, as shown in FIG. 10, on the roughened surface 62 of the interlayer insulating layer 6 and the roughened inner wall surface 61 of the opening hole 60,
The metal layer 5 is formed by the electroless copper plating method. As a result, the second conductor circuit layer 52 is formed on the surface of the interlayer insulating layer 6,
A via hole 53 is formed in the opening hole 60. The metal layer 5 can be formed by sputtering, vapor deposition, or paste application, in addition to the plating method. Then, the cavity forming member 2 and the photosensitive resist film 7 are removed if unnecessary. As described above, the multilayer printed wiring board 8 shown in FIG. 1 is obtained.

【0034】次に,本例の作用効果について説明する。
本例においては,図4に示すごとく,第1導体回路層5
1の表面に,ホール成形用柱1の側壁を取り巻くように
して層間絶縁層6を形成している。そのため,ホール成
形用柱1の頂部17は層間絶縁層6により被覆されず,
露出する。それ故,層間絶縁層6を研磨することなく,
ホール成形用柱1を取り去ることができる。
Next, the function and effect of this example will be described.
In this example, as shown in FIG.
An interlayer insulating layer 6 is formed on the surface of the hole forming column 1 so as to surround the side wall of the hole forming column 1. Therefore, the top portion 17 of the hole forming pillar 1 is not covered with the interlayer insulating layer 6,
Exposed. Therefore, without polishing the interlayer insulating layer 6,
The hole forming pillar 1 can be removed.

【0035】また,図7に示すごとく,ホール成形用柱
を取り去った跡である開口穴60の内壁,及び層間絶縁
層6の表面には,アンカー形成用粉末4を埋設し,その
後アンカー形成用粉末4を溶解除去している。そのた
め,図8に示すごとく,開口穴60には粗化表面61
が,層間絶縁層6には粗化表面62が形成されて,これ
らの表面にはアンカー形成用粉末が残らない。
As shown in FIG. 7, the anchor forming powder 4 is embedded in the inner wall of the opening hole 60, which is a trace of the hole forming pillar, and the surface of the interlayer insulating layer 6, and then the anchor forming powder 4 is formed. The powder 4 is dissolved and removed. Therefore, as shown in FIG.
However, a roughened surface 62 is formed on the interlayer insulating layer 6, and no anchor forming powder remains on these surfaces.

【0036】また,層間絶縁層6の内部にも,アンカー
形成用粉末等の異物が存在しない。従って,層間絶縁層
6が,異物との熱膨張差によって劣化することはなく,
耐久性に優れている。しかも,極めて低価格でありなが
ら,その含有により耐湿性に問題を残す炭酸カルシウム
微粉末をアンカー形成用粉末4として使うことができ
る。
Also, no foreign matter such as anchor forming powder exists inside the interlayer insulating layer 6. Therefore, the interlayer insulating layer 6 does not deteriorate due to the difference in thermal expansion with the foreign matter,
Has excellent durability. Moreover, it is possible to use the calcium carbonate fine powder, which has a problem of moisture resistance due to the inclusion thereof, at a very low price, as the anchor forming powder 4.

【0037】また,図6に示すごとく,層間絶縁層6の
表面及び開口穴60の内壁に対して,アンカー形成用粉
末4を配置し,これを押圧,加熱している。そのため,
層間絶縁層6の表面及び開口穴60の内壁に,均一な厚
みにアンカー形成用粉末4が埋設される。そのため,図
7に示すごとく,アンカー形成用粉末の除去により,層
間絶縁層6の表面には粗化表面62が,また開口穴60
の内壁には粗化内壁面61が,均一な厚みに形成され
る。
Further, as shown in FIG. 6, the anchor forming powder 4 is arranged on the surface of the interlayer insulating layer 6 and the inner wall of the opening hole 60, and this is pressed and heated. for that reason,
The anchor forming powder 4 is embedded in the surface of the interlayer insulating layer 6 and the inner wall of the opening hole 60 with a uniform thickness. Therefore, as shown in FIG. 7, by removing the anchor forming powder, a roughened surface 62 and an opening hole 60 are formed on the surface of the interlayer insulating layer 6.
A roughened inner wall surface 61 is formed on the inner wall of the plate with a uniform thickness.

【0038】従って,図10に示すごとく,層間絶縁層
6の粗化表面62と金属層5との間,及び開口穴60の
粗化内壁面61と金属層5との間に,アンカー効果によ
って,均一な密着力が得られ,金属層の剥離を防止でき
る。また,従来のような上記平行研磨装置は必要としな
いため,低コストで多層プリント配線板8を製造するこ
とができる。
Therefore, as shown in FIG. 10, by the anchor effect, between the roughened surface 62 of the interlayer insulating layer 6 and the metal layer 5, and between the roughened inner wall surface 61 of the opening 60 and the metal layer 5. , Uniform adhesion can be obtained and peeling of the metal layer can be prevented. Further, since the parallel polishing apparatus as in the prior art is not required, the multilayer printed wiring board 8 can be manufactured at low cost.

【0039】[0039]

【発明の効果】本発明によれば,バイアホール形成用の
開口穴の内壁及び層間絶縁層の表面を容易かつ低コスト
で粗化することができ,層間絶縁層の耐久性に優れた,
多層プリント配線板の製造方法を提供することができ
る。
According to the present invention, the inner wall of the opening hole for forming the via hole and the surface of the interlayer insulating layer can be roughened easily and at low cost, and the durability of the interlayer insulating layer is excellent.
A method for manufacturing a multilayer printed wiring board can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施形態例における,多層プリント配線板の断
面図。
FIG. 1 is a cross-sectional view of a multilayer printed wiring board according to an exemplary embodiment.

【図2】実施形態例における,第1導体回路層を形成し
た絶縁基板の説明図。
FIG. 2 is an explanatory diagram of an insulating substrate on which a first conductor circuit layer is formed in the embodiment example.

【図3】実施形態例における,ホール成形用柱及びキャ
ビティ形成部材を配置した絶縁基板の説明図。
FIG. 3 is an explanatory view of an insulating substrate on which a hole forming column and a cavity forming member are arranged in the embodiment example.

【図4】実施形態例における,表面に層間絶縁層を形成
した絶縁基板の説明図。
FIG. 4 is an explanatory diagram of an insulating substrate having an interlayer insulating layer formed on the surface according to the embodiment.

【図5】実施形態例における,ホール成形用柱を取り去
った絶縁基板の説明図。
FIG. 5 is an explanatory view of an insulating substrate from which a hole forming pillar is removed in the embodiment.

【図6】実施形態例における,アンカー形成用粉末を押
圧,加熱する方法を示す説明図。
FIG. 6 is an explanatory view showing a method of pressing and heating anchor forming powder in the embodiment.

【図7】実施形態例における,アンカー形成用粉末を埋
設した層間絶縁層を示す説明図。
FIG. 7 is an explanatory view showing an interlayer insulating layer in which anchor forming powder is embedded, in an embodiment example.

【図8】実施形態例における,粗化表面を形成した層間
絶縁層と,粗化内壁面を形成した開口穴とを示す説明
図。
FIG. 8 is an explanatory view showing an interlayer insulating layer having a roughened surface and an opening hole having a roughened inner wall surface in the embodiment.

【図9】実施形態例における,表面にレジスト膜を形成
した層間絶縁層の説明図。
FIG. 9 is an explanatory diagram of an interlayer insulating layer having a resist film formed on the surface in the embodiment.

【図10】実施形態例における,金属層を被覆した層間
絶縁層の説明図。
FIG. 10 is an explanatory diagram of an interlayer insulating layer coated with a metal layer in the embodiment example.

【図11】実施形態例における,ホール成形用柱の斜視
図。
FIG. 11 is a perspective view of a hole forming column according to the embodiment.

【図12】実施形態例における,離型剤を混合したキャ
ビティ形成部材を示す説明図。
FIG. 12 is an explanatory view showing a cavity forming member in which a release agent is mixed in the embodiment example.

【図13】従来例における,多層プリント配線板の製造
方法の問題点を示す説明図。
FIG. 13 is an explanatory view showing a problem in a method for manufacturing a multilayer printed wiring board in a conventional example.

【図14】従来例における,粗化処理を施した絶縁基板
の説明図。
FIG. 14 is an explanatory diagram of a roughened insulating substrate in a conventional example.

【図15】従来例における,多層プリント配線板の断面
図。
FIG. 15 is a cross-sectional view of a multilayer printed wiring board in a conventional example.

【符号の説明】[Explanation of symbols]

1,,,ホール成形用柱, 10...平滑面, 230...離型剤, 2...キャビティ形成部材, 3...絶縁基板, 51...第1導体回路層, 52...第2導体回路層, 53...バイアホール, 6...層間絶縁層, 60...開口穴, 61...粗化内壁面, 62...粗化表面, 7...レジスト膜, 8...多層プリント配線板, 1,…, Hole forming columns, 10. . . Smooth surface, 230. . . Release agent, 2. . . Cavity forming member, 3. . . Insulating substrate, 51. . . First conductor circuit layer, 52. . . Second conductor circuit layer, 53. . . Via hole, 6. . . Interlayer insulating layer, 60. . . Opening hole, 61. . . Roughened inner wall surface, 62. . . Roughened surface, 7. . . Resist film, 8. . . Multilayer printed wiring board,

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板上に導体回路層と層間絶縁層と
を交互にビルトアップして,バイアホールを有する多層
プリント配線板を製造するに当たり,上記絶縁基板に第
1導体回路層を形成し,次いで,該第1導体回路層にお
けるバイアホール形成位置に,少なくとも表面に離型剤
を含有するホール成形用柱を配置し,次いで,上記ホー
ル成形用柱の頂部を露出させた状態で,上記ホール成形
用柱の側壁を取り巻くようにして,上記第1導体回路層
の表面に上記層間絶縁層を形成し,次いで,上記ホール
成形用柱を取り去って第1導体回路層に達する開口穴を
形成し,次いで,上記層間絶縁層の上面及び上記開口穴
内にアンカー形成用粉末を配置し,次いで,押圧,加熱
して,上記アンカー形成用粉末を層間絶縁層の表面及び
上記開口穴の内壁面に埋設し,次いで,溶剤を用いて上
記アンカー形成用粉末を溶解除去することにより,層間
絶縁層の表面を粗化表面となすと共に上記開口穴の内壁
面を粗化内壁面となし,その後,層間絶縁層の粗化表面
及び開口穴の粗化内壁面を金属層により被覆して,第2
導体回路層及びバイアホールを形成することを特徴とす
る多層プリント配線板の製造方法。
1. When manufacturing a multilayer printed wiring board having via holes by alternately building up conductor circuit layers and interlayer insulating layers on an insulating substrate, forming a first conductor circuit layer on the insulating substrate. Then, a hole forming column containing a release agent on at least the surface thereof is arranged at a via hole forming position in the first conductor circuit layer, and then, with the top of the hole forming column exposed, The interlayer insulating layer is formed on the surface of the first conductor circuit layer so as to surround the side wall of the hole forming pillar, and then the hole forming pillar is removed to form an opening hole reaching the first conductor circuit layer. Then, the anchor forming powder is placed on the upper surface of the interlayer insulating layer and in the opening hole, and then pressed and heated to apply the anchor forming powder to the surface of the interlayer insulating layer and the inner wall surface of the opening hole. By embedding in the substrate, and then dissolving and removing the anchor-forming powder with a solvent to form the surface of the interlayer insulating layer as a roughened surface and the inner wall surface of the opening hole as a roughened inner wall surface, and thereafter, The roughened surface of the interlayer insulating layer and the roughened inner wall surface of the opening hole are covered with a metal layer,
A method of manufacturing a multilayer printed wiring board, which comprises forming a conductor circuit layer and a via hole.
【請求項2】 請求項1において,上記ホール成形用柱
を配置する際に,少なくとも表面に離型剤を含有し,電
子部品搭載用凹部を形成するためのキャビティ形成部材
を,上記電子部品搭載用凹部の形成位置に配置し,該キ
ャビティ形成部材は上記金属層形成後に取り去ることを
特徴とする多層プリント配線板の製造方法。
2. The electronic component mounting method according to claim 1, further comprising a cavity forming member containing a mold release agent on at least a surface of the hole forming column when forming the hole forming column and forming a concave portion for electronic component mounting. A method for manufacturing a multilayer printed wiring board, characterized in that the cavity forming member is disposed at a formation position of a concave portion, and the cavity forming member is removed after the metal layer is formed.
JP11191796A 1996-04-08 1996-04-08 Multilayer printed wiring board manufacturing method Pending JPH09283932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11191796A JPH09283932A (en) 1996-04-08 1996-04-08 Multilayer printed wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11191796A JPH09283932A (en) 1996-04-08 1996-04-08 Multilayer printed wiring board manufacturing method

Publications (1)

Publication Number Publication Date
JPH09283932A true JPH09283932A (en) 1997-10-31

Family

ID=14573360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11191796A Pending JPH09283932A (en) 1996-04-08 1996-04-08 Multilayer printed wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JPH09283932A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008112996A (en) * 2006-10-27 2008-05-15 Samsung Electro-Mechanics Co Ltd Method of manufacturing printed-circuit substrate
WO2010140214A1 (en) * 2009-06-02 2010-12-09 ソニーケミカル&インフォメーションデバイス株式会社 Method for manufacturing multilayer printed wiring board
WO2011037260A1 (en) * 2009-09-28 2011-03-31 京セラ株式会社 Structure and method for producing same
JPWO2009069683A1 (en) * 2007-11-30 2011-04-14 ソニーケミカル&インフォメーションデバイス株式会社 Manufacturing method of multilayer printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008112996A (en) * 2006-10-27 2008-05-15 Samsung Electro-Mechanics Co Ltd Method of manufacturing printed-circuit substrate
JPWO2009069683A1 (en) * 2007-11-30 2011-04-14 ソニーケミカル&インフォメーションデバイス株式会社 Manufacturing method of multilayer printed wiring board
WO2010140214A1 (en) * 2009-06-02 2010-12-09 ソニーケミカル&インフォメーションデバイス株式会社 Method for manufacturing multilayer printed wiring board
WO2011037260A1 (en) * 2009-09-28 2011-03-31 京セラ株式会社 Structure and method for producing same
KR101423534B1 (en) * 2009-09-28 2014-07-25 쿄세라 코포레이션 Structure and method for producing same

Similar Documents

Publication Publication Date Title
US6426011B1 (en) Method of making a printed circuit board
KR20080014623A (en) Wiring board and method for manufacturing the same
JPH09283932A (en) Multilayer printed wiring board manufacturing method
JP4666754B2 (en) Dry film for multilayer printed wiring board and method for producing multilayer printed wiring board using the same
JPH09275277A (en) Manufacture of multi-layer printed wiring board
JPH1012995A (en) Manufacture of circuit component provided with three-dimensional structure
JPH05259639A (en) Manufacture of printed wiring board
JP2000236145A (en) Wiring board and its manufacturing method
JP3890631B2 (en) Method for manufacturing printed wiring board
JP2000294930A (en) Manufacture of multilayer printed circuit board and semiconductor device using the multilayer printed circuit board
JP2002185139A (en) Printed wiring board and its manufacturing method
JP2857270B2 (en) Manufacturing method of multilayer printed wiring board
JPH10335779A (en) Formation of pattern
JPH1065317A (en) Manufacturing method of printed wiring board
JPH0499088A (en) Manufacture of multilayered printed wiring board
JP2002185134A (en) Printed circuit board and its manufacturing method
JP2005142454A (en) Method for manufacturing multilayer printed wiring board
JP2000323807A (en) Printed wiring board and manufacture thereof
JPH10341081A (en) Multilayered printed wiring board manufacture
JP2001177253A (en) Manufacturing method for multilayer printed board
JP2000294904A (en) Manufacture of fine pattern and printed wiring board using the same
JPH02119298A (en) Manufacture of multilayer printed wiring board for mounting semiconductor element
JP2000183525A (en) Manufacture of wiring board
JPS6064495A (en) Method of producing printed circuit board
JPS60167493A (en) Method of producing circuit board