JPH09236825A - Liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device having high opening ratio. SOLUTION: In a region in which a black matrix 204 and a pixel electrode 205 are superposed, holding capacity is formed via an insulating layer consisting of a nitrided film. Especially, as a region 206 makes the most of the whole region covering a thin film transistor of the black matrix 204, necessary area thereof is saved. Since an organic resin material or an inorganic material having small relative dielectric constant is used as a second interlayer insulating film, holding capacity can be formed without consideration of parasitic capacity.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of a liquid crystal display device controlled by a semiconductor device using a crystalline silicon film. In particular, it relates to a configuration of a pixel region of an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Recently, a technique for producing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix liquid crystal display devices has increased.

An active matrix type liquid crystal display device is
A thin film transistor is arranged in each of the millions of pixels arranged in a matrix, and the electric charge flowing in and out of each pixel electrode is controlled by the switching function of the thin film transistor.

A liquid crystal is sandwiched between each pixel electrode and a counter electrode to form a kind of capacitor. Therefore,
By controlling the flow of charges into and out of the capacitor by the thin film transistor, the electro-optical characteristics of the liquid crystal are changed, and light transmitted through the liquid crystal panel can be controlled to display an image.

Further, since the holding voltage of the capacitor having such a configuration gradually decreases due to leakage or the like, there is a problem that the electro-optical characteristics of the liquid crystal change and the contrast of image display deteriorates.

Therefore, it is common to install another capacitor called a storage capacitor in series with the capacitor made of liquid crystal, and supply the charge lost due to leakage or the like to the capacitor made of liquid crystal.

Here, FIG. 1 shows a configuration diagram of a pixel region in a conventional active matrix type liquid crystal display device. As shown in FIG. 1A, a gate line 101 and a capacitor line 102 formed in parallel with the gate line 101 intersect a data line 103 in a lattice pattern. A pixel electrode 104 is arranged in a region surrounded by the above (hereinafter, this region is referred to as a pixel region). The capacitor line 102 and the pixel electrode 104 are three-dimensionally overlapped via the first and second interlayer insulating films to form a storage capacitor.

Reference numeral 105 denotes a semiconductor layer constituting an active layer of the thin film transistor, 106 denotes a contact portion with a data line, and 107 denotes a contact portion with a pixel electrode.

In FIG. 1A, a pixel area surrounded by a gate line 101 and a data line 103 which are formed to intersect in a grid pattern is an area for displaying an image, and it is necessary to secure an area as large as possible. Is required.

However, in the structure shown in FIG. 1A, it is necessary to provide the capacitance line 102 in the region, and therefore, there is a problem that the pixel region is narrowed accordingly, that is, the aperture ratio is deteriorated.

Further, as shown in FIG.
4 is arranged so as not to overlap with the gate line 101 and the data line 103. This is because the parasitic capacitance formed when they are overlapped has an adverse effect such as lowering the operation speed of the liquid crystal display device.

However, on the other hand, the edge portion of the pixel electrode 104 is disturbed when a voltage is applied, causing a display defect such as blurred image. Required.

Further, the semiconductor layer 105 constituting the active layer of the thin film transistor needs to be shielded so that light from the outside is not irradiated. This is because when the semiconductor layer is irradiated with light, the conductivity of the semiconductor layer changes due to a photoexcitation phenomenon.

In general, means for providing a black matrix (BM) on the substrate on which the thin film transistors are disposed or the opposite substrate for the purpose of shielding light is used. Here, FIG. 1B shows a region that can be seen when a black matrix is arranged.

As shown in FIG. 1B, a gate line 101,
The capacitance line 102, the data line 103, and the semiconductor layer 105 are all covered with a black matrix, so that they are out of view. Therefore, the area indicated by 108 is the actual image display area.

As described above, the capacitance line 102 narrows the pixel area more than necessary, which is a factor of deteriorating the aperture ratio.

[0017]

The invention disclosed in the present specification provides a technique for solving the above-mentioned conventional problems. That is, it is an object to provide a technique for forming a pixel region having a high aperture ratio.

[0018]

The structure of the invention disclosed in the present specification has a plurality of gate lines and data lines arranged in a matrix on the same substrate and arranged at each intersection of the gate lines and the data lines. And a thin film transistor connected to the pixel electrode, wherein the first interlayer insulating film covering the gate line and the data line are formed. A second interlayer insulating film made of an organic resin material or an inorganic material,
A black matrix formed above the thin film transistor via the second interlayer insulating film, a third interlayer insulating film formed of a nitride film covering the black matrix, and the third interlayer insulating film. At least a pixel electrode formed on the film, and a storage capacitor is formed between the black matrix and the pixel electrode via the third interlayer insulating film.

According to another aspect of the invention, a plurality of gate lines and data lines arranged in a matrix on the same substrate, a pixel electrode disposed at each intersection of the gate lines and the data lines, and the pixel electrode are arranged. A liquid crystal display device comprising at least a thin film transistor to be connected,
Via a first interlayer insulating film covering the gate line and a second interlayer insulating film formed of an organic resin material or an inorganic material covering the data lines, and the second interlayer insulating film. A black matrix formed above the thin film transistor, a third interlayer insulating film formed of a nitride film covering the black matrix, and a pixel electrode formed on the third interlayer insulating film. Have at least
A storage capacitor is formed between the black matrix and the pixel electrode via the third interlayer insulating film, and the pixel electrode does not directly contact the second interlayer insulating film.

According to another aspect of the invention, a plurality of gate lines and data lines arranged in a matrix on the same substrate, a pixel electrode arranged at each intersection of the gate line and the data line, and the pixel electrode are arranged. In manufacturing a liquid crystal display device including at least a thin film transistor to be connected, a second interlayer insulating film that covers the gate line and a second interlayer insulating film that covers the data line and is made of an organic resin material or an inorganic material. Forming an interlayer insulating film, forming a black matrix made of a metal film on the second interlayer insulating film, and forming a third interlayer insulating film made of a nitride film so as to cover the black matrix. A step of forming a contact hole in the second and third interlayer insulating films, and a step of forming a pixel electrode made of a transparent conductive film on the third interlayer insulating film. At least it has, characterized in that allowed to form a storage capacitor through the third interlayer insulating film between the pixel electrode and the black matrix.

The gist of the present invention is to provide the black matrix with a function as an electrode for forming a storage capacitor in addition to the original function as a light-shielding film.

FIG. 2 is a top view of a pixel region of the liquid crystal display device constructed according to the present invention. In FIG. 2, 201 is a gate line extending from the gate electrode, and 202 is a data line for transmitting an image signal.

The gate lines 201 and the data lines 202 are arranged in a matrix on the same substrate, and a thin film transistor is arranged at each intersection. 203 is a semiconductor layer constituting an active layer of the thin film transistor.

Then, the gate line 201 and the data line 202
A black matrix 204 is arranged above the semiconductor layer 203 so as to shield them. The data line 202 and the black matrix 204 are between 0.1 and 5.0
It is insulated by a second interlayer insulating film having a thickness of μm. This second interlayer insulating film is made of an organic resin material or an inorganic material.

Further, a pixel electrode 205 is provided on the black matrix 204 via a third interlayer insulating film. This third interlayer insulating film is composed of a nitride film, and as the nitride film, AlN, AlN _X O _Y , Si ₃ N
₄ , one or more kinds selected from the insulating films represented by SiO _X N _Y can be used. The thickness of the third interlayer insulating film may be 0.1 to 0.3 μm.

With such a structure, the pixel electrode 205
The capacitance is formed in a region 206 where the black matrix 204 and the black matrix 204 overlap three-dimensionally via the third interlayer insulating film. The present invention utilizes this capacity as a storage capacity.

Here, as a feature of the present invention, it is important that the third interlayer insulating film is a nitride film. There are three major advantages of using the nitride film.

The first is the passivation effect of the nitride film. For example, since the silicon nitride film represented by Si ₃ N ₄ is dense, it is widely used as a protective film (passivation film) for protecting the device from external contamination and the like.

Second, the relative dielectric constant of the nitride film is large. For example, the silicon nitride film made of Si ₃ N ₄ has a relative permittivity of about 7, and has a relative permittivity about twice that of the organic resin material or the inorganic material used as the second interlayer insulating film.

Therefore, since the storage capacitance formed between the black matrix 204 and the pixel electrode 205 has a large relative dielectric constant of the third interlayer insulating film, a necessary and sufficient capacity can be obtained.

Thirdly, it can be utilized also as a mask when forming an opening (contact hole) in the second interlayer insulating film. This is because a large etching selectivity can be obtained between the organic resin material or the inorganic material, which is the second interlayer insulating film, and the nitride film.

For example, if a resist mask is used as a mask when forming an opening in polyimide, which is an organic resin material, the selection ratio cannot be taken because it is the same organic material.
There is a problem that an opening having a depth larger than the film thickness of the resist mask cannot be formed.

In this respect, since the nitride film has a sufficient selection ratio, if only the nitride film is first etched with a hydrofluoric acid-based gas and the remaining nitride film is used as a mask, a desired depth with respect to polyimide can be obtained. It becomes possible to form an opening.

In addition, for example, when a nitride film represented by AlN or AlN _X O _Y is used, these nitride films have an advantage of excellent thermal conductivity. Therefore, it is possible to radiate heat without trapping heat in the device, which is effective in the case where heat is generated due to high-speed operation like a driver TFT.

On the other hand, the advantage of using the organic resin material or the inorganic material as the second interlayer insulating film is that the relative dielectric constant is small and the film thickness can be increased. For example, the parasitic capacitance formed between the black matrix 204 and the gate line 201 and the data line 202 can be suppressed to a level not causing a problem because the relative dielectric constant of the second interlayer insulating film is sufficiently small.

The details of the present invention having the above structure will be described with reference to the following embodiments.

[0037]

【Example】

[Embodiment 1] In this embodiment, an example in which a pixel region having the structure shown in FIG. 2 is formed using the present invention will be described. Specifically, a detailed description will be given of a technique for forming a storage capacitor using a black matrix and a pixel electrode.

FIG. 3 is a manufacturing process diagram of the pixel TFT which constitutes the pixel region shown in FIG. First, an amorphous silicon film (not shown) having a thickness of 200 to 500 Å is formed on a glass substrate 301 having an insulating film having a thickness of 2000 Å as a base film on its surface. The insulating film may be formed using silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), a silicon nitride film (SiN), or the like by a plasma CVD method, a low-pressure thermal CVD method, a sputtering method, or the like.

Next, this amorphous silicon film (not shown) is crystallized by heating, laser annealing, or a combination of both. Further, it is effective to add a metal element that promotes crystallization during crystallization.

After the crystallization is completed, the obtained crystalline silicon film (not shown) is patterned to form the island-shaped semiconductor layer 302. After the island-shaped semiconductor layer 302 is formed, a silicon oxide film 303 functioning as a gate insulating film is formed to a thickness of 1200 ° later. Of course, a silicon oxynitride film or a silicon nitride film may be used.

Next, a conductive film 304 is formed to a thickness of 2000 to 2500Å. In this embodiment, an aluminum film containing 0.2 wt% of scandium is used. Scandium has the effect of suppressing protrusions such as hillocks and whiskers generated on the aluminum surface during heat treatment and the like. This aluminum film 304 will later function as a gate electrode.

Thus, the state shown in FIG. 3A is obtained.
After the state of FIG. 3A is obtained, anodization is performed in the electrolytic solution using the aluminum film 304 as an anode. As the electrolytic solution, a 3% tartaric acid ethylene glycol solution neutralized with aqueous ammonia to adjust the pH to 6.92 is used. Further, platinum is used as a cathode, and the formation current is 5 mA, and the ultimate voltage is 10 V.

The thin and dense anodic oxide film (not shown) thus formed has the effect of increasing the adhesion to the photoresist when the aluminum film 304 is patterned.
Further, the film thickness can be controlled by controlling the voltage application time.

Next, the aluminum film 304 is patterned to form a gate electrode (not shown). However, the part that actually functions as the gate electrode is a part of the inner part that finally remains.

Next, a second anodic oxidation is performed to form a porous anodic oxide film 305 (see FIG. 3B). The electrolytic solution is a 3% oxalic acid aqueous solution, and the treatment is carried out at a formation current of 2 to 3 mA and a reaching voltage of 8 V using platinum as a cathode.

At this time, anodization proceeds in a direction parallel to the substrate. Further, the length of the porous anodic oxide film 305 can be controlled by controlling the voltage application time.

Further, after removing the photoresist (not shown) used for patterning the aluminum film with a dedicated stripping solution, anodic oxidation is performed for the third time to obtain the state of FIG. 3 (B).

For this anodic oxidation, the electrolytic solution used is one in which a 3% ethylene glycol solution of tartaric acid is neutralized with aqueous ammonia to adjust the pH to 6.92. And with platinum as the cathode, formation current 5-6mA, ultimate voltage 40
Process as ~ 100V.

The anodic oxide film 306 formed at this time is extremely dense and strong. For this reason, damage and heat generated in a later process such as a doping process can prevent the gate electrode 3 from being damaged.
Has the effect of protecting 07. The film thickness is 500 to 15
00Å.

Next, impurities are implanted into the island-shaped semiconductor layer 302 by the ion doping method. For example, if an N-channel TFT is manufactured, P + ions may be implanted as impurities, and if a P-channel TFT is manufactured, B + ions may be implanted as impurities.

First, in the state of FIG. 3B, the first ion doping is performed. In this embodiment, the implantation of P + ions is performed at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ atoms / cm 2.
Perform in ² .

Then, the gate electrode 307 and the porous anodic oxide film 305 serve as a mask, and the regions 308 and 309 to be source / drain later are formed in a self-aligned manner.
(FIG. 3 (C))

Next, as shown in FIG. 3C, the porous anodic oxide film 305 is removed and a second doping is performed. The second P + ion implantation was performed at an acceleration voltage of 80 k.
V, at a dose of 1 × 10 ¹⁴ atoms / cm ² .

Then, the gate electrode 307 serves as a mask, and the low-concentration impurity regions 310 and 311 having a lower impurity concentration than the source region 308 and the drain region 309 are formed in a self-aligned manner.

At the same time, since no impurities are implanted right under the gate electrode 307, a region 312 functioning as a channel of the TFT is formed in a self-aligned manner.

The low-concentration impurity region 311 formed in this manner is called an LDD region, and the channel region 31 is called.
2 and the drain region 309 have the effect of suppressing the formation of a high electric field.

Then, the KrF excimer laser is set to 200-
By irradiating with an energy density of 300 mJ / cm ² ,
Activation of the ion-implanted P + ions is performed. In addition,
Activation may be performed by thermal annealing at 300 to 450 ° C. for 2 hours, or laser annealing and thermal annealing may be used in combination.

Next, the first interlayer insulating film 313 is formed by the plasma CVD method. As the interlayer insulating film 313,
A silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like can be used. The film thickness is set to 0.5 to 1.0 μm.

After forming the first interlayer insulating film 313, a contact hole is formed in the source region 308, and an aluminum film (not shown) is formed to a thickness of 3000 Å. Next, a source electrode 314 is formed by patterning an aluminum film (not shown). (FIG. 3 (D))

Next, a second interlayer insulating film 315 is formed to cover the source electrode 314 and have a thickness of 0.1 to 5.0 μm. In this embodiment, the thickness is 1.5 μm. The second interlayer insulating film 315 can be made of an organic resin material or an inorganic material. In this embodiment, transparent polyimide is used as the organic resin material. The relative permittivity of this polyimide is 2.8
It is a small value of ~ 3.4.

In addition, such an organic resin material is easy to form a film and can easily increase the film thickness.
It is possible to reduce irregularities due to the device shape and realize an excellent flat surface.

Next, a titanium film is formed as a black matrix 316 on the second interlayer insulating film 315 to a thickness of 1000 Å. Of course, a metal film such as a chromium film or an aluminum film may be used. (Fig. 4 (A))

When the state shown in FIG. 4A is obtained, the third interlayer insulating film 317 is covered with 0.1 to 3 to cover the black matrix 316.
Film is formed to a thickness of 0.3 μm. This third interlayer insulating film 31
7 is AlN, AlN _X O _Y , Si ₃ N ₄ , SiO _X N _Y
It is possible to use one kind or plural kinds selected from the insulating films shown by.

In this embodiment, a silicon nitride film made of Si ₃ N ₄ is formed to a thickness of 0.2 μm. Since this silicon nitride film uses SiH ₄ , NH ₃ , and H ₂ as film forming gases,
Hydrogen is contained in the film to relax the film stress.

Then, a contact hole for connecting to the drain region 309 is formed, and a pixel electrode 318 made of a transparent conductive film such as ITO is formed. The pixel electrode 318 has a film thickness of 1000 to 1200 Å and is arranged so as to overlap with the black matrix 316 in the largest possible area.

In this case, since the surface of the third interlayer insulating film 317 exhibits excellent flatness, the pixel electrode 318 formed thereon also exhibits excellent flatness, and rubbing failure during cell assembly and liquid crystal display. The disturbance of the electric field applied to the can be eliminated.

Through the above process, the pixel TFT shown in FIG. 4B is manufactured. At this time, a region 319 surrounded by a dotted line of the pixel TFT shown in FIG. 4B corresponds to a region 206 shown in FIG. That is, this region 3
19 functions as a storage capacitor. The capacity of this storage capacitor is proportional to the relative dielectric constant of the third interlayer insulating film 317 and inversely proportional to its film thickness.

The pixel electrode 318 shown in FIG.
In (2), the region where the storage capacitor is not formed on the pixel TFT (the region on the right side of the contact portion with the drain electrode 309 in FIG. 4B) extends to the pixel region where an image is displayed.

Although not shown in FIG. 4B, FIG.
The black matrix 3 including the region 319 shown in FIG.
A storage capacitor is formed in all regions where 16 and the edge portion of the pixel electrode 318 overlap (a region where the black matrix 204 and the pixel electrode 205 overlap in FIG. 2B).

Therefore, the area of the portion where the black matrix 316 and the pixel electrode 318 overlap each other, and the third interlayer insulating film 3
By calculating the film thickness and the relative dielectric constant of No. 17, a storage capacitor having a desired capacity can be designed.

Since the second interlayer insulating film 315 has a small relative permittivity and can obtain a film thickness in the range of 0.1 to 5.0 μm, it is formed between the gate line or data line and the black matrix 316. The generated parasitic capacitance can be suppressed to a negligible level.

With such a structure, it is possible to eliminate the conventional capacitance line and form the storage capacitance by using the black matrix. The following conditions are necessary for that purpose. (1) For the second interlayer insulating film, an organic resin material or an inorganic material having a small relative dielectric constant is used, and its thickness is increased. (2) As the third interlayer insulating film, a nitride film having a large relative dielectric constant is used, and the film thickness thereof is made thin.

As an effect of the structure as described above, it becomes possible to form the storage capacitor having the necessary minimum capacity while suppressing the parasitic capacitance without sacrificing the aperture ratio. Moreover, according to the calculation, the capacity of the storage capacitor formed in the pixel of 60 μm × 180 μm size is estimated.
It becomes 0.6-1.8pF.

Although not described in this embodiment, when a drive circuit is incorporated on the same substrate, a driver TFT is used.
And the pixel TFT are manufactured at the same time. For example, when assembling into an active matrix type liquid crystal display device as in this embodiment, a CM in which N-channel type and P-channel type thin film transistors are complementarily combined is used.
An OC structure is used for the driving circuit. Then, the pixel TFT as described in this embodiment may be arranged in the pixel region.

When the present invention is applied to such a liquid crystal display device, the number of patterning masks required is about 9 to 10. Therefore, the process is not particularly complicated.

The driver TFT described above is basically manufactured in the same process as the pixel TFT. However, the pixel electrode is not necessary, and it is completed by forming the drain electrode at the same time as forming the source electrode 314 in FIG.

[Embodiment 2] This embodiment shows an example in which a black matrix is provided only above a thin film transistor, unlike the structure shown in FIG. The greatest feature of this embodiment is that the gate lines and data lines are used as black matrices.

In the structure shown in FIG. 5, 501 is a gate line, 502 is a data line, 503 is a semiconductor layer forming an active layer of a thin film transistor, and 504 is a black matrix. 505 is a pixel electrode, 506 is a semiconductor layer 5
03 and a contact portion between the pixel electrode 505.

The point to be noted in this embodiment is that the pixel electrode 505 has its edges at the gate line 501 and the data line 50.
2 is formed so as to overlap. In this case, the parasitic capacitance normally formed between the pixel line 505 and the gate line 501 and the data line 502 poses a problem.

However, in this embodiment, the second interlayer insulating film 315, which serves as an insulating layer for parasitic capacitance, is made of a material having a small relative permittivity and can be made thick, so that the parasitic capacitance is reduced. It will be small enough not to have an adverse effect.

On the other hand, a storage capacitor is formed between the black matrix 504 and the pixel electrode 505 via the third interlayer insulating film 317. As described above, the third interlayer insulating film 3
Reference numeral 17 has a capacity capable of sufficiently functioning as a storage capacitor because its film thickness is as thin as 0.1 to 0.3 μm and its relative dielectric constant is larger than that of the second interlayer insulating film 315.

Therefore, since the pixel area is not narrowed inward by the black matrix 504, it is possible to realize a higher aperture ratio.

[Embodiment 3] In this embodiment, an example in which the structure of the island-shaped semiconductor layer in Embodiment 1 is changed will be described. Specifically, the channel length and channel width of the channel region are T
This is an example of a structure that changes depending on whether the FT is on or off.

This technique has already been reported by the present inventors, and its main purpose is to reduce the off current by substantially increasing the channel length and narrowing the channel width when the TFT is in the off state. Is. The outline of the technology will be described below.

FIG. 6 shows an island-shaped semiconductor layer 601 formed according to the process procedure of the first embodiment. Ions are selectively implanted into a region 602 which later functions as a channel. For example, when manufacturing an N-channel TFT, P + ions are added at 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm 3.
² , preferably with a dose of 3 × 10 ^{12 to} 3 × 10 ¹³ atoms / cm ² .

Then, ion-implanted regions 603 to 605 are formed so as to block the channel region. These regions 603 to 605 do not necessarily have to be in contact with the outer edge of the island-shaped semiconductor layer as shown in FIG. That is, it may be in a state of being scattered like islands in the region 602 which becomes a channel later.

An outline of the electrical characteristics of the TFT manufactured by using the island-shaped semiconductor layer on which such ion implantation is performed will be described with reference to FIG.

In FIG. 7A, 701 is a source region,
Reference numeral 702 denotes a drain region, and reference numerals 703 to 705 denote regions in which ions have been previously implanted as described above, which will be referred to as floating island regions (or ion implantation regions). At this time, an undoped substantially intrinsic semiconductor region (referred to as a base region) 706 and floating island regions 703 to 70.
The boundary with 5 has a high potential barrier. Therefore, N
When the channel type TFT is in the off state, electrons slightly move along the arrow of the base region 706. This movement of electrons is observed as off current (or leak current).

However, when the N-channel TFT is in the ON state, the base region 706 is inverted and the floating island regions 703 to 7 are formed.
Since the potential barrier with 05 becomes negligible, a large amount of electrons move along the path shown by the arrow in FIG. This electron movement is observed as an on-current.

The manner in which the potential barrier changes between the OFF state and the ON state of the TFT in this manner will be schematically described with reference to FIG. In FIG. 8, Vg is the gate voltage (V
g> 0), Ec is the conduction band, Ev is the valence band, and Ef is the Fermi level.

First, when the N-channel TFT is in the off state (a state where a negative voltage is applied to the gate), the base region 70
6 has a band state as shown in FIG. That is, since holes, which are minority carriers, are gathered on the semiconductor surface and electrons are dissipated, the movement of electrons between the source / drain is extremely small.

On the other hand, since the floating island regions 703 to 705 are implanted with P + ions, the Fermi level Ef is the conduction band E.
It is pushed up near c. At this time, floating island area 7
The bands 03 to 705 are in a band state as shown in FIG.

As shown in FIG. 8B, in the floating island regions 703 to 705 which are N-type semiconductor layers, even if a negative voltage is applied to the gate, the energy band bends only slightly.

Therefore, the energy difference between the energy of the valence band on the semiconductor surface in FIG. 8A and the energy of the valence band on the semiconductor surface in FIG. 8B corresponds to the potential barrier. Therefore, the electrons are emitted from the base region 70.
6 and the floating island regions 703 to 705 are not reciprocated.

Next, when the N-channel TFT is in the ON state (a state in which a positive voltage is applied to the gate), the base region 70
6 has a band state as shown in FIG. That is, since electrons, which are majority carriers, are accumulated on the semiconductor surface, electrons move between the source / drain.

At this time, the floating island regions 703 to 705 have a band state as shown in FIG. 8D. FIG.
As shown in (D), floating island regions 703 to 70, which are N-type semiconductor layers, are formed as in the case where a negative voltage is applied to the gate.
In No. 5, even if a positive voltage is applied to the gate, the energy band is hardly bent.

However, since the Fermi level Ef is originally pushed up near the conduction band Ec in FIG. 8D, many electrons always exist in the conductor.

Therefore, when a positive voltage is applied to the gate,
Since both the base region 706 and the floating island regions 703 to 705 are in a band state in which electrons easily move, the potential barrier at the boundary between the base region 706 and the floating island regions 703 to 705 can be ignored.

As described above, the base region 70 is in the off state.
Only 6 is a movement path of electrons, and in the ON state, the base region 706 and the floating island regions 703 to 705 are movement paths of electrons.

That is, compared with the W / L ratio when the TFT is in the OFF state, the W / L ratio in the ON state is much larger, and the OFF current can be reduced without impairing the ON current. . As a result, the on / off current ratio can be increased.

With such a structure, there is an advantage that a pixel TFT and a driver TFT having a response characteristic higher than the conventional one can be constructed without changing the area occupied by the island-shaped semiconductor layer of the pixel TFT.

Therefore, for example, even when the circuit configuration as shown in FIG. 2 is adopted, it is possible to dispose a high-performance pixel TFT without lowering the aperture ratio.

Further, it is expected that the substantial channel width when the TFT is in the OFF state in FIG. 7A tends to become narrower as the fine processing of the gate electrode progresses in the future. further,
Considering that the semiconductor layer 601 will eventually be thinned to about 200 Å, it can be said that the effect of reducing the leakage current shown in this embodiment is further enhanced.

[Embodiment 4] In this embodiment, another example of the semiconductor layer having the structure described in Embodiment 3 will be shown. Specifically, it relates to a technique of adding a high resistance region to a channel formation region.

FIG. 9A shows a gate electrode 901 added to the island-shaped semiconductor layer shown in FIG.
If the gate electrode having such a shape is provided, the gate electrode 90
Floating island region 6
It is possible to form 03, 604, and 605 in a self-aligned manner.

The behavior when an applied voltage is applied to the gate electrode 901 has been described in the third embodiment and will not be described. In addition, the example described below is similar to the second embodiment with N
The case of a channel type TFT will be described.

FIG. 9B shows the gate electrode 90 of FIG. 9A.
1 shows a configuration in which a part of 1 is removed by etching. This gate electrode 902 etching process may be performed after the floating island regions 603 to 605 are formed in a self-aligned manner by impurity ion implantation.

At this time, the gate electrode 9 in FIG.
A region 903 to which no voltage is applied by 02 always becomes a substantially intrinsic semiconductor layer. That is, it becomes a region that behaves as a high resistance like a so-called offset.

Therefore, when a negative voltage is applied to the gate electrode 902 (when the TFT is in the off state), the high resistance region 9
Since 03 substantially functions as an offset, the leak current is effectively suppressed. Further, when a positive voltage is applied to the gate electrode 902 (when the TFT is in the ON state), the high resistance region 903 is formed because the entire region of the island-shaped semiconductor layer serves as a path for electrons to flow as described in the third embodiment. Has almost no effect on the on-current.

Therefore, by adopting the structure of this embodiment, it is possible to form the pixel TFT in which the off current is further suppressed. That is, since the electric charge applied to the liquid crystal can be efficiently held, there is a margin in the design margin of the storage capacitor.

[Embodiment 5] In this embodiment, another example of the semiconductor layer having the structure described in Embodiment 3 will be shown. FIG. 9C is a configuration diagram of the semiconductor layer peripheral portion according to the present embodiment.

The feature of this embodiment is that the channel forming region is completely covered with the gate electrode 904. With such a configuration, the movement distance of electrons, that is, the substantial channel length is short when the TFT is in the ON state. Therefore, a thin film transistor having a high operation speed can be formed. A gate electrode 904 is indicated by 905.
It is the floating island region that exists below.

Another advantage of such a structure is that the thin film transistor can be formed in a small size to improve the aperture ratio.

[Embodiment 6] In this embodiment, an LPD (Liquid Phase Depth) is used as the second interlayer insulating film in Embodiment 1.
An example of using an insulating film applied by the osition method is shown below. Note that the manufacturing steps of the pixel TFT and the driver TFT have already been described in the first embodiment, and will not be described here.

The outline of the film formation by the LPD method (also called the spin method) is as follows. Although the explanation is given for the case of a silicon oxide film (SiO _x ) which is an inorganic material, SiOF film (relative permittivity 3.2 to 3.3) as another inorganic material or polyimide (relative permittivity) as an organic resin material. 2.8-3.4) etc. can also be used.

First, an H ₂ SiF ₆ solution is prepared, SiO ₂ : xH ₂ O is added thereto, and stirring is carried out for 3 hours. The processing temperature at this time is kept at 30 ° C. Next, the solution after stirring is filtered so that the solution has a desired concentration. After the adjustment is completed, stir while warming in a water bath or the like until reaching 50 ° C.

With the above, preparation of the solution for coating is completed.
Also, for example, if H ₃ BO ₃ is added to this solution, B
It is possible to form a silicon oxide-based coating containing + ions (so-called BSG coating).

The film formation is completed by immersing the substrate to be treated in the solution prepared according to the above procedure, rinsing it pure and drying it. If the organic resin material is applied, a desired coating solution may be prepared and the coating may be formed by the LPD method.

Polyimide or the like can be used as the organic resin material, which has a low relative dielectric constant of 2.8 to 3.4. In this case, the coating solution is applied on the substrate to be treated held on the spinner, and the spinner is rotated at 2000 rpm to form the coating. After forming the film, bake at 300 ℃ for 30 min to improve the film quality.

As described above, according to the LPD method, a desired film can be formed relatively easily. That is, it is possible to significantly improve the throughput. Further, since the film thickness can be freely adjusted by the time of immersion in the solution (rotation speed when using a spinner) and the solution concentration, it is easy to form a thick and flat film.

[Embodiment 7] In this embodiment, the storage capacitor according to the present invention (in this embodiment, particularly called the first storage capacitor)
An example in which a configuration in which another second storage capacitor is added in addition to the above is shown. This second storage capacitor was invented by the study of the present inventors.

In the second storage capacitor structure, the gate line and the pixel electrode form a capacitor via the first interlayer insulating film. A specific description will be given with reference to FIG.

FIG. 10 shows the first storage capacitor (1
FIG. 3 is a top view of a pixel region in the case where a region surrounded by a broken line indicated by 1) and a second storage capacitor according to the above invention (a region surrounded by a broken line indicated by 12) are used together.

Incidentally, 13 is a gate line, 14 is a data line,
Reference numeral 15 is a semiconductor layer forming an active layer of the thin film transistor.

The manufacturing process of the first storage capacitor 11 is the same as in the first embodiment.
As shown in FIG. Here, a manufacturing process of the second storage capacitor 12 will be briefly described with reference to FIGS. In the figure, the parts constituting the TFT have the same structure as in the first embodiment, so that detailed description will be omitted, and the reference numerals used in the first embodiment will be described only when necessary.

Further, FIG. 11 shows A in FIG.
It is sectional drawing cut | disconnected along the broken line shown by -A '.

First, according to the first embodiment, the third interlayer insulating film is formed until the film is formed, and the state shown in FIG. 11A is obtained. A titanium film 16 is a black matrix. Further, 13 is a gate electrode 30.
It is a gate line extending from 7.

In this state, the first line on the gate line 13
The interlayer insulating film 313, the second interlayer insulating film 315, and the third interlayer insulating film 317 are stacked.

Next, the second interlayer insulating film 315 and the third interlayer insulating film 317 on the gate line 13 are etched to form openings, and the pixel electrodes 17 are formed. It should be noted that 18 is the edge portion of the pixel electrode arranged in the adjacent pixel region.

At this time, the first storage capacitor 11 is formed between the black matrix 16 and the pixel electrode 17 via the third interlayer insulating film 317. In addition, the second storage capacitor 12 is formed on the gate line 13 between the gate line 13 and the pixel electrode 17 via the first interlayer insulating film 313.

Since the second storage capacitor 12 has a large film thickness and the second interlayer insulating film 315 having a small relative dielectric constant is removed, only the first interlayer insulating film 313 can be used as an insulating layer. . Therefore, by selecting a material having a large relative dielectric constant as the first interlayer insulating film 313 and reducing the film thickness, a storage capacitor having sufficient capacity can be formed.

Further, in this embodiment, the gate line 13 and the data line 14 can be used as a black matrix as described in the second embodiment. In this case, unlike the second embodiment, the second storage capacitor (capacitor formed by the gate line and the pixel electrode) is provided in addition to the first storage capacitor (capacitor formed by the black matrix and the pixel electrode). Sufficient capacity can be secured.

As described above, according to the structure of this embodiment, it is possible to realize a pixel region having a high aperture ratio after forming a storage capacitor having a sufficient capacity. further,
It goes without saying that further improvement is possible by using the special semiconductor layer shown in the third embodiment.

[Embodiment 8] This embodiment describes the present invention as Amorph.
This is an example applied to ous and Super-Multidomain AM-LCD. In this case, since an optically active material is added to a general TN material as a liquid crystal material and used, a rubbing step is not required.

[Embodiment 9] This embodiment is an example in which the present invention is applied to a liquid crystal display device of a field effect mode. Such modes include twisted nematic (TN) mode, super twisted nematic (STN) mode, electric field controlled birefringence (ECB) mode, phase transition (PC)
Mode and guest host (GH) mode.

Since this operation mode consumes less power and has a lower driving voltage, it is the most widely used because of its low power consumption.

[Embodiment 10] This embodiment is an example in which the present invention is applied to a liquid crystal display device of a dynamic scattering mode. In this mode, in addition to the electric field effect, a light scattering state associated with turbulent motion caused by the presence of a doped ion additive in the liquid crystal is used for display.

[Embodiment 11] This embodiment is an example in which the present invention is applied to a liquid crystal display device of a heat effect mode. This mode controls the phase transition due to the temperature of the liquid crystal by heating,
The change in optical characteristics based on it is used for display.

[0139]

According to the invention disclosed in this specification, it is easy to form a storage capacitor using a black matrix conventionally used as a light shielding film. This is for the following reasons.

First, by forming the black matrix on the second interlayer insulating film having a small relative dielectric constant and a large film thickness, parasitic capacitance formed between the gate line and the data line is suppressed. It is possible.

Secondly, a pixel electrode formed on the third interlayer insulating film is formed by forming a third interlayer insulating film made of a thin nitride film having a large relative permittivity on the black matrix. This is because it is possible to form a storage capacitor having a sufficient capacity between and.

As an effect of the above-mentioned invention, since the conventional capacitance line can be eliminated and the storage capacitor can be formed by utilizing the black matrix, the pixel region can be effectively utilized to the maximum extent.
A liquid crystal display device having a high aperture ratio can be configured.

[0143]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a pixel region in a liquid crystal display device.

FIG. 2 is a diagram showing a configuration of a pixel region in a liquid crystal display device.

FIG. 3 is a diagram schematically showing a manufacturing process of a pixel TFT.

FIG. 4 is a view schematically showing a manufacturing process of a pixel TFT.

FIG. 5 is a diagram illustrating a configuration of a pixel region in a liquid crystal display device.

FIG. 6 is a diagram schematically showing the structure of a semiconductor layer.

FIG. 7 is a diagram showing an outline of electric characteristics of a semiconductor layer.

FIG. 8 is a diagram showing an outline of a band state of a semiconductor layer.

FIG. 9 is a diagram schematically showing the structure of a semiconductor layer.

FIG. 10 is a diagram showing a configuration of a pixel region in a liquid crystal display device.

FIG. 11 is a diagram showing a cross-sectional structure of a pixel region in a liquid crystal display device.

[Explanation of symbols]

101 Gate line 102 Capacitance line 103 Data line 104 Pixel electrode 105 Semiconductor layer 106 Contact part between semiconductor layer and data line 107 Contact part between semiconductor layer and pixel electrode 108 Image display area 301 Glass substrate 302 Island-shaped semiconductor layer 303 Silicon oxide Film 304 Conductive film 305 Porous anodic oxide film 306 Dense anodic oxide film 307 Gate electrode 308 Source region 309 Drain region 310, 311 Low concentration impurity region 312 Channel formation region 313 First interlayer insulating film 314 Wiring electrode 315 Second interlayer insulating film (transmissive polyimide) 316 Black matrix 317 Third interlayer insulating film (silicon nitride film) 318 Pixel electrode 319 Storage capacitor 601 Island semiconductor layer 602 Channel formation region 603 to 605 Floating island region (ion implantation region) 90 1 Gate Electrode 903 High Resistance Region 905 Floating Island Region (Ion Implantation Region) 11 First Storage Capacitance 12 Second Storage Capacitance 13 Gate Line 16 Black Matrix 17 Pixel Electrode

Claims (7)

[Claims] 1. A plurality of gate lines and data lines arranged in a matrix on the same substrate, pixel electrodes arranged at respective intersections of the gate lines and data lines, and thin film transistors connected to the pixel electrodes. A first interlayer insulating film covering the gate line and a second interlayer insulating film formed of an organic resin material or an inorganic material covering the data line. A film, a black matrix formed above the thin film transistor via the second interlayer insulating film, a third interlayer insulating film made of a nitride film formed so as to cover the black matrix, and the third A pixel electrode formed on the interlayer insulating film, and a storage capacitor is provided between the black matrix and the pixel electrode via the third interlayer insulating film. The liquid crystal display device, characterized by being made. 2. A plurality of gate lines and data lines arranged in a matrix on the same substrate, pixel electrodes arranged at respective intersections of the gate lines and data lines, and thin film transistors connected to the pixel electrodes. A first interlayer insulating film covering the gate line and a second interlayer insulating film formed of an organic resin material or an inorganic material covering the data line. A film, a black matrix formed above the thin film transistor via the second interlayer insulating film, a third interlayer insulating film made of a nitride film formed so as to cover the black matrix, and the third A pixel electrode formed on the interlayer insulating film, and a storage capacitor between the black matrix and the pixel electrode via the third interlayer insulating film. It is formed, a liquid crystal display device, wherein the pixel electrodes are not directly touch the second interlayer insulating film. 3. The film thickness of the second interlayer insulating film according to claim 1 or 2, wherein the film thickness of the second interlayer insulating film is 0.1 to 5.0 μm, and the film thickness of the third interlayer insulating film is 0.1 to 0.3 μm. Liquid crystal display device. 4. The nitride film according to claim 1 or 2, wherein AlN, AlN _X O _Y , Si ₃ N ₄ and SiO _X N are used as the nitride film.
A liquid crystal display device, characterized in that one or more selected from the insulating films represented by _Y are used. 5. The liquid crystal display device according to claim 1, wherein the semiconductor layer forming the active layer of the thin film transistor is formed separately in a base region and a floating island region. 6. A plurality of gate lines and data lines arranged in a matrix on the same substrate, pixel electrodes arranged at respective intersections of the gate lines and data lines, and thin film transistors connected to the pixel electrodes. In manufacturing a liquid crystal display device including at least, a first interlayer insulating film that covers the gate line and a second interlayer insulating film that covers the data line and is made of an organic resin material or an inorganic material are formed. A step of forming a black matrix made of a metal film on the second interlayer insulating film, a step of forming a third interlayer insulating film made of a nitride film so as to cover the black matrix, 2 and the step of forming a contact hole in the third interlayer insulating film, and the step of forming a pixel electrode made of a transparent conductive film on the third interlayer insulating film. A method for manufacturing a liquid crystal display device, characterized in that allowed to form a storage capacitor through the third interlayer insulating film between the pixel electrode and the black matrix. 7. The step of forming a contact hole according to claim 6, wherein a step of forming an opening by etching away the third interlayer insulating film, and a step of forming the opening by using the third interlayer insulating film as a mask. A method of manufacturing a liquid crystal display device, comprising: a step of etching and removing the second interlayer insulating film exposed at a lower portion to form an opening.