JP3696687B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The invention disclosed in this specification relates to a structure of a liquid crystal display device controlled by a semiconductor device using a crystalline silicon film. In particular, the present invention relates to a configuration of a pixel region of an active matrix liquid crystal display device.
[0002]
[Prior art]
Recently, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix liquid crystal display devices has increased.
[0003]
In an active matrix liquid crystal display device, a thin film transistor is disposed in each of millions of pixels arranged in a matrix, and charges entering and exiting each pixel electrode are controlled by a switching function of the thin film transistor.
[0004]
Liquid crystal is sandwiched between each pixel electrode and the counter electrode to form a kind of capacitor. Therefore, by controlling the flow of electric charges into and out of the capacitor with the thin film transistor, the electro-optical characteristics of the liquid crystal can be changed, and the light transmitted through the liquid crystal panel can be controlled to display an image.
[0005]
In addition, the capacitor having such a configuration has a problem in that the holding voltage gradually decreases due to leakage or the like, so that the electro-optical characteristics of the liquid crystal change and the contrast of image display deteriorates.
[0006]
Therefore, it is common to install another capacitor called a holding capacitor in series with a capacitor composed of liquid crystal, and to supply the charge lost due to leakage or the like to the capacitor composed of liquid crystal.
[0007]
Here, FIG. 1 shows a configuration diagram of a pixel region in a conventional active matrix liquid crystal display device. As shown in FIG. 1A, the gate line 101 and the capacitor line 102 formed in parallel thereto intersect with the data line 103 in a grid pattern. A pixel electrode 104 is disposed in a region surrounded by them (hereinafter, this region is referred to as a pixel region). The capacitor line 102 and the pixel electrode 104 are three-dimensionally overlapped with each other via the first and second interlayer insulating films to form a storage capacitor.
[0008]
Reference numeral 105 denotes a semiconductor layer that constitutes an active layer of the thin film transistor. Reference numeral 106 denotes a contact portion with the data line, and reference numeral 107 denotes a contact portion with the pixel electrode.
[0009]
In FIG. 1A, the pixel region surrounded by the gate lines 101 and the data lines 103 formed so as to intersect with each other in a lattice shape is an image display region, and it is required to secure as large an area as possible. The
[0010]
However, in the structure shown in FIG. 1A, since the capacitor line 102 needs to be provided in the region, the pixel region is narrowed by that amount, that is, the aperture ratio is deteriorated.
[0011]
Further, as shown in FIG. 1A, the pixel electrode 104 is disposed so as not to overlap the gate line 101 and the data line 103. This is because the parasitic capacitance formed when they overlap each other adversely affects the operation speed of the liquid crystal display device.
[0012]
However, on the other hand, the edge of the pixel electrode 104 is disturbed by an electric field when a voltage is applied, and a display defect such as blurring of the image occurs. .
[0013]
Further, the semiconductor layer 105 constituting the active layer of the thin film transistor needs to be shielded from light from the outside. This is because when the semiconductor layer is irradiated with light, the conductivity of the semiconductor layer changes due to the photoexcitation phenomenon.
[0014]
For the purpose of light shielding, a means for providing a black matrix (BM) on a substrate on which a thin film transistor is disposed or a counter substrate is generally employed. Here, FIG. 1B shows a region entering the visual field when the black matrix is arranged.
[0015]
As shown in FIG. 1B, the gate line 101, the capacitor line 102, the data line 103, and the semiconductor layer 105 are all covered with a black matrix and do not enter the field of view. Therefore, the area indicated by 108 is the actual image display area.
[0016]
As described above, the capacitor line 102 narrows the pixel region more than necessary, and is a factor that deteriorates the aperture ratio.
[0017]
[Problems to be solved by the invention]
The invention disclosed in this specification provides a technique for solving the above-described conventional problems. That is, it is an object to provide a technique for forming a pixel region having a high aperture ratio.
[0018]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
A plurality of gate lines and data lines arranged in a matrix on the same substrate;
A pixel electrode disposed at each intersection of the gate line and the data line, and a thin film transistor connected to the pixel electrode;
A liquid crystal display device comprising at least
A first interlayer insulating film covering the gate line and a second interlayer insulating film made of an organic resin material or an inorganic material formed to cover the data line;
A black matrix formed above the thin film transistor via the second interlayer insulating film;
A third interlayer insulating film made of a nitride film formed to cover the black matrix;
A pixel electrode formed on the third interlayer insulating film;
Having at least
A storage capacitor is formed between the black matrix and the pixel electrode through the third interlayer insulating film.
[0019]
The configuration of another invention is as follows:
A plurality of gate lines and data lines arranged in a matrix on the same substrate;
A pixel electrode disposed at each intersection of the gate line and the data line, and a thin film transistor connected to the pixel electrode;
A liquid crystal display device comprising at least
A first interlayer insulating film covering the gate line and a second interlayer insulating film made of an organic resin material or an inorganic material formed to cover the data line;
A black matrix formed above the thin film transistor via the second interlayer insulating film;
A third interlayer insulating film made of a nitride film formed to cover the black matrix;
A pixel electrode formed on the third interlayer insulating film;
Having at least
A storage capacitor is formed between the black matrix and the pixel electrode through the third interlayer insulating film,
The pixel electrode does not directly touch the second interlayer insulating film.
[0020]
The configuration of another invention is as follows:
A plurality of gate lines and data lines arranged in a matrix on the same substrate;
A pixel electrode disposed at each intersection of the gate line and the data line, and a thin film transistor connected to the pixel electrode;
In producing a liquid crystal display device having at least
Forming a first interlayer insulating film covering the gate line and a second interlayer insulating film made of an organic resin material or an inorganic material covering the data line;
Forming a black matrix made of a metal film on the second interlayer insulating film;
Forming a third interlayer insulating film made of a nitride film covering the black matrix;
Forming a contact hole in the second and third interlayer insulating films;
Forming a pixel electrode made of a transparent conductive film on the third interlayer insulating film;
Having at least
A storage capacitor is formed between the black matrix and the pixel electrode through the third interlayer insulating film.
[0021]
The gist of the present invention is to provide the black matrix with a function as an electrode for forming a storage capacitor in addition to a function as a light shielding film which is an original purpose.
[0022]
A top view of a pixel region of a liquid crystal display device constructed according to the present invention is shown in FIG. In FIG. 2, 201 is a gate line extending from the gate electrode, and 202 is a data line for transmitting an image signal.
[0023]
The gate lines 201 and the data lines 202 are arranged in a matrix on the same substrate, and a thin film transistor is disposed at each intersection. Reference numeral 203 denotes a semiconductor layer constituting the active layer of the thin film transistor.
[0024]
A black matrix 204 is disposed above the gate line 201, the data line 202, and the semiconductor layer 203 so as to shield them. The data line 202 and the black matrix 204 are insulated by a second interlayer insulating film having a thickness of 0.1 to 5.0 μm. The second interlayer insulating film is made of an organic resin material or an inorganic material.
[0025]
Further, a pixel electrode 205 is provided on the black matrix 204 via a third interlayer insulating film. This third interlayer insulating film is composed of a nitride film, and as the nitride film, AlN, AlN _X O _Y , Si _Three N _Four , SiO _X N _Y One kind or a plurality of kinds selected from the insulating films represented by the above can be used. The film thickness of the third interlayer insulating film may be 0.1 to 0.3 μm.
[0026]
With such a structure, a capacitor is formed in a region 206 where the pixel electrode 205 and the black matrix 204 overlap three-dimensionally with the third interlayer insulating film interposed therebetween. The present invention uses this capacity as a storage capacity.
[0027]
Here, as a feature of the present invention, it is important that the third interlayer insulating film is a nitride film. There are three major advantages of using a nitride film.
[0028]
The first is the passivation effect of the nitride film. For example, Si _Three N _Four Since the silicon nitride film indicated by is dense, it is widely used as a protective film (passivation film) for protecting the device from external contamination and the like.
[0029]
Second, the relative dielectric constant of the nitride film is large. For example, Si _Three N _Four The dielectric constant of the silicon nitride film indicated by is about 7, and has a relative dielectric constant about twice that of the organic resin material or inorganic material used as the second interlayer insulating film.
[0030]
Accordingly, since the storage capacitor formed between the black matrix 204 and the pixel electrode 205 has a large relative dielectric constant of the third interlayer insulating film, a necessary and sufficient capacity can be obtained.
[0031]
Thirdly, it can also be used as a mask when forming an opening (contact hole) in the second interlayer insulating film. This is because the etching selectivity can be increased between the organic resin material or inorganic material which is the second interlayer insulating film and the nitride film.
[0032]
For example, if a resist mask is used as a mask when forming openings in polyimide, which is an organic resin material, the selection ratio cannot be obtained because the same organic material is used, and openings with a depth greater than the thickness of the resist mask are used. There was a problem that could not be formed.
[0033]
In that respect, since the nitride film has a sufficient selection ratio, if only the nitride film is first etched with a hydrofluoric acid gas and the remaining nitride film is used as a mask, an opening having a desired depth is formed in the polyimide. It becomes possible to form.
[0034]
Others such as AlN, AlN _X O _Y When using the nitride films shown by the above, these nitride films have the advantage of excellent thermal conductivity. Therefore, since heat can be dissipated without confining heat to the device, it is effective in the case where heat is generated by high-speed operation like a driver TFT.
[0035]
On the other hand, an advantage of using an organic resin material or an inorganic material as the second interlayer insulating film is that the relative dielectric constant is small and the film thickness can be increased. For example, the parasitic capacitance formed between the black matrix 204 and the gate line 201 and the data line 202 can be suppressed to a level that does not cause a problem because the relative dielectric constant of the second interlayer insulating film is sufficiently small.
[0036]
Details of the present invention configured as described above will be described with reference to the examples described below.
[0037]
【Example】
[Example 1]
In this embodiment, an example in which a pixel region having the structure shown in FIG. 2 is formed using the present invention will be described. Specifically, a technique for forming a storage capacitor with a black matrix and a pixel electrode will be described in detail.
[0038]
FIG. 3 is a manufacturing process diagram of the pixel TFT constituting the pixel region shown in FIG. First, an amorphous silicon film (not shown) having a thickness of 200 to 500 mm is formed on a glass substrate 301 having an insulating film with a thickness of 2000 mm as a base film on the surface. The insulating film is silicon oxide (SiO ₂ ), Silicon oxynitride (SiO _X N _Y ), A silicon nitride film (SiN), or the like may be formed by a plasma CVD method, a low pressure thermal CVD method, a sputtering method, or the like.
[0039]
Next, the amorphous silicon film (not shown) is crystallized by means such as heating, laser annealing, or a combination of both. In addition, it is effective to add a metal element that promotes crystallization during crystallization.
[0040]
When crystallization is completed, the obtained crystalline silicon film (not shown) is patterned to form the island-shaped semiconductor layer 302. After the island-like semiconductor layer 302 is formed, a silicon oxide film 303 that functions as a gate insulating film later is formed to a thickness of 1200 mm. Of course, a silicon oxynitride film or a silicon nitride film may be used.
[0041]
Next, a conductive film 304 is formed to a thickness of 2000 to 2500 mm. In this embodiment, an aluminum film containing 0.2 wt% scandium is used. Scandium has the effect of suppressing protrusions such as hillocks and whiskers generated on the aluminum surface during heat treatment or the like. This aluminum film 304 later functions as a gate electrode.
[0042]
In this way, the state of FIG. When the state of FIG. 3A is obtained, anodization is performed in the electrolytic solution using the aluminum film 304 as an anode. As the electrolytic solution, an ethylene glycol solution of 3% tartaric acid neutralized with aqueous ammonia and adjusted to PH = 6.92 is used.
Moreover, it processes as a formation current 5mA and the ultimate voltage 10V by using platinum as a cathode.
[0043]
The thin and dense anodic oxide film (not shown) formed in this way has an effect of improving adhesion with the photoresist when the aluminum film 304 is patterned. Further, the film thickness can be controlled by controlling the voltage application time.
[0044]
Next, the aluminum film 304 is patterned to form a gate electrode (not shown). However, it is the part of the interior that finally remains that substantially functions as the gate electrode.
[0045]
Next, a second anodic oxidation is performed to form a porous anodic oxide film 305 (see FIG. 3B). The electrolytic solution is a 3% oxalic acid aqueous solution, which is treated with platinum as a cathode at a formation current of 2 to 3 mA and an ultimate voltage of 8V.
[0046]
At this time, anodic oxidation proceeds in a direction parallel to the substrate. Further, the length of the porous anodic oxide film 305 can be controlled by controlling the voltage application time.
[0047]
Further, after removing a photoresist (not shown) used for patterning the aluminum film with a special stripping solution, the third anodic oxidation is performed to obtain the state of FIG.
[0048]
For this anodic oxidation, an electrolytic solution is used in which an ethylene glycol solution of 3% tartaric acid is neutralized with ammonia water and adjusted to PH = 6.92. Then, treatment is performed with platinum as a cathode and a formation current of 5 to 6 mA and an ultimate voltage of 40 to 100 V.
[0049]
The anodic oxide film 306 formed at this time is very dense and strong. Therefore, it has an effect of protecting the gate electrode 307 from damage and heat generated in a subsequent process such as a doping process. The film thickness is 500 to 1500 mm.
[0050]
Next, an impurity is implanted into the island-shaped semiconductor layer 302 by ion doping. For example, if an N-channel TFT is manufactured, P + ions may be implanted as an impurity, and if a P-channel TFT is manufactured, B + ions may be implanted as an impurity.
[0051]
First, the first ion doping is performed in the state of FIG. In this embodiment, P + ions are implanted at an acceleration voltage of 80 kV and a dose of 1 × 10. ¹⁵ Atom / cm ² To do.
[0052]
As a result, the gate electrode 307 and the porous anodic oxide film 305 serve as a mask, and regions 308 and 309 to be the source / drain later are formed in a self-aligned manner. (Figure 3 (C))
[0053]
Next, as shown in FIG. 3C, the porous anodic oxide film 305 is removed and a second doping is performed. The second P + ion implantation is an acceleration voltage of 80 kV and a dose of 1 × 10. ¹⁴ Atom / cm ² To do.
[0054]
Then, the gate electrode 307 serves as a mask, and low-concentration impurity regions 310 and 311 having a lower impurity concentration than the source region 308 and the drain region 309 are formed in a self-aligned manner.
[0055]
At the same time, since no impurities are implanted immediately below the gate electrode 307, a region 312 functioning as a TFT channel is formed in a self-aligned manner.
[0056]
The low-concentration impurity region 311 thus formed is particularly called an LDD region, and has an effect of suppressing the formation of a high electric field between the channel region 312 and the drain region 309.
[0057]
Next, KrF excimer laser is applied to 200-300mJ / cm. ² By irradiating with the energy density of P +, the ion-implanted P + ions are activated. The activation may be performed by thermal annealing at 300 to 450 ° C. for 2 hours, or laser annealing and thermal annealing may be used in combination.
[0058]
Next, a first interlayer insulating film 313 is formed by a plasma CVD method. As the interlayer insulating film 313, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like can be used. The film thickness is 0.5 to 1.0 μm.
[0059]
After forming the first interlayer insulating film 313, a contact hole is formed in the source region 308, and an aluminum film (not shown) is formed to a thickness of 3000 mm. Next, a source electrode 314 is formed by patterning an aluminum film (not shown). (Fig. 3 (D))
[0060]
Next, a second interlayer insulating film 315 is formed to a thickness of 0.1 to 5.0 μm so as to cover the source electrode 314. In this embodiment, the film thickness is 1.5 μm. The second interlayer insulating film 315 can be made of an organic resin material or an inorganic material. In this embodiment, transparent polyimide is used as the organic resin material. The relative dielectric constant of this polyimide is a small value of 2.8 to 3.4.
[0061]
In addition, since such an organic resin material is easy to form a film and can easily increase the film thickness, it is possible to reduce unevenness due to the device shape and realize an excellent flat surface.
[0062]
Next, a titanium film as a black matrix 316 is formed on the second interlayer insulating film 315 to a thickness of 1000 mm. Of course, a metal film such as a chromium film or an aluminum film may be used. (Fig. 4 (A))
[0063]
When the state of FIG. 4A is obtained, a third interlayer insulating film 317 is formed to a thickness of 0.1 to 0.3 μm so as to cover the black matrix 316. This third interlayer insulating film 317 is made of AlN, AlN. _X O _Y , Si _Three N _Four , SiO _X N _Y One kind or a plurality of kinds selected from the insulating films represented by the above can be used.
[0064]
In this example, Si _Three N _Four Is formed to a thickness of 0.2 μm. This silicon nitride film has SiH as a deposition gas. _Four , NH _Three , H ₂ Therefore, hydrogen is contained in the film and the film stress is relieved.
[0065]
Then, a contact hole for connecting to the drain region 309 is formed, and a pixel electrode 318 made of a transparent conductive film such as ITO is formed. The film thickness of the pixel electrode 318 is 1000 to 1200 mm, and is arranged so as to overlap with the black matrix 316 in as wide an area as possible.
[0066]
In this case, since the surface of the third interlayer insulating film 317 exhibits excellent flatness, the pixel electrode 318 formed thereon also exhibits good flatness, and the rubbing failure during cell assembly and application to the liquid crystal Disturbance of the electric field can be eliminated.
[0067]
Through the above process, the pixel TFT shown in FIG. 4B is manufactured. At this time, a region 319 surrounded by a dotted line of the pixel TFT shown in FIG. 4B corresponds to a region 206 shown in FIG. That is, this region 319 functions as a storage capacitor. The capacity of this storage capacitor is proportional to the relative dielectric constant of the third interlayer insulating film 317 and inversely proportional to its film thickness.
[0068]
Note that in the pixel electrode 318 illustrated in FIG. 4B, an image display is performed in a region where a storage capacitor is not formed over the pixel TFT (a region on the right side of the contact portion with the drain electrode 309 in FIG. 4B). Extends to the pixel area.
[0069]
Although not shown in FIG. 4B, the black matrix 316 overlaps with the edge portion of the pixel electrode 318 including the region 319 shown in FIG. 4B (the black matrix 204 in FIG. 2B). A storage capacitor is formed in a region where the pixel electrode 205 overlaps.
[0070]
Accordingly, it is possible to design a storage capacitor having a desired capacity by calculating the area where the black matrix 316 and the pixel electrode 318 overlap, the thickness of the third interlayer insulating film 317, and the relative dielectric constant. is there.
[0071]
Note that the second interlayer insulating film 315 has a small relative dielectric constant and can increase the film thickness in the range of 0.1 to 5.0 μm. Therefore, the second interlayer insulating film 315 is a parasitic element formed between the gate line or the data line and the black matrix 316. Capacity can be suppressed to a negligible level.
[0072]
By adopting such a configuration, it is possible to eliminate the conventional capacitance line and form a storage capacitor using a black matrix. The following are listed as necessary conditions for this purpose.
(1) The second interlayer insulating film is made of an organic resin material or an inorganic material having a small relative dielectric constant, and the film thickness is increased.
(2) A nitride film having a large relative dielectric constant is used as the third interlayer insulating film, and the film thickness is reduced.
[0073]
As an effect of the configuration as described above, it is possible to form a storage capacitor having a necessary minimum capacity while suppressing parasitic capacitance without sacrificing the aperture ratio. In addition, according to the calculation, the capacity of the storage capacitor formed in a pixel having a size of 60 μm × 180 μm is approximately 0.6 to 1.8 pF.
[0074]
Although not described in this embodiment, when a drive circuit is incorporated on the same substrate, a driver TFT and a pixel TFT are manufactured simultaneously. For example, considering that it is incorporated in an active matrix liquid crystal display device as in this embodiment, a CMOC structure in which N-channel and P-channel thin film transistors are complementarily combined is used for a drive circuit. Then, pixel TFTs as described in this embodiment may be arranged in the pixel region.
[0075]
When the present invention is applied to such a liquid crystal display device, the required patterning mask is about 9 to 10 sheets. Therefore, the process is not particularly complicated.
[0076]
The driver TFT described above is basically manufactured in the same process as the pixel TFT. However, the pixel electrode is not necessary, and the pixel electrode is completed by forming the source electrode 314 and the drain electrode at the same time in FIG.
[0077]
[Example 2]
In this embodiment, an example in which a black matrix is provided only above a thin film transistor, unlike the structure shown in FIG. The greatest feature of this embodiment is that the gate line and the data line are substituted as a black matrix.
[0078]
In the structure shown in FIG. 5, 501 is a gate line, 502 is a data line, 503 is a semiconductor layer constituting an active layer of the thin film transistor, and 504 is a black matrix. Reference numeral 505 denotes a pixel electrode, and reference numeral 506 denotes a contact portion between the semiconductor layer 503 and the pixel electrode 505.
[0079]
What should be noted in this embodiment is that the pixel electrode 505 is formed so that the edge thereof overlaps the gate line 501 and the data line 502. In this case, normally, parasitic capacitance formed between the gate line 501 and the data line 502 and the pixel electrode 505 becomes a problem.
[0080]
However, in this embodiment, since the second interlayer insulating film 315 serving as the insulating layer of the parasitic capacitance is a material having a small relative dielectric constant and can be made thick, the parasitic capacitance has an adverse effect. It will be as small as possible.
[0081]
On the other hand, a storage capacitor is formed between the black matrix 504 and the pixel electrode 505 through a third interlayer insulating film 317. As described above, the third interlayer insulating film 317 has a thin film thickness of 0.1 to 0.3 μm and a relative dielectric constant larger than that of the second interlayer insulating film 315, and thus has a capacity capable of functioning as a sufficient storage capacity.
[0082]
Accordingly, since the pixel region is not narrowed inward by the black matrix 504, a higher aperture ratio can be realized.
[0083]
Example 3
In this example, an example in which the configuration of the island-shaped semiconductor layer is changed in Example 1 will be described. Specifically, this is an example in which the channel length and the channel width of the channel region change depending on whether the TFT is on or off.
[0084]
This technique has already been reported by the present inventors, and the gist is to reduce the off-current by substantially increasing the channel length and reducing the channel width when the TFT is in the OFF state. The outline of the technology will be described below.
[0085]
FIG. 6 shows an island-shaped semiconductor layer 601 formed according to the process procedure of the first embodiment. Ions are selectively implanted into a region 602 that functions as a channel later. For example, when an N-channel TFT is manufactured, 1 × 10 P + ions are used. ¹² ~ 1x10 ¹⁴ Atom / cm ² , Preferably 3 × 10 ¹² ~ 3x10 ¹³ Atom / cm ² Doping with a dose amount of
[0086]
Then, regions 603 to 605 into which ions are implanted so as to block the channel region are formed. These regions 603 to 605 are not necessarily in contact with the outer edge of the island-shaped semiconductor layer as shown in FIG. That is, a state in which islands are scattered in the region 602 to be a channel later may be used.
[0087]
An outline of electrical characteristics of a TFT manufactured using an island-shaped semiconductor layer subjected to such ion implantation will be described with reference to FIG.
[0088]
7A, reference numeral 701 denotes a source region, reference numeral 702 denotes a drain region, reference numerals 703 to 705 denote regions previously implanted with ions as described above, which are referred to as floating island regions (or ion implantation regions). At this time, the boundary between the substantially undoped semiconductor region (hereinafter referred to as a base region) 706 and the floating island regions 703 to 705 has a high potential barrier. Therefore, when the N-channel TFT is off, electrons move slightly along the arrow in the base region 706. This electron movement is observed as an off-current (or leakage current).
[0089]
However, when the N-channel TFT is in the ON state, the base region 706 is inverted so that the potential barrier with the floating island regions 703 to 705 can be ignored. Therefore, the path shown by the arrow in FIG. A lot of electrons move. This electron movement is observed as an on-current.
[0090]
The manner in which the potential barrier changes between the off state and the on state of the TFT in this way will be schematically described with reference to FIG. In FIG. 8, Vg represents a gate voltage (Vg> 0), Ec represents a conduction band, Ev represents a valence band, and Ef represents a Fermi level.
[0091]
First, when the N-channel TFT is in an off state (a state where a negative voltage is applied to the gate), the base region 706 is in a band state as shown in FIG. That is, since holes that are minority carriers gather on the semiconductor surface and electrons are removed, there is very little movement of electrons between the source and drain.
[0092]
On the other hand, since the floating island regions 703 to 705 are implanted with P + ions, the Fermi level Ef is pushed closer to the conduction band Ec. At this time, the floating island regions 703 to 705 are in a band state as shown in FIG.
[0093]
As shown in FIG. 8B, in the floating island regions 703 to 705 which are N-type semiconductor layers, even if a negative voltage is applied to the gate, the energy band is bent only slightly.
[0094]
Therefore, the energy difference between the energy of the valence band on the semiconductor surface in FIG. 8A and the energy of the valence band on the semiconductor surface in FIG. 8B corresponds to the potential barrier. Therefore, electrons do not reciprocate between the base region 706 and the floating island regions 703 to 705.
[0095]
Next, when the N-channel TFT is in an on state (a state where a positive voltage is applied to the gate), the base region 706 is in a band state as shown in FIG. That is, electrons, which are majority carriers, are accumulated on the semiconductor surface, so that electrons move between the source and drain.
[0096]
At this time, the floating island regions 703 to 705 are in a band state as shown in FIG. As shown in FIG. 8D, as in the case where a negative voltage is applied to the gate described above, in the floating island regions 703 to 705 which are N-type semiconductor layers, even if a positive voltage is applied to the gate, there is almost no energy band. Unyielding.
[0097]
However, since the Fermi level Ef is originally pushed up near the conduction band Ec in FIG. 8D, a large number of electrons are always present in the conductor.
[0098]
Therefore, when a positive voltage is applied to the gate, the base region 706 and the floating island regions 703 to 705 are both in a band state in which electrons easily move. Therefore, the potential barrier at the boundary between the base region 706 and the floating island regions 703 to 705 is Can be ignored.
[0099]
As described above, in the off state, only the base region 706 is an electron movement path, and in the on state, the base area 706 and the floating island areas 703 to 705 are electron movement paths.
[0100]
In other words, the W / L ratio when the TFT is in the on state is much larger than the W / L ratio when the TFT is in the off state, and the off current can be reduced without impairing the on current. Thereby, the on / off current ratio can be increased.
[0101]
With such a structure, there is an advantage that a pixel TFT and a driver TFT having response characteristics higher than those of the conventional one can be configured without changing the occupied area of the island-shaped semiconductor layer of the pixel TFT.
[0102]
Therefore, for example, even when the circuit configuration as shown in FIG. 2 is adopted, it is possible to dispose a high-performance pixel TFT without reducing the aperture ratio.
[0103]
Further, as the fine processing of the gate electrode proceeds, it is expected that the substantial channel width when the TFT is in the OFF state in FIG. Furthermore, it can be said that the effect of reducing the leakage current shown in this embodiment is further enhanced considering that the semiconductor layer 601 is thinned to about 200 mm.
[0104]
Example 4
In this example, another example of the semiconductor layer having the structure described in Example 3 is shown. Specifically, the present invention relates to a technique for adding a high resistance region to a channel formation region.
[0105]
FIG. 9A shows a gate electrode 901 added to the island-like semiconductor layer shown in FIG. If the gate electrode having such a shape is provided, impurity ions can be implanted using the gate electrode 901 as a mask, and the floating island regions 603, 604, and 605 can be formed in a self-aligning manner.
[0106]
The behavior when an applied voltage is applied to the gate electrode 901 has been described in the third embodiment and will not be described. In the example described below, an N-channel TFT is described as in the second embodiment.
[0107]
FIG. 9B shows a structure in which a part of the gate electrode 901 in FIG. 9A is removed by etching. The etching process of the gate electrode 902 may be performed after the floating island regions 603 to 605 are formed in a self-aligning manner by impurity ion implantation.
[0108]
At this time, a region 903 to which no voltage is applied by the gate electrode 902 in FIG. 9B is always a substantially intrinsic semiconductor layer. That is, it becomes a region that behaves as a high resistance like a so-called offset.
[0109]
Accordingly, when a negative voltage is applied to the gate electrode 902 (when the TFT is in an off state), the high resistance region 903 substantially functions as an offset, so that leakage current is effectively suppressed. Further, when a positive voltage is applied to the gate electrode 902 (when the TFT is on), the entire region of the island-shaped semiconductor layer becomes a path for electrons to flow as described in Embodiment 3, so that the high resistance region 903 is Little effect on on-current.
[0110]
Therefore, by adopting the configuration according to this embodiment, it is possible to form a pixel TFT in which off current is further suppressed. That is, since the charge given to the liquid crystal can be efficiently held, the design margin of the storage capacitor can be afforded.
[0111]
Example 5
In this example, another example of the semiconductor layer having the structure described in Example 3 is shown. FIG. 9C is a configuration diagram of the periphery of the semiconductor layer according to this example.
[0112]
The feature of this embodiment is that the channel formation region is completely covered with the gate electrode 904. With such a configuration, when the TFT is in the on state, the electron moving distance, that is, the substantial channel length can be shortened. Accordingly, a thin film transistor having a high operating speed can be formed. Reference numeral 905 denotes a floating island region existing under the gate electrode 904.
[0113]
Another advantage of such a configuration is that the aperture ratio can be improved by forming a thin film transistor with a small size.
[0114]
Example 6
In this embodiment, an example in which an insulating film applied by an LPD (Liquid Phase Deposition) method is used as the second interlayer insulating film in the first embodiment will be described. Note that the manufacturing steps of the pixel TFT and the driver TFT have already been described in Embodiment 1, and thus are omitted here.
[0115]
The outline of film formation by the LPD method (also called spin method) is as follows. The description is based on an inorganic material silicon oxide-based film (SiO 2 _X However, it is also possible to use a SiOF film (relative dielectric constant: 3.2 to 3.3) as another inorganic material and polyimide (relative dielectric constant: 2.8 to 3.4) as an organic resin material.
[0116]
First, H ₂ SiF ₆ Prepare a solution and add SiO ₂ : xH ₂ Add O and stir for 3 hr. The processing temperature at this time is kept at 30 ° C. Next, the solution after stirring is filtered to adjust the solution to a desired concentration. When the adjustment is complete, stir while warming up to 50 ° C in a water bath or the like.
[0117]
This completes the preparation of the coating solution. In addition, for example, H _Three BO _Three Can be added to form a silicon oxide-based film (so-called BSG film) containing B + ions in the film.
[0118]
After the substrate to be treated is immersed in the solution prepared according to the above procedure, the film formation is completed if it is rinsed pure and dried. Note that if an organic resin material is applied, a desired solution for coating a film may be prepared and a film may be formed by the LPD method.
[0119]
Examples of the organic resin material include polyimide and the relative dielectric constant is as low as 2.8 to 3.4. In this case, the coating solution is applied onto the substrate to be processed held on the spinner, and the spinner is rotated at 2000 rpm to form a coating. After film formation, improve the film quality by baking at 300 ° C for about 30 min.
[0120]
As described above, when the LPD method is used, a desired film can be formed relatively easily. That is, the throughput can be greatly improved. In addition, since the film thickness can be freely adjusted by the time of immersion in the solution (rotation speed or the like when using a spinner) and the solution concentration, it is easy to form a thick and flat film.
[0121]
Example 7
In this embodiment, an example is shown in which a second holding capacitor is added in addition to the holding capacitor according to the present invention (in this embodiment, particularly called the first holding capacitor). This second holding capacity was invented by the inventors' research.
[0122]
In the second storage capacitor, the gate line and the pixel electrode form a capacitor through the first interlayer insulating film. A specific description will be given with reference to FIG.
[0123]
FIG. 10 shows a case where the first storage capacitor according to the present invention (region surrounded by a broken line indicated by 11) and the second storage capacitor according to the previous invention (region surrounded by a broken line indicated by 12) are used together. It is a top view of a pixel region.
[0124]
Note that 13 is a gate line, 14 is a data line, and 15 is a semiconductor layer constituting an active layer of the thin film transistor.
[0125]
The manufacturing process of the first storage capacitor 11 is as described in the first embodiment. Here, a manufacturing process of the second storage capacitor 12 will be briefly described with reference to FIGS. In the drawing, since the portion constituting the TFT has the same structure as that of the first embodiment, detailed description is omitted, and the reference numerals used in the first embodiment are described only when necessary.
[0126]
FIG. 11 is a cross-sectional view taken along the broken line indicated by AA ′ in FIG.
[0127]
First, the third interlayer insulating film is formed according to Example 1 to obtain the state shown in FIG. Reference numeral 16 denotes a titanium film serving as a black matrix. Reference numeral 13 denotes a gate line extending from the gate electrode 307.
[0128]
In this state, a first interlayer insulating film 313, a second interlayer insulating film 315, and a third interlayer insulating film 317 are stacked on the gate line 13.
[0129]
Next, the second interlayer insulating film 315 and the third interlayer insulating film 317 on the gate line 13 are etched to form openings, and the pixel electrode 17 is formed. Reference numeral 18 denotes an edge portion of the pixel electrode disposed in the adjacent pixel region.
[0130]
At this time, the first storage capacitor 11 is formed between the black matrix 16 and the pixel electrode 17 via the third interlayer insulating film 317. On the gate line 13, the second storage capacitor 12 is formed between the gate line 13 and the pixel electrode 17 via the first interlayer insulating film 313.
[0131]
Since the second storage capacitor 12 has a large film thickness and the second interlayer insulating film 315 having a small relative dielectric constant is removed, only the first interlayer insulating film 313 can be used as an insulating layer. Therefore, a storage capacitor having a sufficient capacity can be formed by selecting a material having a high relative dielectric constant as the first interlayer insulating film 313 and reducing the film thickness.
[0132]
Further, as described in the second embodiment, this embodiment can also use the gate lines 13 and the data lines 14 as a black matrix. In this case, unlike the second embodiment, in addition to the first storage capacitor (capacity formed by the black matrix and the pixel electrode), the second storage capacitor (capacitance formed by the gate line and the pixel electrode) is provided. Sufficient capacity can be secured.
[0133]
As described above, according to the configuration shown in this embodiment, it is possible to realize a pixel region with a high aperture ratio while forming a storage capacitor having sufficient capacity. Furthermore, it goes without saying that further improvement is possible by using the special semiconductor layer shown in the third embodiment.
[0134]
Example 8
In this embodiment, the present invention is applied to an amorphous and super-multidomain AM-LCD. In this case, since an optically active material is added to a common TN material as a liquid crystal material, a rubbing process is unnecessary.
[0135]
Example 9
In this embodiment, the present invention is applied to a field effect mode liquid crystal display device. Such modes are classified into five types: twisted nematic (TN) mode, super twisted nematic (STN) mode, electric field controlled birefringence (ECB) mode, phase transition (PC) mode, and guest host (GH) mode. Can be considered.
[0136]
This operation mode has the most widespread use of the feature of low power consumption because of low power consumption and low driving voltage.
[0137]
Example 10
In this embodiment, the present invention is applied to a liquid crystal display device in a dynamic scattering mode. In this mode, in addition to the electric field effect, the light scattering state accompanying the turbulent motion caused by the presence of the ion additive doped in the liquid crystal is used for display.
[0138]
Example 11
This embodiment is an example in which the present invention is applied to a liquid crystal display device in a heat effect mode. In this mode, the phase transition due to the temperature of the liquid crystal is controlled by heating, and a change in optical characteristics based on the phase transition is used for display.
[0139]
【The invention's effect】
According to the invention disclosed in this specification, it is easy to form a storage capacitor by using a black matrix that has been conventionally used as a light shielding film. This is due to the following reasons.
[0140]
First, the parasitic capacitance formed between the gate line and the data line can be suppressed by forming the black matrix on the second interlayer insulating film having a small relative dielectric constant and a large film thickness. .
[0141]
Second, by forming a third interlayer insulating film made of a nitride film having a large relative dielectric constant and a small film thickness on the black matrix, the pixel electrode formed on the third interlayer insulating film is formed. This is because a storage capacitor having a sufficient capacity can be formed.
[0142]
As an effect of the above-described invention, since a conventional capacitor line can be eliminated and a storage capacitor can be formed using a black matrix, a liquid crystal display device with a high aperture ratio can be configured by utilizing the pixel area to the maximum extent possible. It becomes possible to do.
[0143]
[Brief description of the drawings]
FIG. 1 shows a structure of a pixel region in a liquid crystal display device.
FIG. 2 shows a structure of a pixel region in a liquid crystal display device.
FIG. 3 is a diagram showing an outline of a manufacturing process of a pixel TFT.
FIG. 4 is a diagram showing an outline of a manufacturing process of a pixel TFT.
FIG. 5 illustrates a structure of a pixel region in a liquid crystal display device.
FIG. 6 is a diagram schematically showing the structure of a semiconductor layer.
FIG. 7 is a diagram showing an outline of electrical characteristics of a semiconductor layer.
FIG. 8 is a diagram showing an outline of a band state of a semiconductor layer.
FIG. 9 is a diagram schematically showing the structure of a semiconductor layer.
FIG. 10 illustrates a structure of a pixel region in a liquid crystal display device.
FIG. 11 illustrates a cross-sectional structure of a pixel region in a liquid crystal display device.
[Explanation of symbols]
101 Gate line
102 capacity line
103 data lines
104 Pixel electrode
105 Semiconductor layer
106 Contact portion between semiconductor layer and data line
107 Contact portion between semiconductor layer and pixel electrode
108 Image display area
301 glass substrate
302 Island-like semiconductor layer
303 Silicon oxide film
304 Conductive coating
305 Porous anodic oxide film
306 Dense anodic oxide film
307 Gate electrode
308 Source area
309 drain region
310, 311 Low concentration impurity region
312 Channel formation region
313 First interlayer insulating film
314 Wiring electrode
315 Second interlayer insulating film (permeable polyimide)
316 Black Matrix
317 Third interlayer insulating film (silicon nitride film)
318 pixel electrode
319 Retention capacity
601 Island-like semiconductor layer
602 Channel formation area
603 to 605 Floating island region (ion implantation region)
901 Gate electrode
903 High resistance region
905 Floating island area (ion implantation area)
11 First holding capacity
12 Second holding capacity
13 Gate line
16 Black matrix
17 Pixel electrode

Claims (5)

A plurality of gate lines and data lines arranged in a matrix on the same substrate;
A pixel electrode disposed at each intersection of the gate line and the data line and a thin film transistor having a gate electrode connected to the pixel electrode and extending from the gate line;
A liquid crystal display device comprising:
A first interlayer insulating film covering the gate line and the gate electrode;
A second interlayer insulating film made of organic resin materials to be deposited over the first interlayer insulating film and the data line,
A black matrix formed on the second interlayer insulating film above the thin film transistor;
A third interlayer insulating film made of a nitride film formed on the second interlayer insulating film so as to cover the black matrix;
The pixel electrode formed in an opening provided in the second interlayer insulating film and the third interlayer insulating film on the gate line, and formed on the third interlayer insulating film;
Have
The surfaces of the second interlayer insulating film and the third interlayer insulating film are flat.
A first storage capacitor is formed between the black matrix and the pixel electrode through the third interlayer insulating film,
2. A liquid crystal display device according to claim 1, wherein a second storage capacitor is formed between the gate line and the pixel electrode via the first interlayer insulating film in the opening portion .   2. The liquid crystal according to claim 1, wherein the second interlayer insulating film has a thickness of 0.1 to 5.0 μm and the third interlayer insulating film has a thickness of 0.1 to 0.3 μm. Display device. According to claim 1 or claim 2, the liquid crystal, characterized in that AlN as _{nitride, AlN X O Y, Si 3} N 4, SiO X N one or more kinds selected from an insulating film represented by _Y is used Display device. A plurality of gate lines and data lines arranged in a matrix on the same substrate;
A pixel electrode disposed at each intersection of the gate line and the data line and a thin film transistor having a gate electrode connected to the pixel electrode and extending from the gate line;
In manufacturing a liquid crystal display device having
Forming a first interlayer insulating film covering the gate line and the gate electrode;
Covering the first interlayer insulating film and the data line, it becomes an organic resin materials, a step of surface forming the second interlayer insulating film having a flatness,
Forming a black matrix made of a metal film on the second interlayer insulating film above the thin film transistor;
On the second interlayer insulating film, forming a third interlayer insulating film made of a nitride film covering the black matrix and having a flat surface;
Forming an opening in the second and third interlayer insulating films on the gate line;
Forming a pixel electrode made of a transparent conductive film on the opening and the third interlayer insulating film;
Have
Forming a first storage capacitor through the third interlayer insulating film between the black matrix and the pixel electrode;
A method for manufacturing a liquid crystal display device, wherein a second storage capacitor is formed in the opening portion between the gate insulating film and the pixel electrode through the first interlayer insulating film. The step of forming the opening portion according to claim 4, wherein the step of forming the opening by etching away the third interlayer insulating film;
Etching the second interlayer insulating film exposed at the bottom of the opening with the third interlayer insulating film as a mask to form an opening;
A method for manufacturing a liquid crystal display device, comprising:

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