JPH09232385A - Method for joining electronic parts - Google Patents

Method for joining electronic parts

Info

Publication number
JPH09232385A
JPH09232385A JP8034549A JP3454996A JPH09232385A JP H09232385 A JPH09232385 A JP H09232385A JP 8034549 A JP8034549 A JP 8034549A JP 3454996 A JP3454996 A JP 3454996A JP H09232385 A JPH09232385 A JP H09232385A
Authority
JP
Japan
Prior art keywords
adhesive layer
conductor
electronic component
electrode
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8034549A
Other languages
Japanese (ja)
Other versions
JP3319269B2 (en
Inventor
Takatoshi Ishikawa
隆稔 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP03454996A priority Critical patent/JP3319269B2/en
Publication of JPH09232385A publication Critical patent/JPH09232385A/en
Application granted granted Critical
Publication of JP3319269B2 publication Critical patent/JP3319269B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of forming a bump and to inexpensively and easily join an electronic part to a substrate by forming an adhesive layer on the main face of the electronic part, temporarily fitting conductors to positions matched with electrodes in the adhesive layer and press-fixing the conductors to circuit patterns. SOLUTION: The electronic part 1 having the electrodes 2 on the main face are joined with the substrate 6 having the circuit patterns 7 facing the electrodes 2. The adhesive layer 3 is formed on the main face of the electronic part 1 and the conductors 5 are temporarily fitted to the positions matched with the electrodes 2 in the adhesive layer 3. Then, the conductors 5 are press-fixed to the circuit patterns 7, and the electrodes 2 and the circuit patterns 7 are electrically connected by the conductors 5. The anisotropic conductor is used as the adhesive layer 3, and the materials of gold or solder are used as the conductors 5, for example. The conductors 5 are adjusted to the positions of the electrodes 2 and they are held with the recessed parts 4a of a positioning table 4, and the conductors 5 are temporarily fitted to the adhesive layer 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、基板の回路パター
ンと電子部品の電極との間に導電体を介在させる電子部
品接合方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for joining electronic components in which a conductor is interposed between a circuit pattern on a substrate and an electrode of an electronic component.

【0002】[0002]

【従来の技術】近年、電子部品を基板に接合する方法と
して導電体によって形成されたバンプを用いる工法が実
施されている。
2. Description of the Related Art In recent years, a method of using a bump formed of a conductor has been carried out as a method of joining an electronic component to a substrate.

【0003】このものでは、まず電子部品の電極又は基
板の回路パターンのいずれか一方に、導電体を固着し、
バンプ(突出電極)を形成する。そして、このバンプを
接着剤や異方性導電体を介して他方の電極に電気的に接
合するものである。
In this structure, first, a conductor is fixed to either the electrode of the electronic component or the circuit pattern of the substrate,
A bump (protruding electrode) is formed. Then, this bump is electrically joined to the other electrode via an adhesive or an anisotropic conductor.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うにすると、バンプを形成するためだけの工程が必要に
なるためその分コスト高になるという問題点があった。
なお、バンプを形成するについて、比較的安価に行える
ものとして、ワイヤバンプ法が知られているが、この方
法でも、ワイヤの先端部に形成されるボールを1つずつ
電極に押し付け、その後ワイヤをボールから引きちぎる
過程が必要となるものであって、簡便に接合が行えると
は言い難い。
However, in this case, there is a problem in that the cost is increased accordingly because a step only for forming the bump is required.
The wire bump method is known as a relatively inexpensive method for forming bumps. In this method as well, the balls formed at the tip of the wire are pressed one by one against the electrodes, and then the wire is formed into a ball. It requires a process of tearing it off, and it is hard to say that joining can be performed easily.

【0005】そこで本発明は、バンプを形成する必要が
なくしかも低コストかつ簡単に電子部品を基板に接合で
きる電子部品接合方法を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an electronic component bonding method capable of easily bonding an electronic component to a substrate without forming bumps and at low cost.

【0006】[0006]

【課題を解決するための手段】本発明の電子部品接合方
法は、電子部品の主面に粘着層を形成するステップと、
粘着層のうち電極に符合する位置に導電体を仮付けする
ステップと導電体を回路パターンに圧着して導電体によ
り電極と回路パターンとを電気的に接続するステップと
を含む。
The method of joining electronic parts according to the present invention comprises a step of forming an adhesive layer on the main surface of an electronic part,
The method includes the steps of temporarily attaching a conductor to a position of the adhesive layer that corresponds to the electrode, and crimping the conductor to the circuit pattern to electrically connect the electrode and the circuit pattern with the conductor.

【0007】[0007]

【発明の実施の形態】請求項1の構成により、まず導電
体は電子部品の電極に半永久的に固着されるわけではな
く、単に粘着層に仮付けされるだけである。したがっ
て、バンプを全部電極に固着する従来技術に比べ、簡単
しかも短時間に済ませることができる。次に、導電体を
基板の回路パターンに圧着するが、このとき導電体は、
電子部品の電極と基板の回路パターンに挟まれており、
導電体を回路パターンに圧着すると、同時に導電体は電
子部品の電極にも圧着し、電極と回路パターンとを電気
的に接続することができる。
According to the first aspect of the present invention, first, the conductor is not semi-permanently fixed to the electrode of the electronic component, but is simply temporarily attached to the adhesive layer. Therefore, as compared with the conventional technique in which all the bumps are fixed to the electrodes, it can be completed easily and in a short time. Next, the conductor is pressure-bonded to the circuit pattern of the substrate, and at this time, the conductor is
It is sandwiched between the electrodes of electronic parts and the circuit pattern of the board,
When the conductor is pressure-bonded to the circuit pattern, the conductor is also pressure-bonded to the electrode of the electronic component at the same time, so that the electrode and the circuit pattern can be electrically connected.

【0008】次に図面を参照しながら、本発明の第1の
実施の形態における電子部品接合方法について説明す
る。
Next, an electronic component joining method according to the first embodiment of the present invention will be described with reference to the drawings.

【0009】図1は、本発明の第1の実施の形態におけ
る電子部品接合方法の工程説明図である。図1におい
て、1は集積回路を有する面(主面)に複数の電極2を
有する電子部品である。
FIG. 1 is a process explanatory view of an electronic component joining method according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an electronic component having a plurality of electrodes 2 on a surface (main surface) having an integrated circuit.

【0010】さてまず、電子部品1の主面に粘着層3を
形成する。本形態では、粘着層3として異方性導電体
(ACF)を用いたので、異方性導電体を電子部品1の
主面に貼付けるだけでよい(図1(a))。なお、3a
は接着剤であり、3bは接着剤3の中に散点状に存在
し、導電性を備えた粒子である。ここで、粘着層3とし
ては、異方性導電体の他、非導電性の接着剤を用いても
良い。また、後述するように導電体5を仮付けできるも
のであれば、ペースト状のものやテープ状のものなど種
々変更してよい。
First, the adhesive layer 3 is formed on the main surface of the electronic component 1. In this embodiment, since an anisotropic conductor (ACF) is used as the adhesive layer 3, it is only necessary to attach the anisotropic conductor to the main surface of the electronic component 1 (Fig. 1 (a)). 3a
Is an adhesive, and 3b is a particle which is present in the adhesive 3 in a dotted manner and has conductivity. Here, as the adhesive layer 3, a non-conductive adhesive may be used in addition to the anisotropic conductor. Further, as will be described later, if the conductor 5 can be temporarily attached, various changes such as a paste-like one and a tape-like one may be made.

【0011】次に、図1(b)に示すように、位置決め
テーブル4の凹部4aなどによって、導電体5を電極2
の位置に合わせて保持しておき、この導電体5を粘着層
3に仮付けする。ここでも、導電体5の上部を粘着層3
に貼付けさえすれば良く、従来技術(バンプ形成)に比
べ、格段に低コストかつ短時間で済ますことができる。
Next, as shown in FIG. 1B, the conductor 5 is connected to the electrode 2 by the recess 4a of the positioning table 4 or the like.
The electric conductor 5 is temporarily attached to the adhesive layer 3 in accordance with the position. Also here, the upper part of the conductor 5 is covered with the adhesive layer 3
It only needs to be attached to, and it can be done at a significantly lower cost and in a shorter time than the conventional technology (bump formation).

【0012】ここで導電体5としては、金あるいは半田
等の材料を用いることができ、その形状は、図示してい
るような球状でなくとも、直方体、立方体など種々変更
してよい。
Here, a material such as gold or solder can be used as the conductor 5, and the shape thereof may be variously changed, such as a rectangular parallelepiped or a cube, instead of the spherical shape shown in the drawing.

【0013】次に、本形態では、図1(c)に示すよう
に、基板6のうち回路パターン7側を上向きにし、この
面に上述したのと同様の粘着層3を貼付けておく。但
し、基板6上の粘着層3は省略しても良い。そして電子
部品1の電極2が基板6の電極7と符合するように位置
合わせし、導電体5を回路パターン7に圧着する。
Next, in this embodiment, as shown in FIG. 1 (c), the circuit pattern 7 side of the substrate 6 faces upward, and the same adhesive layer 3 as described above is attached to this surface. However, the adhesive layer 3 on the substrate 6 may be omitted. Then, the electrode 2 of the electronic component 1 is aligned with the electrode 7 of the substrate 6, and the conductor 5 is pressure-bonded to the circuit pattern 7.

【0014】このとき、図1(d)に示すように、導電
体5は電極2と回路パターン7に挟まれているから、こ
の圧着を行うと、導電体5は電極2及び回路パターン7
の双方に圧着し、電極2と回路パターン7は電気的に接
続される。この圧着時には、電子部品1を基板6側に加
圧すると共に、加熱を行う。
At this time, as shown in FIG. 1D, the conductor 5 is sandwiched between the electrode 2 and the circuit pattern 7. Therefore, when this crimping is performed, the conductor 5 becomes the electrode 2 and the circuit pattern 7.
The electrode 2 and the circuit pattern 7 are electrically connected to each other by crimping. At the time of this pressure bonding, the electronic component 1 is pressed against the substrate 6 side and heated.

【0015】またこれと平行して、粘着層3を硬化させ
る。硬化させる要領は、粘着層3の性質に応じて行う。
具体的には、粘着層3が紫外線硬化性樹脂であれば、紫
外線を照射すれば良いし、熱硬化性樹脂であれば加熱す
ると良い。要するに、粘着層3を硬化させることで、電
子部品1を基板6に固着できれば良い。
In parallel with this, the adhesive layer 3 is cured. The procedure for curing is performed according to the property of the adhesive layer 3.
Specifically, if the adhesive layer 3 is an ultraviolet curable resin, it may be irradiated with ultraviolet rays, and if it is a thermosetting resin, it may be heated. In short, it is sufficient that the electronic component 1 can be fixed to the substrate 6 by curing the adhesive layer 3.

【0016】次に図2を参照しながら、本発明の第2の
実施の形態における電子部品接合方法について説明す
る。本形態では、上述したものに対して、基板6側に導
電体5を仮付けする点が相違する。
Next, with reference to FIG. 2, an electronic component joining method according to the second embodiment of the present invention will be described. The present embodiment is different from the above-mentioned one in that the conductor 5 is temporarily attached to the substrate 6 side.

【0017】即ち、まず基板6のうち回路パターン7が
形成された面を上向きにして(図2(a))、粘着層3
を貼付けて形成する。次に、吸引路8aを有する吸着ヘ
ッド8により、導電体5を位置決めした上で吸着し(図
2(b))、粘着層3上へ移載する(図2(c))。こ
れにより、導電体5は粘着層3上に仮付けされる。
That is, first, with the surface of the substrate 6 on which the circuit pattern 7 is formed facing upward (FIG. 2A), the adhesive layer 3 is formed.
To be formed. Next, the conductor 5 is positioned and attracted by the suction head 8 having the suction path 8a (FIG. 2B), and is transferred onto the adhesive layer 3 (FIG. 2C). As a result, the conductor 5 is temporarily attached to the adhesive layer 3.

【0018】次に、電子部品1の主面に粘着層3を貼付
けて、図2(d)で示すように、導電体5を圧着する。
この圧着の要領は第1の実施の形態と同様である。な
お、本形態では、電子部品1への粘着層3の貼付けを省
略しても良い。
Next, the adhesive layer 3 is attached to the main surface of the electronic component 1, and the conductor 5 is pressure-bonded as shown in FIG. 2 (d).
The procedure of this crimping is similar to that of the first embodiment. In this embodiment, the sticking of the adhesive layer 3 to the electronic component 1 may be omitted.

【0019】[0019]

【発明の効果】本発明の電子部品接合方法は、電子部品
の主面に粘着層を形成するステップと、粘着層のうち電
極に符合する位置に導電体を仮付けするステップと導電
体を回路パターンに圧着して導電体により電極と回路パ
ターンとを電気的に接続するステップとを含むので、電
子部品の電極にわざわざバンプを形成する必要がなく、
それだけ低コストかつ短時間で電子部品の接合を行うこ
とができる。
According to the method of joining electronic components of the present invention, a step of forming an adhesive layer on the main surface of an electronic component, a step of temporarily attaching an electric conductor to a position of the adhesive layer that corresponds to an electrode, and a circuit of the electric conductor Since it includes the step of pressure-bonding to the pattern and electrically connecting the electrode and the circuit pattern by the conductor, it is not necessary to form a bump on the electrode of the electronic component.
As a result, the electronic components can be joined at low cost and in a short time.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)本発明の第1の実施の形態における電子
部品接合方法の工程説明図 (b)本発明の第1の実施の形態における電子部品接合
方法の工程説明図 (c)本発明の第1の実施の形態における電子部品接合
方法の工程説明図 (d)本発明の第1の実施の形態における電子部品接合
方法の工程説明図
FIG. 1A is a process explanatory diagram of an electronic component bonding method according to a first embodiment of the present invention. FIG. 1B is a process explanatory diagram of an electronic component bonding method according to a first embodiment of the present invention. Process explanatory drawing of the electronic component joining method in the 1st Embodiment of this invention (d) Process explanatory drawing of the electronic component joining method in the 1st Embodiment of this invention

【図2】(a)本発明の第2の実施の形態における電子
部品接合方法の工程説明図 (b)本発明の第2の実施の形態における電子部品接合
方法の工程説明図 (c)本発明の第2の実施の形態における電子部品接合
方法の工程説明図 (d)本発明の第2の実施の形態における電子部品接合
方法の工程説明図
2A is a process explanatory view of an electronic component bonding method according to a second embodiment of the present invention. FIG. 2B is a process explanatory diagram of an electronic component bonding method according to a second embodiment of the present invention. Process explanatory drawing of electronic component joining method in 2nd Embodiment of invention (d) Process explanatory drawing of electronic component joining method in 2nd Embodiment of this invention

【符号の説明】[Explanation of symbols]

1 電子部品 2 電極 3 粘着層 5 導電体 6 基板 7 回路パターン 1 Electronic Component 2 Electrode 3 Adhesive Layer 5 Conductor 6 Substrate 7 Circuit Pattern

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】主面に電極を有する電子部品と、前記電極
に対面する回路パターンを有する基板とを接合する電子
部品接合方法であって、 前記電子部品の主面に粘着層を形成するステップと、前
記粘着層のうち前記電極に符合する位置に導電体を仮付
けするステップと前記導電体を前記回路パターンに圧着
して前記導電体により前記電極と前記回路パターンとを
電気的に接続するステップとを含むことを特徴とする電
子部品接合方法。
1. A method of joining an electronic component having an electrode on a main surface and a substrate having a circuit pattern facing the electrode, the method comprising forming an adhesive layer on the main surface of the electronic component. And a step of temporarily attaching a conductor to the adhesive layer at a position corresponding to the electrode, and the conductor is pressure-bonded to the circuit pattern to electrically connect the electrode and the circuit pattern by the conductor. A method for joining electronic components, comprising:
【請求項2】前記基板には、粘着層が形成されているこ
とを特徴とする請求項1記載の電子部品接合方法。
2. The electronic component joining method according to claim 1, wherein an adhesive layer is formed on the substrate.
【請求項3】前記導電体を前記回路パターンに圧着する
際、又はその後に前記粘着層を硬化させるステップを含
むことを特徴とする請求項1、2記載の電子部品接合方
法。
3. The method for joining electronic components according to claim 1, further comprising the step of curing the adhesive layer when or after the conductor is pressure-bonded to the circuit pattern.
【請求項4】主面に電極を有する電子部品と、前記電極
に対面する回路パターンを有する基板とを接合する電子
部品接合方法であって、 前記基板に粘着層を形成するステップと、前記粘着層の
うち前記回路パターンに符合する位置に導電体を仮付け
するステップと、前記導電体に前記電子部品の電極を圧
着して前記導電体により前記電極と前記回路パターンと
を電気的に接続するステップとを含むことを特徴とする
電子部品接合方法。
4. A method of joining an electronic component having an electrode on its main surface and a substrate having a circuit pattern facing the electrode, the method comprising: forming an adhesive layer on the substrate; A step of temporarily attaching a conductor to a position of the layer corresponding to the circuit pattern; and an electrode of the electronic component is pressure-bonded to the conductor to electrically connect the electrode and the circuit pattern by the conductor. A method for joining electronic components, comprising:
【請求項5】前記電子部品の主面には、粘着層が形成さ
れていることを特徴とする請求項4記載の電子部品接合
方法。
5. The method of joining electronic parts according to claim 4, wherein an adhesive layer is formed on the main surface of the electronic parts.
【請求項6】前記導電体に前記電子部品の電極を圧着す
る際、又はその後に前記粘着層を硬化させるステップと
を含むことを特徴とする請求項4、5記載の電子部品接
合方法。
6. The method of joining electronic components according to claim 4, further comprising the step of curing the adhesive layer when or after pressure-bonding the electrodes of the electronic component to the conductor.
JP03454996A 1996-02-22 1996-02-22 Electronic component joining method Expired - Fee Related JP3319269B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03454996A JP3319269B2 (en) 1996-02-22 1996-02-22 Electronic component joining method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03454996A JP3319269B2 (en) 1996-02-22 1996-02-22 Electronic component joining method

Publications (2)

Publication Number Publication Date
JPH09232385A true JPH09232385A (en) 1997-09-05
JP3319269B2 JP3319269B2 (en) 2002-08-26

Family

ID=12417399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03454996A Expired - Fee Related JP3319269B2 (en) 1996-02-22 1996-02-22 Electronic component joining method

Country Status (1)

Country Link
JP (1) JP3319269B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231759A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
JP2002231758A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
JP2002231757A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
US20170294394A1 (en) * 2016-04-07 2017-10-12 Kabushiki Kaisha Toshiba Semiconductor device having a molecular bonding layer for bonding elements

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231759A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
JP2002231758A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
JP2002231757A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip
US20170294394A1 (en) * 2016-04-07 2017-10-12 Kabushiki Kaisha Toshiba Semiconductor device having a molecular bonding layer for bonding elements

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