JPH09213968A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the malfunction of a TFT due to a detective contact by controlling the dry etching rate of an insulating film as an inter-layer insulating film and tapering the sectional shape of a contact hole so that an angle of inclination is decreased successively towards a lowermost layer from an uppermost layer. SOLUTION: Inter-layer insulating films 114, 115 are formed in multilayer structure of two layers or more, the etching rate of an upper layer is made faster than a lower layer, and tapers, in which the angles of inclination are reduced successively towards a lowermost layer from the uppermost layer of the inter-layer insulating films 114, 115, can be formed. The hollowing-out sections of gate insulating films 103 and an anodic oxide film 107 such as the insides of circles can be removed by light etching, and the upper sectional shapes of contact holes can be improved. Accordingly, the sectional shapes of the contact holes are enhanced largely, the yield of the manufacture of a TFT and the reliability of wiring contacts are elevated, and reliability for a prolonged term of a device or a display system can be advanced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a method for manufacturing a semiconductor device using a thin film semiconductor having crystallinity. In particular, it relates to a method for manufacturing a planar thin film transistor.

[0002]

2. Description of the Related Art Recently, a technique for producing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix liquid crystal display devices has increased.

An active matrix type liquid crystal display device is
A TFT is arranged in each of the millions of pixels arranged in a matrix, and the electric charge that flows in and out of each pixel electrode is T
It is controlled by the switching function of the FT.

Therefore, if one TFT does not operate, the pixel electrode connected to it loses its function as a display element. This causes so-called point defects. For example, in the case of a normally black liquid crystal display device, point defects appear as black dots when displaying white, which is extremely detrimental to the appearance.

Further, it is required to integrate a circuit for driving the pixel electrode display TFT (called a peripheral drive circuit) with the TFT on the same glass substrate.

In this case, if the driving TFT does not operate, all the TFTs to which the driving voltage is applied do not function as a switching element. This causes so-called line defects, which is a fatal obstacle for a liquid crystal display device.

Therefore, in the active matrix type liquid crystal display device, millions of TFTs must be able to maintain normal and stable operation for a long period of time.

However, at present, it is extremely difficult to completely eliminate point defects and line defects. One of the causes is contact failure.

A contact failure is an operation failure that occurs when a connection failure (hereinafter referred to as a contact) between a wiring electrode and a TFT causes a connection failure. In particular, in the planar type TFT, the wiring electrode and the TFT are electrically connected to each other through a thin opening hole (contact hole), and thus contact failure is a serious problem.

The contact failure is the main cause of the early deterioration of semiconductor device characteristics, and the deterioration is accelerated especially when a large current flows or at high temperature operation. Therefore, it is said that the reliability of the contact determines the reliability of the semiconductor device.

Generally, in the case of a pixel display area in an active matrix type liquid crystal display device, the gate electrode is directly drawn out of the pixel display area, so that there is no contact. That is, the contact with the pixel electrode is very important for the reliability of the liquid crystal display device.

In the case of a peripheral drive circuit, there are several hundred thousand to several million contacts. In particular, the presence of the contact of the gate electrode and the rise in temperature due to the large current operation mean that the contact is required to have a reliability higher than that of the pixel display area.

The causes of the contact failure can be roughly classified into three. One of them is that the conductive film forming the wiring electrode and the semiconductor film forming the source / drain of the TFT are not in contact with each other by ohmic contact.

This is because an insulating film, for example, a metal oxide or the like is formed on the joint surface. Further, the state near the surface of the semiconductor film (impurity concentration, defect level density, cleanliness, etc.) greatly affects the contact performance.

The second cause is that the coverage of the conductive film forming the wiring electrode is poor and the wiring is broken in the contact hole. In this case, it is necessary to improve the film forming method and film forming conditions of the wiring electrodes.

The third cause is disconnection of the wiring electrode due to the sectional shape of the contact hole. The cross-sectional shape of the contact hole strongly depends on the etching conditions of the insulator (SiN, SiO ₂ etc.) covered with the contact portion.

In order to form a contact with good coverage, it is desirable to have a gradually changing cross-sectional shape (called a taper). In addition, overetching of the lower layer film, which is often seen in the case of a multi-layer interlayer insulating film, significantly deteriorates the coverage.

[0018]

DISCLOSURE OF THE INVENTION The invention disclosed in the present specification improves the cross-sectional shape of a contact hole that serves as an electrical connection path between a wiring electrode and a TFT, and reduces defective operation of the TFT due to defective contact. This is an issue.

That is, it is an object to improve the reliability of the contact and improve the long-term reliability as a device or a liquid crystal display device. Another object is to improve the yield of the manufacturing process by eliminating point defects and line defects.

[0020]

One of the inventions disclosed in the present specification is to provide a thin film transistor having a gate portion having a gate electrode made of an anodizable material and a source portion or a drain portion made of a semiconductor. In the manufacturing process, the step of laminating at least two layers of the insulating film having the same main component so as to cover the gate part, the source part and the drain part, and the step of opening the insulating film by dry etching, A step of forming a taper such that the inclination angle is gradually decreased from the uppermost layer to the lowermost layer.

In the above invention, the cross-sectional shape of the contact hole is tapered so that the inclination angle becomes gradually smaller from the uppermost layer to the lowermost layer by controlling the dry etching rate of the insulating film serving as the interlayer insulating film. It is characterized by The taper angle is defined by the accuracy indicated by α and β in FIG.

Since the insulating film only needs to have a function as an interlayer insulating film, a silicon oxide film, a silicon nitride film,
Various materials such as organic resins can be used.

At this time, a material which can easily control the dry etching rate is desirable. This is because a desired taper can be easily formed by making the etching rate of the upper layer higher than that of the lower layer.

In general, when a contact hole is formed by dry etching, a reactive ion etching method (RIE method) is used.

However, the drawback of the RIE method is that if the time when etching is completed (called the end point) is not clear, the conductive thin film to be contacted is also dug.

In the case of the RIE method, the end point is generally detected by plasma emission measurement. This is done by monitoring specific radicals and ions generated during etching.

In this case, for example, in the etching of the interlayer insulating film made of a silicon oxide film formed on the gate insulating film made of a silicon oxide film, the emission species to be monitored are confused and it is difficult to confirm the end point.

Considering the above, it is necessary to select the insulating film used as the interlayer insulating film in consideration of the structure of the TFT to be manufactured.

Another aspect of the present invention disclosed in the present specification is a step of manufacturing a thin film transistor having a gate portion having a gate electrode made of an anodizable material and a source portion or a drain portion made of a semiconductor. A step of forming an insulating film covering the source part and the drain part, forming a hole in the insulating film by a dry etching method, etching a thin film in contact with the lower surface of the insulating film, and the step of: And a step of light etching the open hole formed by.

The above invention is characterized in that the contact hole is expanded by light etching and a taper is formed on the upper portion of the contact hole.

When the thin film in contact with the lower surface of the insulating film is wet-etched, it is isotropically etched to form a hole around the insulating film under the insulating film. At that time, the portion that wraps around the bottom becomes a hollow, which later causes a disconnection of the wiring electrode.

According to the present invention, by performing the light etching, the inner wall surface of the contact hole can be expanded by the amount of the engraved portion, and the engraved portion can be eliminated.

At this time, the gas composition ratio at the time of light etching is set so that the amount of O ₂ added is larger than the gas composition ratio at the time of forming the contact hole.

This is because the resist mask that forms the open area of the contact hole is receded at the same time as eliminating the engraved portion, and the lip of the contact hole (in this specification, the outer frame of the contact hole inlet is called a lip). ) To round the corners.

That is, by this light etching, a contact hole having a cross-sectional shape that drops along a gentle curve can be obtained. Therefore, the coverage of the wiring electrode becomes extremely good.

[0036]

【Example】

Example 1 A thin film transistor (TF) utilizing the present invention
An example of the manufacturing process of T) is shown in FIG.

First, a glass substrate 101 having an insulating film such as a silicon oxide film on its surface is prepared. An amorphous silicon film (not shown) having a thickness of 500 Å is formed thereon by a plasma CVD method or a low pressure thermal CVD method and crystallized by an appropriate crystallization method. This crystallization may be performed by heating or irradiation with laser light.

Next, the crystalline silicon film obtained by crystallizing the amorphous silicon film is patterned to form an island-shaped semiconductor layer 102 which constitutes an active layer.

A silicon oxide film 103 which later functions as a gate insulating film is formed thereon with a thickness of 1200 Å. The silicon oxide film 103 may be formed by a plasma CVD method or a low pressure thermal CVD method.

Next, a film 104 made of aluminum or a material containing aluminum as its main component is formed to a thickness of 4000 Å. This aluminum film 104 later functions as a gate electrode. Of course, in addition to aluminum, anodizable materials such as tantalum and niobium may be used.

Next, in the electrolytic solution, the aluminum film 104 is formed.
Is used as an anode to perform anodic oxidation. As the electrolytic solution, 3
% Ethylene glycol solution of tartaric acid is neutralized with aqueous ammonia and adjusted to PH = 6.92.
In addition, using platinum as a cathode, the formation current is 5 mA, and the ultimate voltage is 10 mA.
Process as V.

The dense anodic oxide film 10 thus formed
5 has the effect of increasing the adhesion to the photoresist later. Further, by controlling the voltage application time, the anodic oxide film 1
The thickness of 05 can be controlled. (Fig. 1 (A))

When the state of FIG. 1A is obtained in this way, the aluminum film 104 is patterned to form a gate electrode (not shown).

Next, a second anodic oxidation is performed to form a porous anodic oxide film 106. The electrolytic solution was a 3% oxalic acid aqueous solution, and the formation current was 2 to 3 mA with platinum as the cathode.
It is processed as an ultimate voltage of 8V.

At this time, anodization proceeds in a direction parallel to the substrate. Further, the length of the porous anodic oxide film 106 can be controlled by controlling the voltage application time.

Further, after removing the photoresist with a dedicated stripping solution, anodic oxidation is performed for the third time to obtain the state shown in FIG. 1 (B).

At this time, the electrolytic solution was prepared by neutralizing a 3% ethylene glycol solution of tartaric acid with aqueous ammonia to obtain PH =
Use the one adjusted to 6.92. Then, the platinum is used as a cathode and the formation current is 5 to 6 mA, and the ultimate voltage is 100 V.

The anodic oxide film 107 formed at this time is extremely dense and strong. Therefore, the gate electrode 108 is prevented from being damaged in a post process such as a doping process.
Has the effect of protecting.

Further, since the strong anodic oxide film 107 is hard to be etched, there is a problem that the etching time becomes long when the contact hole is opened. Therefore, 1000Å
The following thicknesses are desirable.

Next, impurities are implanted into the island-shaped semiconductor layer 102 by the ion doping method. For example, when an N-channel TFT is manufactured, P (phosphorus) may be used as an impurity.

First, in the state of FIG. 1B, the first ion doping is performed. The implantation of P (phosphorus) is performed at an acceleration voltage of 60 to 90 kV and a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm.
Perform in ² . In this embodiment, the acceleration voltage is 80 kV and the dose is 1 × 10 ¹⁵ atoms / cm ² .

Then, the gate electrode 108 and the porous anodic oxide film 106 serve as a mask, and the regions 109 and 110 to be source / drain later are formed in a self-aligned manner.

Next, as shown in FIG. 1C, the porous anodic oxide film 106 is removed and a second doping is performed. The second injection of P (phosphorus) is performed at an accelerating voltage of 60 to
It is performed at 90 kV and a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² . In this embodiment, the accelerating voltage is 80 kV and the dose is 1 × 1.
It is set to 0 ¹⁴ atoms / cm ² .

Then, the gate electrode 108 serves as a mask, and the low-concentration impurity regions 111 and 112 having a lower impurity concentration than the source region 109 and the drain region 110 are formed in a self-aligned manner.

At the same time, since no impurities are implanted right under the gate electrode 108, the region 113 functioning as the channel of the TFT is formed in a self-aligned manner.

The low concentration impurity region (or LDD region) 112 thus formed is the channel region 113.
This has the effect of suppressing the formation of a high electric field between the drain region 110 and the drain region 110.

Next, irradiation with KrF excimer laser light and thermal annealing are performed. In this embodiment, the energy density of laser light is 250 to 300 mJ / cm ² , and the thermal anneal is 300
Perform at ~ 450 ° C for 1 hr.

By this step, the crystallinity of the island-shaped semiconductor layer 102 damaged by the ion doping step can be improved.

Next, as shown in FIG. 1D, the interlayer insulating films 114 and 115 having a two-layer structure are formed by plasma CVD.
It is formed by the method. In this embodiment, this interlayer insulating film 11
Reference numerals 4 and 115 are made of silicon nitride films having different composition ratios.

At this time, the second interlayer insulating film 115 has 1
A silicon nitride film having a composition ratio such that the dry etching rate is faster than that of the second interlayer insulating film 114 is used.
For example, the pressure of the film forming gas or the film forming temperature may be increased, or the RF
By lowering the power, a film with a high etching rate can be formed.

Specifically, the film formation temperature of the first layer is 250 ° C.
If the film forming temperature of the second layer is 350 ° C., the dry etching rate of the second layer is about twice as fast as that of the first layer.
Further, the pressure of the film forming gas for the first layer is set to 0.3 torr, and the pressure of the film forming gas for the second layer is set to 0.7 torr. In this case, 2
The dry etching rate of the first layer is about 1.5 times faster than that of the first layer.

This is because in the shape of the contact hole shown in FIG. 3, the inclination angle α of the first interlayer insulating film 114 is smaller than the inclination angle β of the second interlayer insulating film 115. It is a necessary element.

The total film thickness of the first and second interlayer insulating films is set to be 1 to 3 times the film thickness of the gate electrode 108. This is to prevent the leakage current through the interlayer insulating film by improving the coverage of the interlayer insulating film.

However, the thickness of the first interlayer insulating film 114 is preferably 1/3 or less of the total film thickness. If it is more than that, the inclination angle α becomes large, which causes a problem in the subsequent light etching process.

Next, a resist mask 201 shown in FIG. 2A is formed, and a contact hole is formed by a dry etching method. The composition ratio of the etching gas is CF ₄ :
O ₂ = 40: 60.

The etching ends 150 seconds after the end point is confirmed. As shown in FIG. 5, the end point is detected as the time when the signal intensity of nitrogen ions becomes constant. The signal intensity of nitrogen ions in the first layer is high because the first layer is denser than the second layer.

At this time, the source / drain contact portion 2
In Nos. 02 and 203, the gate insulating film 103 functions as a stopper film for dry etching. Also, the gate electrode section 2
In 04, the anodic oxide film 107 functions as a stopper film for dry etching.

Furthermore, since the second-layer interlayer insulating film 115 has a faster etching rate than the first-layer interlayer insulating film 114,
A taper is formed as shown in FIG.

Next, the gate insulating film 103 on the bottom surface of the contact hole is etched using buffer hydrofluoric acid,
The source / drain portions 109 and 110 contact holes are completed.

Then, the anodic oxide film 107 is etched by using a chromium mixed acid solution having a composition in which chromic acid, acetic acid, phosphoric acid and nitric acid are mixed to complete the contact hole of the gate electrode portion 204.

As described above, if the gate insulating film 103 is etched first, the anodic oxide film 107 is excellent in buffer hydrofluoric acid resistance, so that the gate electrode 108 can be protected. The chromium mixed acid solution is used in the source region 10
9. The surface of the drain region 110 is hardly etched.

As described above, the state of FIG. 2B is obtained. However, in wet etching using buffer hydrofluoric acid or chromic acid mixture, since the etching proceeds isotropically, a cut-out portion as shown in a circle in FIG. 2B is formed.

Therefore, the interlayer insulating film is made to recede by light etching so as to be in a state where there is no engraved portion as shown in FIG. 2 (C). At this time, the first interlayer insulating film 114 is more easily retracted as the inclination angle α is smaller.

This light etching is performed by a dry etching method, and the composition ratio of the etching gas is CF ₄ : O ₂ =
25: 75. With this composition ratio, since the selection ratio of silicon nitride and silicon is 10 or more, the source region 1
09, the surface of the drain region 110 is hardly etched.

Since this light etching is performed with a gas composition ratio with a high O ₂ addition rate, the resist mask 20 is used.
1 also retreats at the same time. Therefore, as shown in the circle of FIG. 4, the cross-sectional shape at the edge of the contact hole becomes a curve with the corners etched.

After the formation of the contact holes is completed, the wiring electrodes 205, 206, 207 are formed and an annealing treatment is performed at 350 ° C. for 2 hours in a hydrogen atmosphere.

Through the above steps, a thin film transistor as shown in FIG. 2D is manufactured.

[Embodiment 2] This embodiment is an example in which the invention disclosed in this specification is applied to an IC process using a single crystal silicon wafer. Specifically, an example of manufacturing a MOS transistor using a silicon wafer will be shown.

6 to 8 show the manufacturing process of this embodiment.
First, as shown in FIG. 6A, a thermal oxide film and a silicon nitride film are laminated on an N-type single crystal silicon wafer 601, and then patterned to form a thermal oxide film 602 and a silicon nitride film 603. A pattern made of a film is formed.

Next, field oxide films 604 and 605 are formed by a selective thermal oxidation method. Thus, FIG. 6 (A)
The state shown in is obtained.

Next, the thermal oxide film 602 and the silicon nitride film 603 are removed, and the thermal oxide film 606 is formed again by the thermal oxidation method. This thermal oxide film 606 constitutes a gate insulating film.

Next, the gate electrode 607 is formed of a suitable metal material,
Alternatively, it is formed using a silicide material or a semiconductor material. After forming the gate electrode 607, doping of impurities for forming the source / drain regions is performed.

Here, B (boron) doping is performed by an ion implantation method in order to manufacture a P-channel type MOS transistor. N-channel type MOS
If a type transistor is to be manufactured, P (phosphorus) doping may be performed.

After the above doping, heat treatment is performed to activate the implanted impurities and anneal damage to the semiconductor layer during the doping.

Thus, as shown in FIG. 6B, the P-type source region 608 and the drain region 609 are formed in a self-aligned manner.

Next, silicon nitride films 610 and 611 are formed as interlayer insulating films. Also in this case, the same method as in Example 1 is used to obtain a film quality such that the etching rate of the silicon nitride film 611 is faster than that of 610.

Thus, the state shown in FIG. 6C is obtained. Next, as shown in FIG. 7A, a resist mask 612 is arranged, and the contact hole 6 is formed by a dry etching method.
13 and 614 are formed.

Thus, the state shown in FIG. 7A is obtained. At this time, the gate insulating film 606 made of a thermal oxide film functions as an etching stopper.

Next, using a wet etching method, 61
Contact holes 5 and 616 are formed.

Thus, the state shown in FIG. 7B is obtained. At this time, isotropic etching by the wet etching method progresses, so that the contact holes 615 and 616 expand the bottoms of the contact holes 613 and 614.

Next, the interlayer insulating film and the resist mask are set back by light dry etching. The dry etching here is performed using a mixture of CF ₄ and O ₂ . The reason for mixing oxygen here is to retract the resist mask.

In this way, it is possible to obtain a contact having such a cross-sectional shape as shown in FIG.

After obtaining the state shown in FIG. 8A, a source electrode 619 and a drain electrode 620 are formed. Thus M
The OS type transistor is completed.

[0094]

According to the present invention, since the interlayer insulating film has a multi-layer structure of two or more layers and the etching rate of the upper layer is higher than that of the lower layer, the inclination angle is sequentially increased from the uppermost layer to the lowermost layer of the interlayer insulating film. The taper can be formed so that

Further, by performing the light etching, it is possible to eliminate the hollowed-out portions of the gate insulating film 103 and the anodic oxide film 107 as shown in the circle of FIG. 2B. further,
The upper cross-sectional shape of the contact hole can also be improved.

Due to the above effects, the cross-sectional shape of the contact hole is greatly improved, and the yield of TFT fabrication and the reliability of the wiring contact are improved. In addition, the long-term reliability of the device or the display system can be improved accordingly.

[Brief description of drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 is a view showing a sectional shape of a contact hole.

FIG. 4 is a diagram showing a cross-sectional shape of a contact hole.

FIG. 5 is a diagram showing end points during dry etching.

FIG. 6 is a diagram showing an IC process utilizing the invention.

FIG. 7 is a diagram showing an IC process using the invention.

FIG. 8 is a diagram showing an IC process utilizing the invention.

[Explanation of symbols]

 Reference Signs List 101 glass substrate 102 island-shaped semiconductor layer 103 silicon oxide film 104 aluminum film 105 dense anodic oxide film 106 porous anodic oxide film 107 strong anodic oxide film 108 gate electrode 109 source region 110 drain region 111 low concentration impurity region 112 Low-concentration impurity region 113 Channel region 114 First layer interlayer insulating film 115 Second layer interlayer insulating film 201 Resist mask 202 Source contact part 203 Drain contact part 204 Gate contact part 205 Wiring electrode 206 Wiring electrode 207 Wiring electrode

Claims (12)

[Claims] 1. A method of manufacturing a thin film transistor comprising: a gate portion having a gate electrode made of an anodizable material; and a source portion or a drain portion made of a semiconductor, covering the gate portion, the source portion and the drain portion. A step of laminating the insulating coating in at least two layers, and forming a taper so that the inclination angle becomes gradually smaller from the uppermost layer to the lowermost layer of the insulating coating when the insulating coating is opened by dry etching. A method of manufacturing a semiconductor device, comprising: 2. A thin film transistor having a gate portion having a gate electrode made of an anodizable material, and a source portion or a drain portion made of a semiconductor, the insulating film covering the gate portion, the source portion and the drain portion. A step of forming a hole in the insulating film by a dry etching method, a step of etching a thin film in contact with the lower surface of the insulating film, and a step of light etching the hole formed in the step. A method for manufacturing a semiconductor device, comprising: 3. A thin film transistor comprising: a gate portion having a gate electrode made of an anodizable material; and a source portion or a drain portion made of a semiconductor, wherein the gate portion, the source portion and the drain portion are covered with a main component. A step of laminating at least two layers of the same insulating film, and, when opening the insulating film by dry etching, taper so that the inclination angle becomes gradually smaller from the uppermost layer to the lowermost layer of the insulating film. A method for manufacturing a semiconductor device, comprising: a forming step; a step of etching a thin film in contact with the lower surface of the insulating coating; and a step of light etching the hole formed in the step. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film having the same main component as the upper layer has a higher dry etching rate. 5. A method according to claim 2 or claim 3, the gas composition ratio at the time of light etching, the insulating film that higher O ₂ addition rate than the gas composition ratio at the time of allowed to opening by dry etching, A method for manufacturing a semiconductor device, comprising: 6. The method for manufacturing a semiconductor device according to claim 2, wherein the cross-sectional shape at the edge of the contact hole has a curve by light etching. 7. A thin film transistor having a gate portion having a gate electrode made of an anodizable material and a source portion or a drain portion made of a semiconductor, the silicon nitride film covering the gate portion, the source portion and the drain portion. And a step of forming a taper such that when the silicon nitride film is opened by dry etching, the inclination angle becomes gradually smaller from the uppermost layer to the lowermost layer of the silicon nitride film. A step of etching a silicon oxide film in contact with the lower surface of the silicon nitride film in the source part and the drain part, and a step of etching an anodized aluminum oxide film in contact with the lower surface of the silicon nitride film in the gate part after the step, A step of performing light etching on the hole formed by the above step, And a method for manufacturing a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the upper layer of the silicon nitride film has a faster dry etching rate. 9. The gas composition ratio in light etching according to claim 7, wherein the O ₂ addition rate is higher than the gas composition ratio in opening the silicon nitride film by dry etching. Manufacturing method of semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the thickness of the silicon nitride film is 1 to 3 times that of the gate electrode. 11. The method of manufacturing a semiconductor device according to claim 7, wherein the cross-sectional shape at the edge of the contact hole has a curve by light etching. 12. A thin film transistor having a gate portion having a gate electrode made of an anodizable material and a source portion or a drain portion made of a semiconductor, the silicon nitride film covering the gate portion, the source portion and the drain portion. And a step of laminating the silicon nitride film as a single layer or a multi-layer, and in forming the silicon nitride film by dry etching, a silicon oxide film is used as a stopper film in the source portion and the drain portion, and an anodized aluminum film is used as a stopper film in the gate portion. A method for manufacturing a semiconductor device, comprising: