JPH10116992A - Thin film semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the formation of the contact of a gate electrode in a thin film transistor having offset. SOLUTION: An anode oxide film is prevented from being formed on a gate electrode by forming a barrier layer on the gate electrode before performing the first anodizing, and after formation of a source region 202/a drain region 203, and the first sidewall oxide film and the barrier layer are removed, and a thin anodized film 220 is made on the gate electrode, whereby the formation of a contact hole is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
A semiconductor device having an insulated gate structure using a non-single-crystal film provided on an insulating substrate such as glass or quartz or an SOI (Silicon On Insulator) having an insulating layer provided on a single crystal, for example, a thin film transistor (TFT) And a thin film diode (TFD) or a thin film integrated circuit using the same, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display), and a method of manufacturing the same. Particularly, the maximum process temperature is 700 ° C. The present invention relates to a structure of a thin film transistor formed by a low-temperature process described below and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor using a silicon film has been known. This is a technique for forming a thin film transistor using a silicon film formed on a glass substrate or a quartz substrate.

[0003] Glass substrates and quartz substrates are used for
This is because a thin film transistor is used for an active matrix display device. Conventionally, a thin film transistor is formed using an amorphous silicon film. However, in order to obtain higher performance, it has been attempted to manufacture a thin film transistor using a silicon film having crystallinity (crystalline silicon film). ing.

[0004] A thin film transistor using a crystalline silicon film has a higher mobility than a transistor using an amorphous silicon film, and thus can perform a high-speed operation of two digits or more.

However, while a high ON current can be obtained, there is a problem of a high leakage current generated by a reverse voltage. As a method for solving this problem, a technique described in Japanese Patent Application Laid-Open No. 7-226515 is known. FIG. 1 shows a structure of a thin film transistor using this technique.

A polysilicon thin film is formed on an insulating substrate 100. The polysilicon thin film has a source region 102 / drain region 103 doped with impurities at a high concentration and a channel region 1 between the source / drain regions.
01, and offset regions 115 and 116 are formed between the channel region and the source / drain region.

A gate insulating film 10 is formed on the polysilicon thin film.
4 are formed. Further, a gate electrode 105 made of metal is formed on the gate insulating film 104 and above the channel region 101. Above the offset regions 115 and 116, a metal oxide film 122 is formed adjacent to the side wall of the gate electrode 105. And
Barrier layer 1 is formed on gate electrode 105 and metal oxide film 122.
06 is formed.

Further, an interlayer insulating film 108 is formed so as to cover the whole.
Are formed. Further, the source region 102 and the metal wiring 125 are connected, and the drain region 103 and the metal wiring 126 are connected. The metal wiring 1 is formed on the gate electrode 105.
27 are connected.

In the above configuration, the width of the metal oxide film 122 and the width of the offset regions 115 and 116 are substantially equal. The method for forming the metal oxide film 122 is as follows.
Is an anodic oxidation method using an aqueous solution of ammonium tartrate (3% by volume) as an electrolytic solution on the side wall of.

When an anodic oxide film is used instead of the barrier layer, the upper anodic oxide film is formed simultaneously with the side wall oxide film. Therefore, the thickness of the anodic oxide film formed on the upper portion has the same thickness as that of the sidewall oxide film which is thickened to form the offset.

[0011]

In the prior art, in the step of forming an anodic oxide film on a gate electrode, anodic oxidation is performed using an aqueous solution of ammonium tartrate (3% by volume) as an electrolytic solution. When anodic oxidation is performed under the conditions using this electric field solution, a dense metal oxide film is formed.

The graph in FIG. 8 shows that the aluminum gate electrode is increased in anodic oxidation voltage to 40, 60, and 80 V for 16 minutes using a 3% by volume aqueous solution of ammonium tartrate, and then the voltage is increased to 40, 60. , And 80 V, the horizontal axis represents the anodic oxidation time, and the vertical axis represents the anodic oxidation film thickness.

As shown in the graph of FIG.
Even if anodizing is performed for 0 minutes, only an anodic oxide film having a thickness of 1000 ° can be obtained. This is because the thickness of the metal oxide film is almost determined by the anodic oxidation voltage in the anodic oxidation using an aqueous solution of ammonium tartrate as the electrolytic solution. That is, it takes a high voltage and time to form the metal oxide film to a thickness of 0.1 to 2 μm.

Further, since a high voltage is required, a problem such as peeling of a barrier layer arises. And, due to high voltage and large current, impurities slightly enter into the electrolytic solution due to aging or the like, and the current value and voltage fluctuate, and the reproducibility of the thickness of the anodic oxide film deteriorates. Variations occur in transistor characteristics. Therefore, even if it can be used at the laboratory level, it is not suitable for factory production, etc., and is not industrially useful.

When an anodic oxide film is used as the barrier layer, the upper anodic oxide film and the sidewall oxide film have the same thickness.
Therefore, when forming a contact hole in the upper anodic oxide film in order to make contact with the gate electrode, the upper anodic oxide film is compared with the gate electrode and the gate insulating film, and as an etchant having a selective etch rate ratio, the The use of harmful chromic acids, which can cause harm, was forced.

An object of the invention disclosed in this specification is to provide a thin-film semiconductor device which solves the above problems and a method for manufacturing the same.

[0017]

According to the invention disclosed in this specification, a source region and a drain region are formed on a substrate having an insulating surface, and the source region and the drain region are formed between the source region and the drain region. A channel region, an offset region is formed between the source region and the channel region, and between the drain region and the channel region, adjacent to the channel region, and at least a gate insulation formed on the channel region A film, a gate electrode formed on the gate insulating film above the channel region,
A thin film semiconductor device comprising: a side wall oxide film layer formed by oxidizing the electrode on the side wall of the gate electrode; and an upper oxide film layer formed by oxidizing the electrode on the gate electrode. The offset region extends outside the sidewall oxide film, and the sidewall oxide film is thicker than the upper oxide film.

In another aspect of the invention, a first step of forming a non-single-crystal film on a substrate having an insulating surface, a second step of forming a conductive film on the non-single-crystal film, A third step of forming a barrier layer on the conductive film, a fourth step of patterning the conductive film and the barrier layer, and oxidizing a sidewall of the conductive film to form a primary sidewall oxide film A fifth step, a sixth step of forming a second side wall oxide film inside the conductive film adjacent to the first side wall oxide film, and
A seventh step of removing the next sidewall oxide film, an eighth step of removing the barrier layer, and a step of doping impurities between after the fourth step and before the seventh step. It is characterized by:

In another aspect of the invention, a first step of forming a non-single-crystal film on a substrate having an insulating surface, a second step of forming a conductive film on the non-single-crystal film, A third step of forming a barrier layer on the conductive film, a fourth step of patterning the conductive film and the barrier layer, and oxidizing a sidewall of the conductive film to form a primary sidewall oxide film A fifth step, a sixth step of forming a second side wall oxide film inside the conductive film adjacent to the first side wall oxide film, and
A seventh step of removing the next sidewall oxide film, an eighth step of removing the barrier layer, a ninth step of forming an anodic oxide film on the conductive film, and a fourth step after the fourth step. And a step of doping impurities before the step (7).

Examples of the material of the barrier layer include silicon nitride, silicon oxide, silicon carbide, a film containing carbon as a main component, TiN,
BN, a conductor different from the gate electrode, for example, W, Ti, T
a, Au, Ag, Pt, Cr, Mo, Pd, Ar, C
o, Zr and the like.

In this specification, an insulating substrate refers to a glass substrate, a quartz substrate, a substrate having an insulating layer formed on a semiconductor surface, or the like.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the configuration of a preferred embodiment of the invention disclosed in this specification. A substrate 200 having an insulating surface and a source region 202 on the substrate
A drain region 203, a channel region 201 between the source region and the drain region, an offset region 215 between the channel region and the source region 202,
An offset region 216 is provided between the channel region and the drain region 203, and the offset regions 215 and 216 are arranged close to the channel region 201, and have a gate insulating film 204 and a gate electrode 205 on the channel region, It has a sidewall oxide layer 222 on the side of the electrode and an upper oxide layer 220 above the gate electrode.

As shown in FIG. 2, the offset regions 215 and 216 extend outside the sidewall oxide film layer 222. The upper oxide layer 220 is formed on the side wall oxide layer 22.
Film thickness is smaller than 2.

Then, an interlayer insulating film 208 is formed, and wiring electrodes 225 and 22 for operating the thin film semiconductor device are formed.
6, 227 are connected to the source, drain and channel regions. The structure shown in FIG. 2 is formed by the steps shown in FIGS.

First, as shown in FIG. 4A, an active layer 430 and a gate insulating film 404 are formed on a glass substrate 400. Next, an aluminum film 409 serving as a gate electrode is formed over the gate insulating film 404. On the aluminum film 409, a barrier layer 406 made of silicon nitride is formed. Thereafter, as shown in FIG. 4B, the side wall of the aluminum film 409 serving as a gate electrode is subjected to anodic oxidation using an oxalic acid aqueous solution. Thus, the first sidewall oxide film 421 is formed to a thickness of 0.3 to 2.0 μm, preferably 0.7 μm.

FIG. 7 is a graph showing anodic oxidation using an oxalic acid aqueous solution. The graph in FIG. 7 shows the anodic oxidation film when the anodizing time when the aluminum gate electrode is formed in an electrolytic solution of 3% by volume of oxalic acid solution and a voltage of 3 V is applied thereto is plotted on the horizontal axis. Is shown on the vertical axis. When an oxalic acid aqueous solution is used as the electrolytic solution, the anodized film thickness can be easily controlled in a wide range by the anodizing time. An anodic oxide film having a thickness of about 1 μm can be formed in an anodic oxidation time of 60 minutes. The completed anodic oxide film is more porous than the anodic oxide film formed using an aqueous solution of ammonium tartrate, and can be easily etched with a mixed acid of phosphoric acid, acetic acid, and nitric acid.

Next, the solution was washed with an aqueous solution of ammonium tartrate 3
Anodization is performed again in place of volume%. And FIG.
A second sidewall oxide film 422 is formed in FIG. This second sidewall oxide film 422 has a thickness of 800 to 30
00 °, preferably 1400 °. Next, impurity doping is performed. Thus, a source region 402 and a drain region 403 are formed. Further, the gate electrode and the barrier layer 406 formed thereon form an I-type region 431 which is left without being doped with impurities.

Next, the first sidewall oxide film 421 is removed. In this step, phosphoric acid, acetic acid,
This is performed using a mixed acid mixed with nitric acid. With this mixed acid,
The first sidewall oxide film 421 is selectively removed.

Then, the barrier layer 406 is removed. In the state of FIG. 5 (D) thus obtained, anodic oxidation is again performed using 3% by volume of an aqueous solution of ammonium tartrate. By this anodic oxidation, an upper anodic oxide film indicated by 420 in FIG. 5E is formed. The thickness of this anodic oxide film 420 is 100 to 10
The thickness is set to 00 °, preferably 300 °.

Then, on the structure formed as described above, an interlayer insulating film 408 is formed as shown in FIG. Further, the metal wiring 425 is connected to the source region 402,
The metal wiring 426 is connected to the drain region 403 and the metal wiring 42.
7 is connected to the gate electrode 405.

With this configuration, the gate electrode is protected by the two anodic oxide films 220 and 222. Further, since the upper anodic oxide film 220 is formed to be thin, even when the contact hole is formed, even if the etchant having no etch rate ratio between the gate electrode 205 and the upper anodic oxide film 220 has a contact hole, It is possible to take a process margin for forming.

However, when forming a contact hole,
Etching so as not to damage the gate electrode as shown in FIG. 3A also causes disconnection of the wiring and contact failure. Therefore, as shown in FIG.
It is preferable to perform excessive etching so that 27 bites into gate electrode 205.

Further, in the state shown in FIG.
7 can be arranged under the upper oxide film layer 220.

The widths of the offset regions 215 and 216 are determined by the width of the first sidewall oxide film and the width of the second sidewall oxide film 222.
Is the sum of the widths. Therefore, it is not necessary to form the secondary sidewall oxide film having a slow oxidation formation speed to the same length as the offset region, and if the primary sidewall oxide film capable of forming a wide film in a short time with a low voltage is used, a large width can be obtained. The offset region can be formed quickly.

[0035]

【Example】

[Embodiment 1] In this embodiment, as shown in FIGS.
4 shows a step of forming a thin film transistor on a glass substrate.

As the glass substrate 400, # made by Corning Incorporated
Using 1737, a base film (not shown) is formed thereon. As the base film, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. In this embodiment, silicon oxide is formed to a thickness of 2000 ° by a sputtering method. When a quartz substrate or the like is used, the base film need not be formed.

On the underlying film, a thickness of 300 to 1000 mm
Next, an active layer is formed. In this embodiment, an intrinsic or substantially intrinsic (I-type) amorphous silicon film having a thickness of 500 ° is formed by a parallel plate type plasma CVD method using silane glow discharge. When using the low pressure CVD method, 450 ° C. to 650 ° C., typically 540 ° C. using disilane.
To form an amorphous silicon film.

The obtained amorphous silicon was patterned by photolithography to form an island region 430. Next, the amorphous silicon film as the island region 430 is crystallized into a non-single-crystal silicon film having crystallinity by an excimer laser of KrF of 248 nm. The irradiation energy is 130 to 300 mJ / cm ² and 230 in this embodiment.
It is crystallized by irradiation at mJ / cm ² . The non-single-crystal silicon film may be crystallized by heat without using a laser.
The non-single-crystal silicon film having crystallinity means polycrystalline, microcrystalline, semi-amorphous, or a mixed crystal thereof.

Further, a silicon oxide film having a thickness of 500 to 2000 .mu.m, in this embodiment, 1100 .mu.m was deposited as a gate insulating film 404 on the entire surface of the non-single-crystal silicon film by a plasma CVD method. In the plasma CVD method, a film is formed by glow discharge of a mixed gas of silane and oxygen.

In this embodiment, silicon oxide is used for the gate insulating film. However, silicon nitride, silicon oxynitride, and a laminated film of these may be used.

Next, on the gate insulating film 404, an aluminum film having a thickness of 3000Å10000Å, in this example, 4000Å was deposited as a conductive film over the entire surface by sputtering. For this aluminum film formation, an aluminum alloy target containing 0.1 to 5.0% by weight of a substance such as silicon or scandium is used. In this embodiment, the film is formed using a target containing 0.2% by weight of scandium. Other aluminum alloys may be used as the gate electrode.

The scandium is added in the later 10
This is to prevent the formation of protrusions called hillocks or whiskers due to abnormal growth of aluminum in the heat step at 0 ° C. or higher.

On the conductive film, a thickness of 5
In this embodiment, a silicon nitride film having a thickness of 00 to 2000 mm and a thickness of 1000 mm was deposited on the entire surface as a barrier layer. The silicon nitride film as the barrier layer needs to be dense, but may be a silicon oxynitride film doped with oxygen in order to prevent the silicon nitride film from being peeled off by a stress peculiar to silicon nitride.
Alternatively, the silicon nitride film may be formed at a low temperature (200 to 400 ° C.) by a plasma CVD method, an optical CVD method, or the like instead of sputtering. A carbon film or a silicon oxide film may be used instead of the silicon nitride film.

This barrier layer suppresses generation of hillocks and whiskers in the aluminum film in a later step. Further, the barrier layer has an effect of preventing an anodic oxide film from being formed on the gate electrode in the step of forming the primary side wall oxide film and the step of forming the secondary side wall oxide film.

Note that hillocks and whiskers are
Needle-like or barbed protrusions caused by abnormal growth of aluminum. The hillocks and whiskers are generated by heat treatment, laser beam irradiation, and doping of an impurity element.

Next, a resist mask is formed on the barrier layer. Then, the aluminum film and the barrier layer are patterned using a resist mask, so that the conductive film and the barrier layer are formed in an island shape in a region covering the channel region.

Then, by removing the resist mask, as shown in FIG. 4A, an aluminum film 409 formed in an island shape and a barrier layer 40 formed thereon are formed.
6 is obtained.

Next, anodic oxidation is performed on the side surfaces of the island-shaped aluminum film 409. This anodic oxidation is performed under the following conditions using a 3% aqueous solution of oxalic acid as an electrolytic solution. Voltage 8V Temperature 30 ° C Time 40min

As described above, the first sidewall oxide film 421
Is formed to a thickness of 0.3 μm to 2.0 μm, and in this embodiment, 0.7 μm. The thickness of the primary side wall oxide film can be easily formed by appropriately changing the oxidation time as shown in FIG. The first side wall oxide film 421 is a porous alumina film.

Thus, the state shown in FIG. 4B is obtained.
In this anodic oxidation, the anodic oxide film is not formed because the barrier layer 406 is formed on the island-shaped aluminum film 409.

Next, anodic oxidation is performed again. This anodic oxidation is performed under the following conditions using a 3% aqueous solution of ammonium tartrate as an electrolytic solution. Voltage 100V Temperature 10 ℃ Time 46min

Under the above conditions, a dense secondary side wall oxide film 422 is formed on the inner side adjacent to the primary side wall oxide film 421 at 800 to 3000 °, in this embodiment, 1400 °. This step raises the voltage to 100V in the first 16 minutes. Thereafter, the voltage is kept constant at 100 V and anodic oxidation is continued for 30 minutes. Most of the anodic oxide film is formed in the first 16 minutes, and the remaining 30 minutes are spent on increasing the film density.

The thickness of the second side wall oxide film 422 can be easily formed by appropriately changing the oxidation voltage as shown in FIG. The growth distance of the anodic oxide film having the dense film quality is limited to about 3000 °. When the growth is over 3000 ° C, the applied voltage becomes too high and the solution is sensitive to aging, so that the desired voltage is not actually applied and the thickness of the anodic oxide film is reduced. There is a problem in terms of safety due to the application.

The second side wall oxide film 422 is formed in order to prevent the etching of aluminum serving as the gate electrode by the etchant when the first side wall oxide film 421 is removed. Next, impurity doping is performed using the barrier layer 406 as a mask.

As a method of doping impurities, there are a method called a plasma doping method and a method called an ion implantation method. For plasma doping, PH ₃ or B
_{In this method} , a gas containing an impurity element to be doped, such as ₂ H _{6, is} converted into plasma by high-frequency power or the like, impurity ions are extracted therefrom by an electric field, and accelerated implantation is further performed by the electric field.

On the other hand, in the ion implantation method, PH ₃ or B ₂
In this method, a gas containing an impurity element to be doped, such as H _6, is converted into plasma, ions extracted therefrom are selected by mass separation using a magnetic field, and the selected impurity ions are acceleratedly implanted.

In this embodiment, impurity doping is performed by the plasma doping method. In this embodiment, P (phosphorus) ions are used as impurities at an accelerating voltage of 70 to 10.
0 kV, 80 kV in this embodiment, and a dose of 1 × 10
¹⁵ to 1 × 10 ¹⁶ cm ⁻² , 2.5 × 10 ¹⁵ c in this embodiment
Doping is performed at a dose of m ^-2 .

In this manner, as shown in FIG. 4C, a source region 402 / drain region 403 doped with phosphorus and an I-type non-single-crystal region 431 remaining by the barrier layer 406 are formed. .

In this embodiment, the impurity doping is performed in the second
After the step of forming the next sidewall oxide film, the barrier layer 40
After the step of patterning the barrier layer and the aluminum layer, which makes it possible to use the mask 6 as a mask, doping may be performed before the removal of the primary sidewall oxide film.

In this step, since the basic structure of the MOS type thin film transistor is completed, it is possible to complete the semiconductor device by crystallization and connecting the wiring metal. However, if crystallization is performed at this stage, the impurities that have come under the first anodic oxide film 421 will cause the non-single-crystal region 4
Since a part of 31 is made amorphous, a grain boundary is formed in the active layer.

Therefore, only the first side wall oxide film 421 is removed by etching. The removal of the porous anodic oxide is performed at 45 ° C. for 5 minutes using an etchant (referred to as an aluminum mixed acid) in which acetic acid, nitric acid, phosphoric acid, and water are mixed. This aluminum mixed acid has an extremely low etching rate with respect to a dense oxide film such as the second sidewall oxide film 422, and has selectivity. The dense anodic oxide film 422 has a role of preventing the gate electrode made of aluminum from coming into contact with the aluminum mixed acid. That is, the second sidewall oxide film 4
If there is no 22, the aluminum film 409 is also etched.

Conventionally, without using this aluminum mixed acid,
A chromium-based mixed acid has been used to obtain etching selectivity with aluminum. The chromium-based mixed acid has a serious damage to the environment, and there has been a problem in using it.

Next, the barrier layer is removed by a dry etching method. The etching is performed by plasma etching using a gas containing fluorine, in this embodiment, nitrogen trifluoride. Thus, the state shown in FIG. 5D is obtained.

Then, an aqueous solution of ammonium tartrate 3
Anodization using wt% is performed. This step is performed under the condition that a thin anodic oxide film is formed on the aluminum film 409. The thickness of the upper anodic oxide film 420 is 100Å to 10Å.
00 °, and in this embodiment, 300 °. In this example, only the voltage was set to 20 V, and the other conditions were formed under the same conditions as the step of forming the second sidewall oxide film.

Thus, the gate electrode 405 is formed,
The state shown in FIG. Then, the gate electrode 40
5, a channel region 401, an offset region 415 between the channel region and the source region 402, and an offset region 416 between the channel region and the drain region 403 are simultaneously formed.

The offset regions 415 and 416 have the same I-type conductivity as the channel region 401. The offset regions 415 and 416 function as high resistance regions and have an effect of reducing leakage current.

In this embodiment, the voltage at the time of forming the upper oxide film 420 is set to 20 V. At this time, it is possible to change the film thickness by changing the oxidation voltage. This upper oxide film 420 is formed to suppress hillocks and whiskers of aluminum.

Next, the source region 402 / drain region 40 which has been made amorphous by doping with impurities.
3 is irradiated with a laser beam.

The laser light irradiation activates and crystallizes the region where the impurity ions are doped. Excimer laser such as KrF or XeCl is used for laser irradiation conditions. In this embodiment, activation is performed by irradiating an energy density of 165 mJ / cm ² using KrF of 248 nm.

The thin film transistor thus formed has
An interlayer insulating film 408 is formed. Then, metal wirings 425, 426, and 427 for operating the thin film transistor
A contact hole for making contact with the substrate is formed.

In the step of forming a contact hole in the gate electrode, since the thickness of the anodic oxide film 420 existing on the upper surface of the gate electrode 405 is as thin as about 300 °, a dense anodic oxidation using an aqueous solution of ammonium tartrate is performed. Although it is a film, it can be easily removed with a normal aluminum mixed acid or buffered hydrofluoric acid used to remove a natural oxide film without using a chromic acid, ensuring the formation of a contact hole.
In addition, it can be performed with good reproducibility.

In this embodiment, the etchant for etching the upper oxide film 420 formed on the gate electrode is HF: NH ₄ F: H ₂ O = 3: 2: 150.
Use a solution of In this etchant, the etch rates of aluminum and aluminum oxide are almost equal, and a sufficient process margin can be obtained when there is a difference between the gate electrode and the upper oxide film.

Then, a source electrode, a drain electrode, and a gate extraction electrode are formed by metal wiring. In this embodiment, aluminum is used as the metal wiring.

Finally, heat treatment is performed in a hydrogen atmosphere at 350 ° C. to hydrogenate the thin film transistor and sinter the wiring aluminum. Thus, a thin film transistor having an offset structure is completed as shown in FIG.

Here, the manufacturing process of a standard N-channel thin film transistor has been described. However, a P-channel type thin film transistor can be formed by changing the type of the dopant. In addition, by performing selective doping, a CMOS circuit can be formed. Also,
It is also possible to obtain a channel-doped MOS structure in which the channel region is doped with low-concentration N-type or P-type impurities in advance.

Further, if a pixel electrode made of ITO is formed by connecting to the drain electrode, a structure arranged in the pixel matrix portion of an active matrix type liquid crystal display device can be obtained.

In the structure shown in this embodiment, it is possible to easily form an opening for contact above the gate electrode by utilizing an anodic oxidation process using the gate electrode as an anode. .

[Embodiment 2] In this embodiment, as shown in FIG. 6, an SOI N-channel thin film transistor using a single crystal silicon wafer as a substrate is shown.

First, a step of forming an insulating layer 607 is performed. In this step, SIMOX (Separation-by-I) is used to form a buried insulating layer in the substrate by implanting oxygen ions, nitrogen ions, etc. into the single crystal silicon wafer.
mplanted Oxygen) method, and a wafer bonding method in which two silicon wafers are directly bonded via an insulating film such as an oxide film or a nitride film on the surface.

In this embodiment, SIMOX (Separation-by-Implanted O
xygen) method.

First, oxygen ions are implanted into a single crystal silicon wafer. This oxygen ion implantation has a dose of 1 ×
10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻² , 2 × 10 ¹⁸ c in the present embodiment
At a dose of m ^-2 , acceleration energy is 32-180ke
V, in this embodiment, implantation is performed at an acceleration energy of 180 keV.

Thus, by subjecting oxygen ions added to the single crystal silicon wafer to a high-temperature heat treatment,
A buried silicon oxide layer 607 is formed. High temperature heat treatment is 1
The heat treatment is performed at 100 to 1400 ° C., in this embodiment, at 1300 ° C.

In this step, the single-crystal silicon wafer is separated into a single-crystal silicon substrate 600 and a single-crystal silicon layer on the surface serving as an active layer. The silicon oxide film 607 is formed to a thickness of 20 to 5000 Å, and 3000 で は in this embodiment. During ion implantation into the single crystal silicon wafer, the temperature of the single crystal silicon wafer is raised to 400 to 600 ° C., in this embodiment, 500 ° C., to maintain the single crystallinity of the silicon layer on the surface.

The thickness of the single crystal silicon layer on the surface is 100
It is formed at 0 to 5000 °, in this embodiment at 2000 °.
The single-crystal silicon layer on the surface thus formed is used for a semiconductor device.

In this embodiment, the same processing as in the first embodiment is performed using the single crystal silicon layer on the surface as an active layer of the thin film transistor. That is, the active layer is patterned to obtain an island-shaped active layer. Then, a gate insulating film 604 is formed in the active layer. An aluminum film and a barrier layer are formed thereon,
Patterning is performed to obtain an island-shaped aluminum film and a barrier layer. A primary sidewall oxide film is formed on the sidewall of the aluminum film by anodic oxidation using an oxalic acid aqueous solution.

Next, a second anodic oxide film 622 is formed on the inner side near the first sidewall oxide film. Then, phosphorus is doped as an impurity. In this step, the source region 602 and the drain region 603 are formed in the active layer, and the channel region 601 is formed under the aluminum film serving as the gate electrode.
Is formed. Further, an offset region 615 and a channel region 6 between the channel region 601 and the source region 602.
01 and the drain region 603, the offset region 616
Is formed. Thereafter, a step of removing the primary sidewall oxide film and a step of removing the barrier layer are performed.

Then, an anodic oxide film is formed on the aluminum film serving as the gate electrode. By this step, upper anodic oxide film 620 and gate electrode 605 are formed.
Next, the source region 602 and the drain region 603 are activated using laser light.

The thin film transistor thus formed has
An interlayer insulating film 608 is formed. Then, the interlayer insulating film 60
A contact hole is formed in 8.

Then, the source electrode 62 is formed by metal wiring.
5, a drain electrode 626 and a gate extraction electrode 627 are formed. Finally, heat treatment is performed in a hydrogen atmosphere at 350 ° C. to hydrogenate the thin film transistor and sinter the wiring aluminum. Thus, FIG.
As shown in (1), a thin film transistor having an offset structure on a silicon wafer is completed.

In the thin film transistor thus completed, the elements can be completely separated from each other, so that a higher integration can be realized by miniaturization of the device. Further, since the parasitic capacitance between the element and the substrate can be reduced, the operation speed of the device can be increased. Furthermore, a three-dimensional structure is made possible, and higher integration and multifunction of the device can be achieved.

[0091]

In the thin film transistor, by providing a barrier layer above the gate electrode, it is possible to suppress the formation of the anodic oxide film having the same thickness as the side wall up to the upper portion of the gate electrode in the step of anodizing the side wall. Has the effect of doing Then, by removing the barrier layer and forming a thin anodic oxide film on the gate electrode, the contact of the gate electrode can be easily formed. Therefore, it is possible to realize a highly reliable thin film transistor having an in-plane uniformity and an offset region and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional thin film transistor having an offset structure.

FIG. 2 is a cross-sectional view illustrating a thin film transistor having an offset structure according to an example of the present embodiment.

FIG. 3 is an enlarged view of a contact portion between a gate electrode and a metal wiring.

FIG. 4 is a sectional view of a manufacturing process according to an example of the embodiment.

FIG. 5 is a sectional view of a manufacturing process according to an example of the embodiment.

FIG. 6 is a cross-sectional view illustrating a thin film transistor having an offset structure according to an example of the present embodiment.

FIG. 7 is a graph of oxidation time and oxide film thickness when anodizing aluminum with an oxalic acid aqueous solution.

FIG. 8 is a graph showing an oxidation time and an oxide film thickness when anodizing aluminum with an aqueous solution of ammonium tartrate.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 substrate 101 channel region 102 source region 103 drain region 104 gate insulating film 105 gate electrode 106 barrier layer 108 interlayer insulating film 115 source-side offset region 116 drain-side offset region 122 secondary anodic oxide film 125 source metal wiring 126 drain Metal wiring 127 Gate metal wiring 200 Substrate 201 Channel region 202 Source region 203 Drain region 204 Gate insulating film 205 Gate electrode 208 Interlayer insulating film 215 Source side offset region 216 Drain side offset region 220 Upper anodic oxide film 222 Secondary anode Oxide film 225 Source metal wiring 226 Drain metal wiring 227 Gate metal wiring 400 Substrate 401 Channel region 402 Source region 403 Drain region 404 Gate Edge film 405 Gate electrode 406 Barrier layer 408 Interlayer insulating film 409 Aluminum film 415 Offset region on the source side 416 Offset region on the drain side 420 Upper anodized film 421 First anodized film 422 Second anodized film 425 Source metal wiring 426 Drain metal wiring 427 Gate metal wiring 430 Active layer 431 I-type layer 600 Substrate 601 Channel region 602 Source region 603 Drain region 604 Gate insulating film 605 Gate electrode 607 Embedded insulating film 608 Interlayer insulating film 615 Source offset region 616 Drain side Offset region 620 Upper anodic oxide film 622 Secondary anodic oxide film 625 Source metal wiring 626 Drain metal wiring 627 Gate metal wiring

Claims (6)

[Claims] A source region, a drain region, a channel region formed between the source region and the drain region, and a source region and a drain region between the source region and the channel region. An offset region is formed adjacent to the channel region between the drain region and the channel region, and at least a gate insulating film formed on the channel region and on the gate insulating film above the channel region. A formed gate electrode, a sidewall oxide film layer formed by oxidizing the electrode on a sidewall of the gate electrode, and an upper oxide film layer formed by oxidizing the electrode on the gate electrode. Wherein the offset region extends outside the sidewall oxide film, and the upper oxide film is A thin film semiconductor device characterized by being thinner than an oxide film. 2. An insulating layer on a silicon wafer, a source region, a drain region, a channel region formed between the source region and the drain region, and a region between the source region and the channel region. An offset region is formed adjacent to the channel region between the drain region and the channel region, and at least a gate insulating film formed on the channel region and on the gate insulating film above the channel region. A formed gate electrode, a sidewall oxide film layer formed by oxidizing the electrode on a sidewall of the gate electrode, and an upper oxide film layer formed by oxidizing the electrode on the gate electrode. Wherein the offset region extends outside the sidewall oxide film, and the upper oxide film is A thin film semiconductor device characterized by being thinner than a sidewall oxide film. 3. A first step of forming a non-single-crystal film on a substrate having an insulating surface, a second step of forming a conductive film on the non-single-crystal film, and a barrier layer on the conductive film A fourth step of patterning the conductive film and the barrier layer; a fifth step of oxidizing a sidewall of the conductive film to form a primary sidewall oxide film; A sixth step of forming a second sidewall oxide film inside the conductive film adjacent to the first sidewall oxide film, a seventh step of removing the first sidewall oxide film, and removing the barrier layer And a step of doping impurities between after the fourth step and before the seventh step. 4. A first step of forming a non-single-crystal film on a substrate having an insulating surface, a second step of forming a conductive film on the non-single-crystal film, and a barrier layer on the conductive film A fourth step of patterning the conductive film and the barrier layer; a fifth step of oxidizing a sidewall of the conductive film to form a primary sidewall oxide film; A sixth step of forming a second sidewall oxide film inside the conductive film adjacent to the first sidewall oxide film, a seventh step of removing the first sidewall oxide film, and removing the barrier layer An eighth step of forming, an ninth step of forming an anodic oxide film on the conductive film, and a step of doping impurities between after the fourth step and before the seventh step A method for manufacturing a semiconductor device. 5. The thin film semiconductor device according to claim 4, wherein an anodic oxidation voltage when anodizing the secondary oxide film in the sixth step is higher than an anodic oxidation voltage in the ninth step. How to make 6. A first step of implanting oxygen ions or nitrogen ions into a silicon wafer, a second step of performing a high-temperature heat treatment on the silicon wafer to form an active layer, and a third step of patterning the active layer. A second step of forming a conductive film on the active layer, a third step of forming a barrier layer on the conductive film, and a fourth step of patterning the conductive film and the barrier layer. A fifth step of oxidizing a sidewall of the conductive film to form a first sidewall oxide film, and forming a second sidewall oxide film inside the conductive film adjacent to the first sidewall oxide film. Step 6, a seventh step of removing the primary sidewall oxide film, an eighth step of removing the barrier layer, and after the fourth step and before the seventh step. Method for fabricating thin film semiconductor device having impurity doping step Law.