JPH0837309A - Manufacture of thin-film semiconductor device - Google Patents

Abstract

PURPOSE:To form a highly reliable thin-film semiconductor device at a low cost even when forming it on a substrate having a large area. CONSTITUTION:In the manufacturing method of a thin-film semiconductor device, a film forming process and an ion implantation process are included. In the film forming process, on the surface of an insulation substrate 1, a semiconductor layer 2 to be changed into an active layer, a gate insulation film 3, and a gate electrode 4 are formed respectively. In the ion implantation process, by the implantation of non-mass-separative ions, in a self-aligned way, source and drain regions 6 are formed using the gate electrode 4 as a mask. In this manufacturing method of a thin-film semiconductor device, first, the gate electrode 4 is so formed that its film thickness exceeds 350nm, and thereafter, in the ion implantation process, the ions are implanted into the source and drain regions 6 while the gate electrode 4 is used as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device, and more particularly, to image input / output of a liquid crystal display, an image scanner, etc. in which a peripheral circuit made of thin film transistors is built on a large area insulating substrate such as a glass substrate. The present invention relates to a method for manufacturing a large-area thin film transistor applied to a device.

[0002]

2. Description of the Related Art A polycrystalline silicon thin film transistor which has been used for a liquid crystal display or the like having a driving circuit using a polycrystalline silicon thin film transistor has a process temperature of 600 ° C. or more and a large amount of expansion and contraction on an inexpensive glass substrate. , It was necessary to use a quartz substrate. on the other hand,
Quartz substrates are expensive and it is difficult to increase the area, so
It was limited to small panels such as viewfinders and projection displays.

FIG. 3 shows Japan Display as an example of a manufacturing process of a conventional polycrystalline silicon thin film transistor.
92 Hiroshima (JAPAN Display 92 HI
ROSHIMAP App565-568).

First, as shown in FIG. 3 (a), a quartz substrate 1
An amorphous silicon film is deposited on the upper surface by a low pressure CVD method, crystallized by using an excimer laser or the like, a polycrystalline silicon thin film to be the active layer 2 is processed into an island shape, and a silicon oxide film or the like is formed by a CVD method or the like. A gate insulating film 3 is deposited to 100 nm, and then a polycrystalline silicon film 4 to be a gate electrode is deposited to 300 nm by CVD or the like. Subsequently, the polycrystalline silicon film 4 is patterned into a desired shape (see FIG.
(b)), as shown in FIG. 3 (c), P + is 2E15 cm at an energy of 100 KeV using mass separation ion implantation.
^-2 implantation is performed to form the source / drain regions 6, and thereafter, heat treatment for activating impurities is performed. After that, hydrogen plasma treatment for passivating defect levels in the MOS interface or in the active layer is performed, and subsequently, silicon dioxide serving as a first interlayer insulating film is deposited using a plasma CVD method to form a contact hole. Then, a laminated film of aluminum / molybdenum as a wiring metal is formed and processed, and SiN _x having a film thickness of about 1 μm as a protective insulating film is plasma CVD
Then, the thin film transistor is completed.

By the way, in recent years, due to the development of the low temperature technology of the polycrystalline silicon thin film transistor process, the maximum temperature of 50 has been reached.
Since the temperature can be lowered to 0 ° C. or lower, it has become possible to use glass for the substrate. Therefore, the possibility of increasing the panel size is increasing.

[0006]

Conventionally, as described above, the mass separation ion implantation method has been used for ion implantation. This mass separation ion implantation method has a problem that the throughput is very low. Further, in the mass separation ion implantation method, since the beam diameter is extremely small, there is a problem that workability is poor for a large area substrate.

Further, it is necessary to perform a heat treatment in order to activate the impurities after the ion implantation, but this heat treatment temperature is about 600 ° C., and there is a problem that the glass substrate is melted during the heat treatment.

Therefore, the present inventors have proposed to use non-mass separated ion implantation. When implanting non-mass separated ions, for example, when PH ₃ diluted with H ₂ is used, light ions such as hydrogen as a diluent gas are simultaneously introduced, and the reason is not clear, but the annealing temperature is 300 to 4
It is known that even at a low temperature of about 00 ° C, it is sufficiently activated. Further, since the beam diameter can be freely increased, the throughput is high, which is extremely effective for a large area substrate.

However, at this time, light ions such as hydrogen pass through the gate electrode and the gate insulating film and reach the polycrystalline silicon layer, which damages the polycrystalline silicon film in the channel region and causes characteristic deterioration. There was a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to form a thin film semiconductor device which can be formed at a low temperature and is low in cost and highly reliable even on a large area substrate.

[0011]

Therefore, in the present invention, when the source / drain regions are formed in the gate electrode in a self-aligned manner by implanting non-mass separated ions, the thickness of the gate electrode is made sufficiently large. It is something that I tried to leave.

That is, from the experimental results, the gate electrode is
I try to keep it above 0 nm. A step of forming a semiconductor layer to be an active layer on the surface of an insulating substrate, a gate insulating film, and a gate electrode, and a source / drain region in a self-aligned manner by implanting non-mass separated ions using the gate electrode as a mask. In a method of manufacturing a thin film semiconductor device including an ion implantation step of forming a film, the ion implantation step is a step of forming the gate electrode to have a film thickness of 350 nm or more and then performing ion implantation using this as a mask. Characterize.

[0013]

According to the method of the present invention, the thickness of the gate electrode is 3
Since the thickness is set to 50 nm or more, light ions other than desired impurities are prevented from damaging the channel during the formation of the source / drain of the thin film transistor, the transistor is not deteriorated, and the thin film transistor is highly reliable at low temperature. Can be obtained.

Further, according to the method of the present invention, since non-mass separated ion implantation is used, annealing can be performed at a low temperature, the glass substrate can be easily used, and the throughput can be increased. It is possible to reduce the cost.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a conceptual diagram showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

According to this method, an amorphous silicon layer is deposited on a quartz substrate 1 and is crystallized by using an excimer laser or the like to form a polycrystalline silicon layer which becomes an active layer 2, and a gate insulating film 3 is formed on the polycrystalline silicon layer. With a film thickness of 100 nm
The VD silicon oxide film and the gate electrode 4 have a film thickness of 50.
After forming a 0 nm tantalum film and patterning it,
This gate electrode 4 is used as a mask to form source / drain regions 6 by doping P + ions using non-mass separation ion implantation, and thus the gate electrode 4 is thickened in this manner. H +
Light ions such as the above do not penetrate the gate electrode 4 and reach the channel region.

Hereinafter, this method will be described in detail.

First, as shown in FIG. 1 (a), a 100 nm-thick amorphous silicon film is deposited on a quartz substrate 1 by a low pressure CVD method, and then a KrF excimer laser is used to form 45.
A polycrystalline silicon film 2 is formed by performing laser irradiation on the entire surface with an intensity of 0 mJ / cm ² . Thereafter, this polycrystalline silicon film 2 is patterned into an island shape by using a photolithography method.

Further, as shown in FIG. 1 (b), ECR-
A 100 nm-thickness silicon oxide film serving as a gate insulating film is deposited by the CVD method. Then, a tantalum thin film 4 having a film thickness of 500 nm is deposited by a sputtering method, and OFPR8
A novolac-based resist manufactured by Tokyo Ohka Co., Ltd., which is called "00", is used as a mask with a resist pattern formed by photolithography using a G line having a wavelength of 435 nm as a mask.
This tantalum thin film is patterned by using the DE method to form the gate electrode 4.

Then, as shown in FIG. 1 (c), the gate electrode 4 is used as a mask to perform doping using non-mass separation ion implantation, and P + ions are implanted at 1 Ke16 cm ^{-2 with} an energy of 100 KeV to form the source / drain regions 6.
To form.

Thereafter, in order to activate the impurities, 500 ° C. 2
Heat treatment for a period of time to activate P + ions, and further hydrogen plasma treatment for passivating defect levels in the MOS interface or in the active layer, followed by plasma CVD to form a first interlayer insulating film. A silicon dioxide film (not shown) having a film thickness of 800 nm is formed. After forming a contact hole in the first interlayer insulating film,
An aluminum / molybdenum laminated film to be a wiring metal is deposited and patterned, and finally a film thickness of 1 is formed as a protective insulating film.
A μm SiN _x film is formed.

The thin film transistor formed by the method of the present invention has good characteristics and high reliability without causing damage to the channel, and also has high ion implantation throughput.

In the above embodiment, the thickness of the gate electrode is 500.
nm is used because this is because the implantation energy in the ion doping step is as high as 100 KeV, and can be appropriately changed according to this implantation energy. Since this implantation energy must be strong enough to pass through the gate insulating film, the lower limit varies depending on the thickness of the gate insulating film, but it can be reduced to about 70 KeV. In that case, about 350 nm. Was enough.

Next, in order to investigate the relationship between the occurrence of channeling and the film thickness of the gate electrode, a silicon oxide film having a film thickness of 100 nm is formed on the surface of the polycrystalline silicon layer, and a tantalum film having various film thicknesses is formed thereon. A thin film was formed, ion doping was performed through the tantalum thin film, and then electrodes were further formed on the front and back surfaces to prepare a sample. Then, a voltage is applied between the electrodes to measure the relationship between the capacitance of the silicon oxide film and the polycrystalline silicon layer and the applied voltage, that is, the CV characteristic of the MOS capacitor formed here, and the result is shown in FIG. Shown in. Where the vertical axis is C
_min / C _ox , and the horizontal axis is the thickness (nm) of the tantalum thin film.
The ion implantation conditions in this doping step were an implantation energy of 100 KeV, a dose concentration of 1E16 cm ^-2, and non-mass separated ion implantation (curve a). At this time, H + ions are implanted together with P + ions, and activation becomes easy. The other conditions were exactly the same, and only the implantation energy was set to 70 KeV (curve b).

For comparison, C _min / C _{ox in the} case of non-doping, that is, without ion implantation was 0.3 (broken line ref). Therefore, if the target is to suppress C _min / C _ox to 0.3, it is 5 when the implantation energy is 100 KeV.
It was about 350 nm at 00 nm and an implantation energy of 70 KeV. Although the same characteristics were measured by changing only the dose amount, it was found that the dose amount hardly depends on the dose amount, but depends only on the implantation energy. Further, although the material of the gate electrode was changed to a polycrystalline silicon film, a tungsten film, etc., it was found that it hardly depends on the material of the gate electrode but only on the implantation energy.

From these results, it can be seen that a thin film transistor with high reliability can be obtained without damaging the channel when the film thickness of the gate electrode is 350 nm or more at low temperature.

Further, in the above embodiment, the gate electrode is used as it is after ion doping, but it may be etched back to a normal thickness after ion doping, or two kinds of conductors having etching selectivity may be used. It may be formed in advance and used as a mask for ion doping, and thereafter, only the upper-layer gate electrode may be removed by etching under etching conditions having etching selectivity. As a result, the surface step difference can be reduced and the disconnection of the upper layer wiring can be prevented.

Further, although the tantalum thin film is used as the gate electrode in the above-mentioned embodiment, the invention is not limited to tantalum, but can be applied to the case of using other refractory metal such as tungsten, or polycrystalline silicon. is there.

Further, it is needless to say that the invention is not limited to the thin film transistor, and can be applied to any device including a step of implanting impurity ions in a self-aligned manner such as a semiconductor device formed on a semiconductor substrate. .

Modifications can be made as appropriate without departing from the scope of the present invention.

[0032]

As described above, according to the present invention, it is possible to form a highly reliable semiconductor device such as a thin film transistor integrated circuit on a large area substrate.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing the results of measuring the tantalum film thickness dependence on channeling.

FIG. 3 is an explanatory view showing a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

 1 Glass Substrate 2 Polycrystalline Silicon Film 3 Gate Insulating Film 4 Tantalum Thin Film (Gate Electrode) 5 Doping Ion 6 Source / Drain Region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 G

Claims (1)

[Claims] 1. A film forming step of forming a semiconductor layer to be an active layer on a surface of an insulating substrate, a gate insulating film, and a gate electrode; and ion implantation into the active layer using the gate electrode as a mask, In the method of manufacturing a thin film semiconductor device including an ion implantation step of forming source / drain regions in a self-aligned manner, the ion implantation step uses the gate electrode as a mask after the gate electrode is formed to have a film thickness of 350 nm or more. A method of manufacturing a thin film semiconductor device, which comprises a step of implanting non-mass separated ions.