JPH09213744A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH09213744A JPH09213744A JP8020741A JP2074196A JPH09213744A JP H09213744 A JPH09213744 A JP H09213744A JP 8020741 A JP8020741 A JP 8020741A JP 2074196 A JP2074196 A JP 2074196A JP H09213744 A JPH09213744 A JP H09213744A
- Authority
- JP
- Japan
- Prior art keywords
- package
- film
- hole
- semiconductor device
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置のう
ち、特にフリップチップ接続によってパッケージを実装
した半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a package mounted by flip chip connection and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来の半導体装置及びその製造方法につ
いて、図4を参照して説明する。図4は従来の半導体装
置の断面図である。従来、LGA(Land Grid Array
)やBGA(Ball Grid Array )等のパッケージを
用いた半導体装置においては、パッケージ11の裏面の
電極部12に半田ボール15を形成し、プリント基板1
3の電極部14に対応する場所に合わせて半田付けして
プリント基板13にパッケージ11を直接実装するとい
う、いわゆるフリップチップ接続が用いられている。2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described with reference to FIG. FIG. 4 is a sectional view of a conventional semiconductor device. Conventionally, LGA (Land Grid Array)
), A BGA (Ball Grid Array), or other semiconductor device using a package, a solder ball 15 is formed on the electrode portion 12 on the back surface of the package 11,
A so-called flip-chip connection is used in which the package 11 is directly mounted on the printed circuit board 13 by soldering at a position corresponding to the third electrode portion 14.
【0003】[0003]
【発明が解決しようとする課題】半田ボール15を用い
てパッケージ11を実装する方法においては、パッケー
ジ11の電極部12に半田ボール15をつけ、その後プ
リント基板13の電極部14に接続する工程が必要とな
るため、時間がかかるという問題があった。In the method of mounting the package 11 using the solder balls 15, the step of attaching the solder balls 15 to the electrode portions 12 of the package 11 and then connecting the solder balls 15 to the electrode portions 14 of the printed circuit board 13 is required. Since it is necessary, there is a problem that it takes time.
【0004】また、図5の従来の半導体装置における問
題点の一例を示した説明図で見られるように、実装時に
半田ボール15がつぶれて隣接する半田ボール15と接
触しショートする可能性があるため、隣り合う電極部1
2間の間隔を広くしなければならないので、狭ピッチ化
が制限されるという問題があった。Further, as seen in the explanatory view showing an example of the problem in the conventional semiconductor device of FIG. 5, there is a possibility that the solder ball 15 is crushed during mounting and comes into contact with the adjacent solder ball 15 to cause a short circuit. Therefore, the adjacent electrode portions 1
Since the space between the two must be widened, there is a problem that the narrowing of the pitch is limited.
【0005】本発明は上記のような事情を考慮し、パッ
ケージをフリップチップ接続で実装する際に、工程を簡
略化して、更に、電極間の狭ピッチ化を実現できる半導
体装置を提供することを目的としている。In view of the above circumstances, the present invention provides a semiconductor device which simplifies the process when mounting a package by flip-chip connection and can realize a narrow pitch between electrodes. Has an aim.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置は、半導体素子を封止したパッケ
ージと、このパッケージが実装されるプリント基板と、
このプリント基板と前記パッケージの間に挿入され、前
記プリント基板の電極と前記パッケージの電極の接続さ
れるべき部分に貫通孔を有するフィルムとを具備したこ
とを特徴とするものである。In order to achieve the above object, a semiconductor device of the present invention comprises a package in which a semiconductor element is sealed, a printed board on which the package is mounted,
It is characterized in that it is provided between the printed board and the package, and is provided with a film having a through hole at a portion to be connected to the electrode of the printed board and the electrode of the package.
【0007】また、前記フィルムの前記貫通孔には低融
点金属を充填することを特徴とするものである。更に、
前記貫通孔は、開口端の幅が中心部の幅よりも広いこと
が好ましい。Further, the through hole of the film is filled with a low melting point metal. Furthermore,
The width of the opening of the through hole is preferably wider than the width of the central portion.
【0008】また、プリント基板とパッケージの間に挿
入するフィルムの前記プリント基板の電極と前記パッケ
ージの電極の接続されるべき部分に、貫通孔を開ける工
程と、前記貫通孔に低融点金属を充填する工程と、前記
パッケージと前記フィルムの位置合わせを行う工程と、
前記フィルムと前記プリント基板の位置合わせを行う工
程と、位置合わせをおこなった前記パッケージと前記プ
リント基板とを前記フィルムを介して低融点金属で接続
する工程とを具備したことを特徴とする半導体装置の製
造方法がある。Further, a step of forming a through hole in a portion of the film to be connected between the electrode of the printed board and the electrode of the package of the film inserted between the printed board and the package, and filling the through hole with a low melting point metal. And a step of aligning the package and the film,
A semiconductor device comprising: a step of aligning the film and the printed circuit board; and a step of connecting the aligned package and the printed circuit board with a low melting point metal through the film. There is a manufacturing method of.
【0009】[0009]
【発明の実施の形態】以下、図面を参照して本発明の実
施例に係る半導体装置及びその製造方法を説明する。図
1は、本発明の第1の実施例に係る半導体装置の断面
図、図2(a)は、本発明の第1の実施例で用いられる
フィルムの斜視図、図2(b)は、図2(a)のフィル
ムの断面図である。DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2A is a perspective view of a film used in the first embodiment of the present invention, and FIG. It is sectional drawing of the film of FIG.
【0010】フィルム6は非導電で耐熱性の材料、例え
ば厚さ1mil程度のポリイミドを用いる。フィルム6
は、まず、パッケージ1及びプリント基板3の電極部
2,4に対応する場所にプレス加工により表側から裏側
まで同じ幅の貫通孔7を開け、次にこの貫通孔7よりも
大きな穴のあいたマスクをフィルム6の上に被せてエッ
チング処理を行い開口端を広くする。その後、貫通孔7
の上下から半田5を流し半田ボール5の両側の先端がフ
ィルム6の表面から出るように形成する。The film 6 is made of a non-conductive and heat-resistant material such as polyimide having a thickness of about 1 mil. Film 6
First, a through hole 7 having the same width is formed from the front side to the back side by press working at a position corresponding to the electrodes 2 and 4 of the package 1 and the printed circuit board 3, and then a mask having a hole larger than the through hole 7 is formed. Is covered on the film 6 and an etching process is performed to widen the opening end. After that, through hole 7
The solder 5 is made to flow from above and below so that the ends of the solder balls 5 on both sides come out from the surface of the film 6.
【0011】上記のような加工をしたフィルム6に位置
合わせ用の印を付ける。同様に、パッケージ1及びプリ
ント基板3にも位置合わせ用の印を付けて、例えばレー
ザーを用いて場所を検出しパッケージ1及びプリント基
板3の電極部2,4を対応させるように位置合わせを行
い、熱を加えて半田5を溶かし、パッケージ1の電極部
2とプリント基板3の電極部4をフィルム6を介して電
気的に接続する。A mark for alignment is attached to the film 6 processed as described above. Similarly, a mark for alignment is also attached to the package 1 and the printed circuit board 3, and the position is detected by using a laser, for example, and the electrodes 1 and 4 of the package 1 and the printed circuit board 3 are aligned with each other. Then, heat is applied to melt the solder 5, and the electrode portion 2 of the package 1 and the electrode portion 4 of the printed board 3 are electrically connected via the film 6.
【0012】これにより、パッケージ1の電極部2に半
田ボール5をつけていく工程が必要なくなり、半田5を
充填したフィルム6をパッケージ1及びプリント基板3
の間に挿入する工程に置き換えることができるので、効
率が良く、組立て工程の時間が短縮される。As a result, the step of attaching the solder balls 5 to the electrode portions 2 of the package 1 is not necessary, and the film 6 filled with the solder 5 is attached to the package 1 and the printed circuit board 3.
Since it can be replaced with a process of inserting the device in between, the efficiency is improved and the assembly process time is shortened.
【0013】また、開口端を広くしたことにより、実装
時に半田5がつぶれてもフィルム6の開口端スペースに
半田5が流れ込むため、隣接する半田5と接触する心配
が無いので半田5によるショートを防ぐことができる。Further, by widening the opening end, the solder 5 flows into the opening end space of the film 6 even if the solder 5 is crushed at the time of mounting, and there is no fear of contact with the adjacent solder 5, so that a short circuit due to the solder 5 occurs. Can be prevented.
【0014】次に、図1及び図2を参照して本発明の第
2の実施例に係る半導体装置及びその製造方法について
説明する。まず、フィルム6の外形サイズをパッケージ
1と同じ外形サイズに形成する。フィルム6の上のパッ
ケージ1及びプリント基板3の電極部2,4に対応する
場所に任意の大きさに穴のあいたマスクを被せ、エッチ
ング処理を行い表側から裏側まで同じ幅の貫通孔7を開
ける。その後、この貫通孔7よりも大きな穴のあいたマ
スクを被せ再びエッチング処理を行い、貫通孔7の開口
端を広くする。更に、貫通孔7の中心に半田5を充填
し、その後上下から半田ボール5を形成し半田5の充填
が完了する。Next, a semiconductor device according to a second embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. First, the outer size of the film 6 is formed to be the same as the outer size of the package 1. A mask having a hole of an arbitrary size is covered on the film 6 at a position corresponding to the electrodes 1 and 4 of the package 1 and the printed circuit board 3, and an etching process is performed to form a through hole 7 having the same width from the front side to the back side. . After that, a mask having a hole larger than the through hole 7 is covered and etching is performed again to widen the opening end of the through hole 7. Further, the center of the through hole 7 is filled with the solder 5, and then the solder balls 5 are formed from above and below to complete the filling of the solder 5.
【0015】次に、位置合わせ用に枠を形成し、その枠
内にフィルム6及びパッケージ1を合わせて固定し、そ
れをプリント基板3の上に載せて熱処理し、半田5によ
ってパッケージ1の電極部2とプリント基板3の電極部
4をフィルム6を介して電気的に接続する。Next, a frame is formed for alignment, the film 6 and the package 1 are aligned and fixed in the frame, and the film 6 and the package 1 are placed on the printed circuit board 3 and heat-treated. The portion 2 and the electrode portion 4 of the printed circuit board 3 are electrically connected via the film 6.
【0016】また、フィルム6の貫通孔7に半田5を充
填する方法としては、フィルム6を3層構造にするもの
があり、図面を用いて説明する。図3は、本発明で使用
されるフィルムの変形例の製造工程図である。As a method for filling the through holes 7 of the film 6 with the solder 5, there is a method of forming the film 6 into a three-layer structure, which will be described with reference to the drawings. FIG. 3 is a manufacturing process diagram of a modified example of the film used in the present invention.
【0017】まず、図3(a)及び(b)に示されるよ
うに、フィルム6aのパッケージ1及びプリント基板3
の電極部2,4に対応する場所にプレス加工により表側
から裏側まで同じ幅の貫通孔7を開ける。次に、図3
(c)に示されるように貫通孔7にCuを充填し、図3
(d)に示されるようにフィルム6aの上下からフィル
ム6b及び6cを被せる。被せたフィルム6b及び6c
に、図3(e)及び(f)に示されるように上記第1の
実施例と同様の方法でエッチング処理を行い、開口部に
半田5を形成する。First, as shown in FIGS. 3A and 3B, the package 1 of the film 6a and the printed circuit board 3 are formed.
Through holes 7 of the same width are formed from the front side to the back side by press working at the locations corresponding to the electrode portions 2 and 4. Next, FIG.
As shown in FIG. 3C, the through hole 7 is filled with Cu, and
As shown in (d), the film 6a is covered with the films 6b and 6c from above and below. Covered films 6b and 6c
Then, as shown in FIGS. 3 (e) and 3 (f), an etching process is performed by the same method as in the first embodiment to form the solder 5 in the opening.
【0018】尚、図3に示される製造工程において、あ
らかじめフィルム6b及び6cのパッケージ1及びプリ
ント基板3の電極部2,4に対応する場所にエッチング
処理を行い、その後、フィルム6aの上下からフィルム
6b及び6cを被せる方法もある。In the manufacturing process shown in FIG. 3, etching treatment is performed in advance on the portions of the films 6b and 6c corresponding to the package 1 and the electrode portions 2 and 4 of the printed circuit board 3, and then the film 6a is removed from above and below. There is also a method of covering 6b and 6c.
【0019】また、フィルム6、パッケージ1及びプリ
ント基板3の位置合わせ方法としては、基板3上にガイ
ドピンを立てて、フィルム6及びパッケージ1をそのガ
イドピンにそって順次固定していき、熱を加えてパッケ
ージ1及びプリント基板3の電極部2,4を電気的に接
続する方法もある。As a method of aligning the film 6, the package 1 and the printed circuit board 3, a guide pin is erected on the substrate 3 and the film 6 and the package 1 are sequentially fixed along the guide pin and heat is applied. There is also a method of electrically connecting the electrodes 1 and 4 of the package 1 and the printed circuit board 3 by adding.
【0020】尚、本発明は、上記第1及び第2の実施例
に限定されず、フィルム6の貫通孔7の加工方法とフィ
ルム6、パッケージ1及びプリント基板3の位置合わせ
方法は、各々どの組み合わせを用いてもよい。The present invention is not limited to the first and second embodiments described above, and the method of processing the through hole 7 of the film 6 and the method of aligning the film 6, the package 1 and the printed circuit board 3 are different from each other. A combination may be used.
【0021】尚、本発明は、上記第1及び第2の実施例
に限定されず、フィルム6はポリイミドの代わりにエポ
キシ樹脂、フッ素樹脂、ガラスエポキシ、ポリエステル
を用いることも可能である。また、パッケージ1の電極
部2とプリント基板3の電極部4を電気的に接続するも
のとして、半田5の代わりに低融点金属のCu、Al、
Au、Ni等を用いてもよい。The present invention is not limited to the first and second embodiments described above, and the film 6 can use epoxy resin, fluororesin, glass epoxy, polyester instead of polyimide. Further, instead of the solder 5, Cu, Al, which is a low melting point metal, is used to electrically connect the electrode portion 2 of the package 1 and the electrode portion 4 of the printed board 3.
You may use Au, Ni, etc.
【0022】またフィルム6の穴の形状は、図2(a)
に示されている形状に限定されず、開口端に広がりを持
たせればいかなる形状も可能である。尚、本発明のパッ
ケージ1は、プラスチック樹脂に限定されず、セラミッ
クを用いてもよい。The shape of the holes in the film 6 is shown in FIG.
The shape is not limited to the shape shown in FIG. 1, and any shape is possible as long as the opening end has a spread. The package 1 of the present invention is not limited to plastic resin, and ceramic may be used.
【0023】[0023]
【発明の効果】本発明によれば、貫通孔に半田を充填し
たフィルムを介してパッケージとプリント基板の電極部
を接続することによって、パッケージをフリップチップ
接続で実装する時に生じる可能性のある半田によるショ
ートを防止し、電極間の狭ピッチ化を図ることができ
る。According to the present invention, by connecting the package and the electrode portion of the printed circuit board through the film having the through hole filled with solder, solder which may occur when the package is mounted by flip chip connection It is possible to prevent a short circuit due to, and to narrow the pitch between the electrodes.
【図1】 本発明の実施例の半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図2】 (a)本発明の実施例で用いられるフィルム
の斜視図である。 (b)(a)のフィルムの断面図である。FIG. 2 (a) is a perspective view of a film used in an example of the present invention. (B) It is sectional drawing of the film of (a).
【図3】 本発明で用いられるフィルムの変形例の製造
工程の説明図である。FIG. 3 is an explanatory diagram of a manufacturing process of a modified example of the film used in the present invention.
【図4】 従来の半導体装置の断面図である。FIG. 4 is a sectional view of a conventional semiconductor device.
【図5】 従来の半導体装置における問題点の一例を示
した説明図である。FIG. 5 is an explanatory diagram showing an example of problems in a conventional semiconductor device.
1,11…パッケージ、2,12…パッケージの電極
部、3,13…基板、4,14…基板の電極部、5,1
5…半田、6,6a,6b,6c…フィルム、7…貫通
孔、8…Cu1, 11 ... Package, 2, 12 ... Package electrode part, 3, 13 ... Substrate, 4, 14 ... Substrate electrode part, 5, 1
5 ... Solder, 6, 6a, 6b, 6c ... Film, 7 ... Through hole, 8 ... Cu
Claims (4)
のパッケージが実装されるプリント基板と、このプリン
ト基板と前記パッケージの間に挿入され、前記プリント
基板の電極と前記パッケージの電極の接続されるべき部
分に貫通孔を有するフィルムとを具備したことを特徴と
する半導体装置。1. A package encapsulating a semiconductor element, a printed circuit board on which the package is mounted, and a package which is inserted between the printed circuit board and the package and which connects the electrode of the printed circuit board and the electrode of the package. A semiconductor device, comprising: a film having a through hole in an intended portion.
属を充填したことを特徴とする請求項1記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the through hole of the film is filled with a low melting point metal.
よりも広いことを特徴とする請求項1記載の半導体装
置。3. The semiconductor device according to claim 1, wherein a width of an opening end of the through hole is wider than a width of a central portion of the through hole.
るフィルムの前記プリント基板の電極と前記パッケージ
の電極の接続されるべき部分に、貫通孔を開ける工程
と、前記貫通孔に低融点金属を充填する工程と、前記パ
ッケージと前記フィルムの位置合わせを行う工程と、前
記フィルムと前記プリント基板の位置合わせを行う工程
と、位置合わせをおこなった前記パッケージと前記プリ
ント基板とを前記フィルムを介して低融点金属で接続す
る工程とを具備したことを特徴とする半導体装置の製造
方法。4. A step of forming a through hole in a portion of the film to be inserted between the printed board and the package, where the electrode of the printed board and the electrode of the package are to be connected, and the through hole is filled with a low melting point metal. The step of aligning the package and the film, the step of aligning the film and the printed circuit board, and the package and the printed circuit board that have been aligned via the film. And a step of connecting with a melting point metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8020741A JPH09213744A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8020741A JPH09213744A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09213744A true JPH09213744A (en) | 1997-08-15 |
Family
ID=12035628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8020741A Withdrawn JPH09213744A (en) | 1996-02-07 | 1996-02-07 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09213744A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6544814B1 (en) | 1999-07-27 | 2003-04-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby |
EP1982353A2 (en) * | 2006-01-24 | 2008-10-22 | Texas Instruments Incorporated | Flip-attached and underfilled stacked semiconductor devices |
CN100431150C (en) * | 2001-08-30 | 2008-11-05 | 皇家飞利浦电子股份有限公司 | Sensor arrangement consisting of light-sensitive and/or x-ray sensitive sensors |
-
1996
- 1996-02-07 JP JP8020741A patent/JPH09213744A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6544814B1 (en) | 1999-07-27 | 2003-04-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby |
CN100431150C (en) * | 2001-08-30 | 2008-11-05 | 皇家飞利浦电子股份有限公司 | Sensor arrangement consisting of light-sensitive and/or x-ray sensitive sensors |
EP1982353A2 (en) * | 2006-01-24 | 2008-10-22 | Texas Instruments Incorporated | Flip-attached and underfilled stacked semiconductor devices |
EP1982353A4 (en) * | 2006-01-24 | 2009-04-29 | Texas Instruments Inc | Flip-attached and underfilled stacked semiconductor devices |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030506 |