JPH09205202A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09205202A JPH09205202A JP1215596A JP1215596A JPH09205202A JP H09205202 A JPH09205202 A JP H09205202A JP 1215596 A JP1215596 A JP 1215596A JP 1215596 A JP1215596 A JP 1215596A JP H09205202 A JPH09205202 A JP H09205202A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- well region
- channel
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 14
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 description 35
- 108091006146 Channels Proteins 0.000 description 15
- 238000000034 method Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、半導体基板をドレイン領域としたディプレッ
ションモード二重拡散型ＭＯＳＦＥＴに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a depletion mode double diffusion type MOSFET having a semiconductor substrate as a drain region.
【０００２】[0002]
【従来の技術】従来のディプレッションモード二重拡散
型ＭＯＳＦＥＴ（以下、ディプレッションモードＤＭＯ
Ｓと称す）は、図３（ａ）に示すように、ドレイン領域
を兼ねるＮ形半導体基板１の主表面に、Ｐ形ウェル領域
２とＮ形ソース領域３とが二重拡散技術により形成され
ている。また、Ｎ形半導体基板１とＮ形ソース領域３と
で挟まれたＰ形ウェル領域２の表面領域にはキャリア濃
度が低いＮ形反転層であるＮ形チャネル４が形成されて
いる。Ｎ形チャネル４の上方には絶縁膜５を介してゲー
ト電極６が設けられている。なお、Ｎ形ソース領域３上
にはソース電極８が、Ｎ形半導体基板１（つまり、ドレ
イン領域）の裏面にはドレイン電極９が、それぞれ設け
られている。2. Description of the Related Art A conventional depletion mode double diffusion MOSFET (hereinafter referred to as depletion mode DMO).
As shown in FIG. 3A, a P-type well region 2 and an N-type source region 3 are formed on the main surface of the N-type semiconductor substrate 1 which also serves as a drain region by a double diffusion technique. ing. Further, in the surface region of the P-type well region 2 sandwiched between the N-type semiconductor substrate 1 and the N-type source region 3, an N-type channel 4 which is an N-type inversion layer having a low carrier concentration is formed. A gate electrode 6 is provided above the N-type channel 4 with an insulating film 5 interposed therebetween. A source electrode 8 is provided on the N-type source region 3, and a drain electrode 9 is provided on the back surface of the N-type semiconductor substrate 1 (that is, the drain region).
【０００３】ところで、上記ディプレッションモードＤ
ＭＯＳにおけるＰ形ウェル領域２の水平断面形状は、図
３（ｂ）に示すように四角形である。By the way, the depletion mode D
The horizontal cross-sectional shape of the P-type well region 2 in the MOS is a quadrangle as shown in FIG.
【０００４】[0004]
【発明が解決しようとする課題】ところで、ディプレッ
ションモードＤＭＯＳは、ゲート電圧が零ボルトでもチ
ャネル領域を有する（所謂ノーマリ・オン形のデバイ
ス）ので、オフ状態にするためには、ゲート電圧（信
号）の印加によりＮ形チャネル４のキャリアをなくす必
要がある。このオン・オフの状態が変化する電圧が所謂
しきい値電圧である。しかしながら、上記ディプレッシ
ョンモードＤＭＯＳでは、チップ温度が上昇すると、し
きい値電圧の絶対値が大きくなってしまうという問題が
あり、その結果、オフ状態にする（Ｎ形チャネル４のキ
ャリアをなくす）ためには、より大きなゲート電圧が必
要となってしまうという問題があった。The depletion mode DMOS has a channel region even if the gate voltage is zero volt (a so-called normally-on type device). Therefore, in order to turn it off, the gate voltage (signal) is required. It is necessary to eliminate the carrier of the N-type channel 4 by applying. The voltage at which the on / off state changes is the so-called threshold voltage. However, in the depletion mode DMOS, there is a problem that the absolute value of the threshold voltage becomes large when the chip temperature rises, and as a result, in order to turn it off (to eliminate the carrier of the N-type channel 4). Has a problem that a larger gate voltage is required.
【０００５】本発明は上記事由に鑑みて為されたもので
あり、その目的は、しきい値電圧の温度依存性が小さい
半導体装置を提供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device in which the temperature dependence of the threshold voltage is small.
【０００６】[0006]
【課題を解決するための手段】請求項１の発明は、上記
目的を達成するために、第１導電形の半導体基板の主表
面に、第１導電形のソース領域が形成され、前記ソース
領域を囲んで第２導電形のウェル領域が形成され、前記
半導体基板の主表面と前記ソース領域との間に介在する
前記ウェル領域の表面領域に第１導電形のチャネルが形
成され、前記チャネル上に絶縁膜を介してゲート電極が
形成されて成り、前記ウェル領域の水平断面形状は、略
多角形であり且つ前記略多角形のコーナ部を形成する角
度が１３５度以上であることを特徴とするものであり、
前記ウェル領域のコーナ部の角度が１３５度以上である
ことにより、前記ウェル領域の表面領域での不純物濃度
を均一化できるため、前記チャネルにおける不純物の濃
度が均一となり、その結果、しきい値電圧の温度依存性
が小さくなる。In order to achieve the above object, a first conductivity type source region is formed on a main surface of a first conductivity type semiconductor substrate, and the source region is formed. A well region of the second conductivity type is formed surrounding the channel region, and a channel of the first conductivity type is formed in a surface region of the well region interposed between the main surface of the semiconductor substrate and the source region. And a gate electrode formed on the insulating film via an insulating film, wherein the well region has a substantially polygonal horizontal cross-section, and an angle forming the corner of the polygon is 135 degrees or more. Is what
When the corner portion of the well region has an angle of 135 degrees or more, the impurity concentration in the surface region of the well region can be made uniform, so that the impurity concentration in the channel becomes uniform, resulting in a threshold voltage. The temperature dependence of is reduced.
【０００７】請求項２の発明は、請求項１の発明におい
て、ウェル領域の水平断面形状が、正多角形であるの
で、正多角形でない場合に比べて前記ウェル領域の表面
領域での不純物濃度を均一化できるため、前記チャネル
における不純物濃度が、より均一になり、その結果、し
きい値電圧の温度依存性が小さくなる。請求項３の発明
は、請求項１又は請求項２の発明において、コーナ部の
外接円の曲率半径が１０μｍ以上なので、前記ウェル領
域の表面領域での不純物濃度を更に均一化できるため、
前記チャネルにおける不純物濃度が更に均一になり、そ
の結果、しきい値電圧の温度依存性が小さくなる。According to a second aspect of the invention, in the first aspect of the invention, since the horizontal cross-sectional shape of the well region is a regular polygon, the impurity concentration in the surface region of the well region is larger than that in the case where the well region is not a regular polygon. Can be made uniform, the impurity concentration in the channel becomes more uniform, and as a result, the temperature dependence of the threshold voltage is reduced. According to the invention of claim 3, in the invention of claim 1 or 2, since the radius of curvature of the circumscribed circle of the corner portion is 10 μm or more, the impurity concentration in the surface region of the well region can be made more uniform,
The impurity concentration in the channel becomes more uniform, and as a result, the temperature dependence of the threshold voltage is reduced.
【０００８】請求項４の発明は、第１導電形の半導体基
板の主表面に、第１導電形のソース領域が形成され、前
記ソース領域を囲んで第２導電形のウェル領域が形成さ
れ、前記半導体基板の主表面と前記ソース領域との間に
介在する前記ウェル領域の表面領域に第１導電形のチャ
ネルが形成され、前記チャネル上に絶縁膜を介してゲー
ト電極が形成されて成り、前記チャネル形成用拡散領域
の水平断面形状が略円形であることを特徴とするもので
あり、前記ウェル領域の形状を円形にすることにより、
前記ウェル領域の表面領域での不純物濃度を更に均一化
できるため、前記チャネルにおける不純物濃度が均一に
なり、その結果、しきい値電圧の温度依存性が小さくな
る。さらに、コーナ部が無いので前記ウェル領域への電
界集中が無くなり、耐圧が向上する。According to a fourth aspect of the present invention, a source region of the first conductivity type is formed on the main surface of the semiconductor substrate of the first conductivity type, and a well region of the second conductivity type is formed surrounding the source region. A channel of the first conductivity type is formed in a surface region of the well region interposed between the main surface of the semiconductor substrate and the source region, and a gate electrode is formed on the channel via an insulating film, It is characterized in that the horizontal cross-sectional shape of the diffusion region for channel formation is substantially circular, by making the shape of the well region circular,
Since the impurity concentration in the surface region of the well region can be made more uniform, the impurity concentration in the channel becomes uniform, and as a result, the temperature dependence of the threshold voltage is reduced. Further, since there is no corner portion, electric field concentration on the well region is eliminated and the breakdown voltage is improved.
【０００９】[0009]
【発明の実施の形態】図１（ａ）に本発明の実施の形態
のディプレッションモードＤＭＯＳの断面図を示す。本
ディプレッションモードＤＭＯＳの基本構成は従来例と
略同じであり、ドレイン領域を兼ねるＮ形半導体基板１
の主表面に、Ｐ形ウェル領域２とＮ形ソース領域３とが
二重拡散技術により形成されている。また、Ｎ形半導体
基板１とＮ形ソース領域３とで挟まれたＰ形ウェル領域
２の表面領域にはキャリア濃度が低いＮ形反転層である
Ｎ形チャネル４が形成されている。Ｎ形チャネル４の上
方には絶縁膜５を介してゲート電極６が設けられてい
る。なお、Ｎ形ソース領域３上にはソース電極８が、Ｎ
形半導体基板１（つまり、ドレイン領域）の裏面にはド
レイン電極９が、それぞれ設けられている。FIG. 1A is a sectional view of a depletion mode DMOS according to an embodiment of the present invention. The basic configuration of the depletion mode DMOS is almost the same as the conventional example, and the N-type semiconductor substrate 1 also serving as the drain region is formed.
A P-type well region 2 and an N-type source region 3 are formed on the main surface of the substrate by the double diffusion technique. Further, in the surface region of the P-type well region 2 sandwiched between the N-type semiconductor substrate 1 and the N-type source region 3, an N-type channel 4 which is an N-type inversion layer having a low carrier concentration is formed. A gate electrode 6 is provided above the N-type channel 4 with an insulating film 5 interposed therebetween. The source electrode 8 is formed on the N-type source region 3 by N
Drain electrodes 9 are provided on the back surface of the shaped semiconductor substrate 1 (that is, the drain region), respectively.
【００１０】本ディプレッションモードＤＭＯＳの特徴
とするところは、図１（ｂ）に示すようにＰ形ウェル領
域２の水平断面形状が正８角形であり、その各角部（コ
ーナ部）の角度が略１３５度で形成されていることにあ
る。本ディプレッションモードＤＭＯＳでは、Ｎ形チャ
ネル４は、チャネル形成用Ｐ形ウェル領域２の水平断面
形状を正八角形にすることにより、従来の四角形の場合
よりもＰ形ウェル領域２の表面領域での不純物濃度を均
一にできる。本ディプレッションモードＤＭＯＳでは、
Ｐ形ウェル領域２の水平断面形状が正八角形であり、そ
の各角部（コーナ部）の角度が１３５度で形成されてい
るので、Ｐ形ウェル領域２形成時における正八角形のコ
ーナ部でのＰ形不純物の濃度がコーナ部以外の領域での
Ｐ形不純物の濃度と略均一になる。このため、しきい値
制御用のＮ形不純物をイオン注入によって添加した時
に、Ｎ形チャネル４におけるＮ形不純物濃度を均一にで
きるのである（つまり、図１（ｂ）におけるコーナ部４
ａのＮ形不純物濃度が、コーナ部４ａ以外の領域に比べ
て高くならないのである）。その結果、しきい値電圧の
温度依存性が小さくなるのである。ところで、従来例の
ようにＰ形ウェル領域２の水平断面形状が四角形の場合
は、Ｐ形ウェル領域２形成時に四角形のコーナ部でのＰ
形不純物の濃度が低くなってしまい、その後のＮチャネ
ル４形成時にコーナ部（図４における４ａ’の部分）の
Ｎ形不純物の濃度が高くなって、その結果、しきい値電
圧の温度依存性が大きくなってしまうのである。従っ
て、従来のような水平断面形状が四角形のＰ形ウェル領
域をもつ場合に比べて、本ディプレッションモードＤＭ
ＯＳの方がしきい値電圧の温度依存性を小さくできるの
である。その結果、チップ温度や周囲温度が上昇しても
しきい値電圧の絶対値の変動が抑制され、大きなゲート
電圧が必要でなくなるのである。The feature of the depletion mode DMOS is that the horizontal cross-sectional shape of the P-type well region 2 is a regular octagon as shown in FIG. 1B, and the angle of each corner (corner) is It is formed at approximately 135 degrees. In the depletion mode DMOS, the N-type channel 4 has a regular octagonal horizontal cross-sectional shape of the P-type well region 2 for forming a channel, so that the impurity in the surface region of the P-type well region 2 is larger than that in the conventional quadrangle. The concentration can be made uniform. In this depletion mode DMOS,
Since the horizontal cross-sectional shape of the P-type well region 2 is a regular octagon and the angle of each corner portion (corner portion) is formed to be 135 degrees, the regular octagonal corner portion at the time of forming the P-type well region 2 is formed. The concentration of P-type impurities becomes substantially uniform with the concentration of P-type impurities in regions other than the corners. Therefore, when the N-type impurity for controlling the threshold value is added by ion implantation, the N-type impurity concentration in the N-type channel 4 can be made uniform (that is, the corner portion 4 in FIG. 1B).
The N-type impurity concentration of a is not higher than that of the region other than the corner portion 4a). As a result, the temperature dependence of the threshold voltage is reduced. By the way, if the horizontal cross-sectional shape of the P-type well region 2 is a quadrangle as in the conventional example, the P at the corner portion of the quadrangle when forming the P-type well region 2 is P.
The concentration of the N-type impurity becomes low, and the concentration of the N-type impurity in the corner portion (portion 4a ′ in FIG. 4) becomes high during the subsequent formation of the N-channel 4, resulting in the temperature dependence of the threshold voltage. Is getting bigger. Therefore, the depletion mode DM is compared to the conventional case where the horizontal cross-sectional shape has a square P-type well region.
The OS can reduce the temperature dependence of the threshold voltage. As a result, even if the chip temperature or the ambient temperature rises, the variation of the absolute value of the threshold voltage is suppressed and a large gate voltage is not needed.
【００１１】以下に、本ディプレッションモードＤＭＯ
Ｓの製造方法を図２及び図３に基づいて説明する。ま
ず、Ｎ半導体基板１の主表面上に酸化膜１０を形成す
る。続いて、例えば、通常のフォトリソグラフィ技術と
ドライエッチング技術等によって、酸化膜１０に水平断
面が図３に示すような正八角形の開孔２０（側断面図は
図４（ａ）参照）を複数設ける。その後、酸化膜１０を
マスクとしてＰ形不純物の拡散を行い、高温熱処理を行
うことによって図４（ａ）に示すようなＰ形ウェル領域
２が形成される。ここで、酸化膜１０ａの下方にもＰ形
ウェル領域２が形成されているが、これは、前記高温熱
処理によって前記Ｐ形不純物が横方向（つまり、酸化膜
１０ａの下方）にも拡散されるためである。したがっ
て、Ｐ形ウェル領域２の水平断面は、正八角形もしくは
正八角形に近い形状（例えば、正八角形の角部が丸まっ
たような形状）となる。The depletion mode DMO will be described below.
A method of manufacturing S will be described with reference to FIGS. 2 and 3. First, oxide film 10 is formed on the main surface of N semiconductor substrate 1. Then, a plurality of regular octagonal openings 20 (see FIG. 4A for a side sectional view) whose horizontal section is a horizontal section as shown in FIG. 3 are formed in the oxide film 10 by, for example, ordinary photolithography technology and dry etching technology. Set up. After that, P-type impurities are diffused using the oxide film 10 as a mask, and high-temperature heat treatment is performed to form the P-type well region 2 as shown in FIG. 4A. Here, the P-type well region 2 is also formed below the oxide film 10a, but the P-type impurity is diffused laterally (that is, below the oxide film 10a) by the high temperature heat treatment. This is because. Therefore, the horizontal cross section of the P-type well region 2 is a regular octagon or a shape close to a regular octagon (for example, a shape in which the corners of the regular octagon are rounded).
【００１２】次に、酸化膜１０をマスクとして、露出し
たＰ形ウェル領域２の表面領域にソース領域形成用のＮ
形不純物を拡散することによってＮ形ソース領域３が形
成され図４（ｂ）に示す構造が得られる。すなわち、上
記Ｐ形ウェル領域２及びＮ形ソース領域３は所謂二重拡
散技術によって形成している。続いて、酸化膜１０をウ
ェットエッチング技術等によって選択的に除去する。次
に、イオン注入装置等によって、しきい値電圧を制御す
るためのＮ形不純物を、例えば、図４（ｃ）に一点鎖線
で示す深さまで注入する。このＮ形不純物の注入量によ
ってしきい値が決まる。ここで、Ｎ形不純物が注入され
ることによって、Ｎ形ソース領域３とＮ半導体基板１の
表面領域との間に介在するＰ形ウェル領域２の表面領域
は、キャリア濃度が低くなり導電形がＮ形に反転するこ
とでＮ形チャネル４が形成され、図４（ｃ）に示す構造
が得られる。Next, using the oxide film 10 as a mask, N for forming a source region is formed in the exposed surface region of the P-type well region 2.
The N-type source region 3 is formed by diffusing the N-type impurity, and the structure shown in FIG. 4B is obtained. That is, the P-type well region 2 and the N-type source region 3 are formed by the so-called double diffusion technique. Subsequently, the oxide film 10 is selectively removed by a wet etching technique or the like. Next, an N-type impurity for controlling the threshold voltage is implanted by, for example, an ion implanter to a depth shown by a chain line in FIG. 4C. The threshold value is determined by the implantation amount of the N-type impurity. Here, by implanting the N-type impurity, the surface region of the P-type well region 2 interposed between the N-type source region 3 and the surface region of the N semiconductor substrate 1 has a low carrier concentration and has a conductivity type. The N-type channel 4 is formed by inversion to the N-type, and the structure shown in FIG. 4C is obtained.
【００１３】次に、ゲート酸化膜である絶縁膜５、ゲー
ト電極６、層間絶縁膜７、ソース電極８、ドレイン電極
９それぞれを周知の技術によって形成することにより図
４（ｄ）に示す構造が得られる。以上説明したように本
ディプレッションモードＤＭＯＳでは、Ｐ形ウェル領域
２の水平断面形状を正八角形に形成するために、正八角
形のマスクを用いていることに特徴がある。Next, the insulating film 5, which is a gate oxide film, the gate electrode 6, the interlayer insulating film 7, the source electrode 8 and the drain electrode 9 are formed by known techniques to obtain the structure shown in FIG. can get. As described above, the depletion mode DMOS is characterized in that a regular octagonal mask is used to form the horizontal cross-sectional shape of the P-type well region 2 into a regular octagon.
【００１４】なお、本実施の形態では、所謂縦型構造の
ディプレッションモードＤＭＯＳについて説明したが、
縦型構造に限定するものではなく、横型構造であっても
よい。また、上記各領域の導電形のＰ形とＮ形とが逆転
した構成のものでもよいことは勿論である。Ｐ形ウェル
領域２の水平断面形状は正八角形に限定するものではな
く、コーナ部の角度が１３５度以上であれば、略多角形
でもよい（ただし、正多角形の方が加工は容易にな
る）。また、正八角形以上の角を有する正多角形にする
ことにより、よりＰ形ウェル領域２の表面領域でのＰ形
不純物濃度を均一化でき、その結果、よりＮ形チャネル
４のＮ形不純物濃度を均一化でき、しきい値電圧の温度
依存性を小さくできる。図１（ｂ））に示すコーナ部の
外接円Ａの曲率半径が１０μｍ以上であれば、更に、Ｎ
形チャネルのＮ形不純物濃度はさらに均一になり、しき
い値電圧の温度依存性は更に小さくなる。In this embodiment, the depletion mode DMOS having a so-called vertical structure has been described.
The structure is not limited to the vertical structure, but may be a horizontal structure. Further, it goes without saying that the conductivity type of each of the above regions may be reversed from the P type and the N type. The horizontal cross-sectional shape of the P-type well region 2 is not limited to a regular octagon, and may be a substantially polygonal shape as long as the corner portion has an angle of 135 degrees or more (however, the regular polygonal shape facilitates processing). ). Further, by forming a regular polygon having a regular octagon or more, the P-type impurity concentration in the surface region of the P-type well region 2 can be made more uniform, and as a result, the N-type impurity concentration of the N-type channel 4 can be further increased. Can be made uniform, and the temperature dependence of the threshold voltage can be reduced. If the radius of curvature of the circumscribed circle A of the corner portion shown in FIG.
The N-type impurity concentration of the N-type channel becomes more uniform, and the temperature dependence of the threshold voltage becomes smaller.
【００１５】また、Ｐ形ウェル領域２の水平断面形状を
略円形にすることにより、Ｐ形ウェル領域２の表面領域
でのＰ形不純物濃度を均一化できるため、Ｎ形チャネル
４におけるＮ形不純物濃度が均一になり、その結果、し
きい値電圧の温度依存性が小さくなる。さらに、円形の
場合は、コーナ部が無いのでＰ形ウェル領域２への電界
集中が無くなり、耐圧が向上するFurther, by making the horizontal cross-section of the P-type well region 2 substantially circular, the P-type impurity concentration in the surface region of the P-type well region 2 can be made uniform, so that the N-type impurity in the N-type channel 4 is formed. The concentration becomes uniform, and as a result, the temperature dependence of the threshold voltage is reduced. Further, in the case of a circular shape, since there is no corner portion, electric field concentration on the P-type well region 2 is eliminated and the breakdown voltage is improved.
【００１６】[0016]
【発明の効果】請求項１の発明は、上記目的を達成する
ために、ウェル領域の水平断面形状が、略多角形であり
且つ前記略多角形のコーナ部を形成する角度が１３５度
以上であるから、前記ウェル領域の表面領域での不純物
濃度を均一化できるため、前記チャネルにおける不純物
の濃度が均一となり、しきい値電圧の温度依存性が小さ
くなるという効果がある。その結果、チップ温度や周囲
温度が上昇してもしきい値電圧の絶対値の変動が抑制さ
れ、大きなゲート電圧が必要でなくなるという効果があ
る。According to the invention of claim 1, in order to achieve the above object, the horizontal cross-sectional shape of the well region is substantially polygonal, and the angle forming the corner portion of the substantially polygonal is 135 degrees or more. Therefore, the impurity concentration in the surface region of the well region can be made uniform, so that the impurity concentration in the channel becomes uniform and the temperature dependence of the threshold voltage is reduced. As a result, even if the chip temperature or the ambient temperature rises, fluctuations in the absolute value of the threshold voltage are suppressed, and a large gate voltage is not required.
【００１７】請求項２の発明は、請求項１の発明におい
て、ウェル領域の水平断面形状が、正多角形であるの
で、正多角形でない場合に比べて前記ウェル領域の表面
領域での不純物濃度を均一化できるため、前記チャネル
における不純物濃度が、より均一になり、その結果、し
きい値電圧の温度依存性が小さくなるという効果があ
る。According to a second aspect of the present invention, in the first aspect of the invention, since the horizontal cross-sectional shape of the well region is a regular polygon, the impurity concentration in the surface region of the well region is greater than that in the case where the well region is not a regular polygon. Can be made uniform, so that the impurity concentration in the channel becomes more uniform, and as a result, the temperature dependence of the threshold voltage is reduced.
【００１８】請求項３の発明は、請求項１又は請求項２
の発明において、コーナ部の外接円の曲率半径が１０μ
ｍ以上なので、前記ウェル領域の表面領域での不純物濃
度を更に均一化できるため、前記チャネルにおける不純
物濃度が更に均一になり、その結果、しきい値電圧の温
度依存性が小さくなるという効果がある。請求項４の発
明は、ウェル領域の形状を円形にすることにより、前記
ウェル領域の表面領域での不純物濃度を更に均一化でき
るため、前記チャネルにおける不純物濃度が均一にな
り、その結果、しきい値電圧の温度依存性が小さくなる
という効果がある。さらに、コーナ部が無いので前記ウ
ェル領域への電界集中が無くなり、耐圧が向上するとい
う効果がある。The invention of claim 3 is claim 1 or claim 2.
In the invention, the radius of curvature of the circumscribed circle of the corner portion is 10 μm.
Since it is m or more, the impurity concentration in the surface region of the well region can be made more uniform, so that the impurity concentration in the channel becomes more uniform, and as a result, the temperature dependence of the threshold voltage is reduced. . According to the fourth aspect of the present invention, by making the shape of the well region circular, the impurity concentration in the surface region of the well region can be made more uniform, so that the impurity concentration in the channel becomes uniform, and as a result, the threshold concentration is increased. This has the effect of reducing the temperature dependence of the value voltage. Further, since there is no corner portion, there is an effect that electric field concentration on the well region is eliminated and the breakdown voltage is improved.
【図１】（ａ）は本発明の実施の形態を示す半導体装置
の側断面図である。（ｂ）は同上の要部の平面図であ
る。FIG. 1A is a side sectional view of a semiconductor device showing an embodiment of the present invention. (B) is a plan view of the main part of the same.
【図２】同上の主要工程断面図である。FIG. 2 is a sectional view of a main process of the above.
【図３】同上の主要工程平面図である。FIG. 3 is a plan view of the main steps of the above.
【図４】（ａ）は従来例の半導体装置の側断面図であ
る。（ｂ）は同上の要部の平面図である。FIG. 4A is a side sectional view of a conventional semiconductor device. (B) is a plan view of the main part of the same.
１ Ｎ形半導体基板 ２ Ｐ形ウェル領域 ３ Ｎ形ソース領域 ４ Ｎ形チャネル ５ 絶縁膜 ６ ゲート電極 ７ 層間絶縁膜 ８ ソース電極 ９ ドレイン電極 1 N-type semiconductor substrate 2 P-type well region 3 N-type source region 4 N-type channel 5 insulating film 6 gate electrode 7 interlayer insulating film 8 source electrode 9 drain electrode
Claims (4)
１導電形のソース領域が形成され、前記ソース領域を囲
んで第２導電形のウェル領域が形成され、前記半導体基
板の主表面と前記ソース領域との間に介在する前記ウェ
ル領域の表面領域に第１導電形のチャネルが形成され、
前記チャネル上に絶縁膜を介してゲート電極が形成され
て成り、前記ウェル領域の水平断面形状は、略多角形で
あり且つ前記略多角形のコーナ部を形成する角度が１３
５度以上であることを特徴とする半導体装置。1. A main surface of a semiconductor substrate of the first conductivity type is formed with a source region of the first conductivity type, and a well region of the second conductivity type is formed so as to surround the source region. A channel of the first conductivity type is formed in a surface region of the well region interposed between the surface and the source region,
A gate electrode is formed on the channel via an insulating film, and the well region has a horizontal cross-sectional shape that is substantially polygonal, and an angle that forms the substantially polygonal corner portion is 13 degrees.
A semiconductor device characterized by being at least 5 degrees.
であることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the horizontal cross-sectional shape of the well region is a regular polygon.
以上であることを特徴とする請求項１又は請求項２記載
の半導体装置。3. The radius of curvature of the circumscribed circle of the corner portion is 10 μm.
It is above, The semiconductor device of Claim 1 or Claim 2 characterized by the above-mentioned.
１導電形のソース領域が形成され、前記ソース領域を囲
んで第２導電形のウェル領域が形成され、前記半導体基
板の主表面と前記ソース領域との間に介在する前記ウェ
ル領域の表面領域に第１導電形のチャネルが形成され、
前記チャネル上に絶縁膜を介してゲート電極が形成され
て成り、前記ウェル領域の水平断面形状が略円形である
ことを特徴とする半導体装置。4. A main region of the semiconductor substrate of the first conductivity type is formed with a source region of the first conductivity type, and a well region of the second conductivity type is formed so as to surround the source region. A channel of the first conductivity type is formed in a surface region of the well region interposed between the surface and the source region,
A semiconductor device, wherein a gate electrode is formed on the channel via an insulating film, and a horizontal cross-section of the well region is substantially circular.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215596A JPH09205202A (en) | 1996-01-26 | 1996-01-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215596A JPH09205202A (en) | 1996-01-26 | 1996-01-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09205202A true JPH09205202A (en) | 1997-08-05 |
Family
ID=11797581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1215596A Withdrawn JPH09205202A (en) | 1996-01-26 | 1996-01-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09205202A (en) |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002029900A3 (en) * | 2000-10-03 | 2002-10-31 | Cree Inc | Silicon carbide power mosfets having a shorting channel and methods of fabrication them |
| US6610366B2 (en) | 2000-10-03 | 2003-08-26 | Cree, Inc. | Method of N2O annealing an oxide layer on a silicon carbide layer |
| US6767843B2 (en) | 2000-10-03 | 2004-07-27 | Cree, Inc. | Method of N2O growth of an oxide layer on a silicon carbide layer |
| US6972436B2 (en) | 1998-08-28 | 2005-12-06 | Cree, Inc. | High voltage, high temperature capacitor and interconnection structures |
| US6979863B2 (en) | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
| US7022378B2 (en) | 2002-08-30 | 2006-04-04 | Cree, Inc. | Nitrogen passivation of interface states in SiO2/SiC structures |
| US7067176B2 (en) | 2000-10-03 | 2006-06-27 | Cree, Inc. | Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment |
| US7074643B2 (en) | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
| US7118970B2 (en) | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
| US7414268B2 (en) | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
| US7485924B2 (en) | 2005-08-31 | 2009-02-03 | Sharp Kabushiki Kaisha | Lateral double-diffused field effect transistor and integrated circuit having same |
| US7528040B2 (en) | 2005-05-24 | 2009-05-05 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
| US7615801B2 (en) | 2005-05-18 | 2009-11-10 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
| US7727904B2 (en) | 2005-09-16 | 2010-06-01 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
| US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
| US9029945B2 (en) | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
| US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9231122B2 (en) | 2011-09-11 | 2016-01-05 | Cree, Inc. | Schottky diode |
| US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
| CN105990407A (en) * | 2015-01-30 | 2016-10-05 | 张家港意发功率半导体有限公司 | IGBT cellular structure and manufacturing process thereof |
| US9548374B2 (en) | 2006-08-17 | 2017-01-17 | Cree, Inc. | High power insulated gate bipolar transistors |
| US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
| US9640652B2 (en) | 2009-03-27 | 2017-05-02 | Cree, Inc. | Semiconductor devices including epitaxial layers and related methods |
| US9673283B2 (en) | 2011-05-06 | 2017-06-06 | Cree, Inc. | Power module for supporting high current densities |
| US9984894B2 (en) | 2011-08-03 | 2018-05-29 | Cree, Inc. | Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions |
-
1996
- 1996-01-26 JP JP1215596A patent/JPH09205202A/en not_active Withdrawn
Cited By (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972436B2 (en) | 1998-08-28 | 2005-12-06 | Cree, Inc. | High voltage, high temperature capacitor and interconnection structures |
| US6998322B2 (en) | 1998-08-28 | 2006-02-14 | Cree, Inc. | Methods of fabricating high voltage, high temperature capacitor and interconnection structures |
| US6610366B2 (en) | 2000-10-03 | 2003-08-26 | Cree, Inc. | Method of N2O annealing an oxide layer on a silicon carbide layer |
| US6767843B2 (en) | 2000-10-03 | 2004-07-27 | Cree, Inc. | Method of N2O growth of an oxide layer on a silicon carbide layer |
| US6956238B2 (en) | 2000-10-03 | 2005-10-18 | Cree, Inc. | Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel |
| US7067176B2 (en) | 2000-10-03 | 2006-06-27 | Cree, Inc. | Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment |
| WO2002029900A3 (en) * | 2000-10-03 | 2002-10-31 | Cree Inc | Silicon carbide power mosfets having a shorting channel and methods of fabrication them |
| US7022378B2 (en) | 2002-08-30 | 2006-04-04 | Cree, Inc. | Nitrogen passivation of interface states in SiO2/SiC structures |
| US7381992B2 (en) | 2003-04-24 | 2008-06-03 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions |
| US6979863B2 (en) | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
| US7074643B2 (en) | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
| US7118970B2 (en) | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
| US7705362B2 (en) | 2004-06-22 | 2010-04-27 | Cree, Inc. | Silicon carbide devices with hybrid well regions |
| US7414268B2 (en) | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
| US7615801B2 (en) | 2005-05-18 | 2009-11-10 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
| US7528040B2 (en) | 2005-05-24 | 2009-05-05 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
| US8188483B2 (en) | 2005-05-24 | 2012-05-29 | Cree, Inc. | Silicon carbide devices having smooth channels |
| US9142663B2 (en) | 2005-05-24 | 2015-09-22 | Cree, Inc. | Silicon carbide devices having smooth channels |
| US8859366B2 (en) | 2005-05-24 | 2014-10-14 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
| US7485924B2 (en) | 2005-08-31 | 2009-02-03 | Sharp Kabushiki Kaisha | Lateral double-diffused field effect transistor and integrated circuit having same |
| US7727904B2 (en) | 2005-09-16 | 2010-06-01 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
| US8536066B2 (en) | 2005-09-16 | 2013-09-17 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
| US9548374B2 (en) | 2006-08-17 | 2017-01-17 | Cree, Inc. | High power insulated gate bipolar transistors |
| US9064840B2 (en) | 2007-02-27 | 2015-06-23 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
| US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
| US9640652B2 (en) | 2009-03-27 | 2017-05-02 | Cree, Inc. | Semiconductor devices including epitaxial layers and related methods |
| US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
| US9595618B2 (en) | 2010-03-08 | 2017-03-14 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
| US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9029945B2 (en) | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9673283B2 (en) | 2011-05-06 | 2017-06-06 | Cree, Inc. | Power module for supporting high current densities |
| US9984894B2 (en) | 2011-08-03 | 2018-05-29 | Cree, Inc. | Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions |
| US9231122B2 (en) | 2011-09-11 | 2016-01-05 | Cree, Inc. | Schottky diode |
| US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
| US9865750B2 (en) | 2011-09-11 | 2018-01-09 | Cree, Inc. | Schottky diode |
| US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
| US10141302B2 (en) | 2011-09-11 | 2018-11-27 | Cree, Inc. | High current, low switching loss SiC power module |
| US10153364B2 (en) | 2011-09-11 | 2018-12-11 | Cree, Inc. | Power module having a switch module for supporting high current densities |
| US11024731B2 (en) | 2011-09-11 | 2021-06-01 | Cree, Inc. | Power module for supporting high current densities |
| US11171229B2 (en) | 2011-09-11 | 2021-11-09 | Cree, Inc. | Low switching loss high performance power module |
| CN105990407A (en) * | 2015-01-30 | 2016-10-05 | 张家港意发功率半导体有限公司 | IGBT cellular structure and manufacturing process thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH09205202A (en) | Semiconductor device | |
| JPH01183856A (en) | Double diffusion type field-effect semiconductor device and manufacture thereof | |
| JPH11214529A (en) | Integration of mos device and semiconductor chip | |
| KR100238699B1 (en) | Soi type mos transistor | |
| KR101099560B1 (en) | Method for manufacturing high voltage transistor | |
| KR0165381B1 (en) | High voltage mosfet manufacturing method | |
| JP2001274383A (en) | Semiconductor device and manufacturing method | |
| JPH10256534A (en) | Semiconductor device with dmos structure and its manufacture | |
| KR20050104163A (en) | High voltage transistor and method of fabricating the same | |
| KR100935249B1 (en) | High Voltage Device and Method for the same | |
| KR20040051669A (en) | Method of manufacturing DMOS transistor in semiconductor device | |
| JPH0479336A (en) | Production of semiconductor device | |
| KR950002184B1 (en) | Manufacturing method for semiconductor memory device | |
| KR100244478B1 (en) | Manufacturing method for compact mask rom | |
| JPH0691250B2 (en) | Semiconductor device | |
| KR100225383B1 (en) | Method of manufacturing semiconductor device | |
| KR20050066901A (en) | Mos transistor having low junction capacitance and method for fabricating the same | |
| KR0165348B1 (en) | Method for manufacturing mos transistor | |
| JPH0344076A (en) | Manufacture of semiconductor device | |
| JPH03151669A (en) | Manufacture of semiconductor device | |
| KR20040006772A (en) | Method for fabricating semiconductor device | |
| KR20030002660A (en) | Manufacturing method for semiconductor device | |
| JPS61253865A (en) | Manufacture of semiconductor device | |
| JPS6260265A (en) | Manufacture of semiconductor device | |
| JPH01189173A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030401 |