JPH09153661A - Wiring board and manufacture thereof - Google Patents

Wiring board and manufacture thereof

Info

Publication number
JPH09153661A
JPH09153661A JP7313815A JP31381595A JPH09153661A JP H09153661 A JPH09153661 A JP H09153661A JP 7313815 A JP7313815 A JP 7313815A JP 31381595 A JP31381595 A JP 31381595A JP H09153661 A JPH09153661 A JP H09153661A
Authority
JP
Japan
Prior art keywords
copper foil
wiring board
insulating adhesive
etching
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7313815A
Other languages
Japanese (ja)
Inventor
Kazuyuki Tazawa
和幸 田沢
Haruo Ogino
晴夫 荻野
義之 ▲つる▼
Yoshiyuki Tsuru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP7313815A priority Critical patent/JPH09153661A/en
Publication of JPH09153661A publication Critical patent/JPH09153661A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To make it possible to simply and efficiently manufacture a wiring board excellent in low profile by forming recesses in chip components on a multilayer wiring board having via holes or in places of installation of board securing screws. SOLUTION: Insulating adhesive is applied to the copper foil to form insulating adhesive layers with the copper foil. The adhesive surfaces of such insulating adhesive layers with copper foil are superposed in such a manner that they are in contact with inner circuits, and they are laminated and integrated by application of heat and pressure. The insulating adhesive layer of the obtained laminated board is selectively etched and removed to form recesses. Further, the entire surface of the workpiece is subjected to electroless plating, and the unnecessary copper foil is selectively etched and removed to obtain this wiring board. The recesses can be formed by removing the outermost wiring layer and the insulating layer supporting the wiring layer, and the inner circuits exposed in the recesses and the circuit in the outermost layer can be connected with each other by plating.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、配線板とその製造
法に関する。
TECHNICAL FIELD The present invention relates to a wiring board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、多層配線板の高密度化、薄型化が
進展し、ガラスクロスを使用しない多層配線板製造法が
検討されており、隣接する配線層のみ接続を行う、いわ
ゆるインタースティシャルバイアホール(以下、IVH
という。)を形成する方法が種々検討されている すなわち、ガラスクロスを使用しないことにより絶縁層
の厚さを抑制し、隣接する配線層のみの接続により、接
続層以外の回路層の配線面積が増加するものである。こ
のようなバイアホールを有する配線板は、特開昭58−
64097号公報、特開平4−148590号公報に記
載され、図2に示すように、複数の絶縁層と、複数の配
線層と、少なくとも隣接する配線層の接続を行うバイア
ホールを有する多層配線板が記載されている。
2. Description of the Related Art In recent years, multilayer wiring boards have been made higher in density and thinner, and a method for manufacturing a multilayer wiring board without using glass cloth has been studied. A so-called interstitial for connecting only adjacent wiring layers. Via hole (hereinafter IVH
That. ) Are being studied. That is, the thickness of the insulating layer is suppressed by not using glass cloth, and the wiring area of the circuit layers other than the connection layer is increased by connecting only the adjacent wiring layers. It is a thing. A wiring board having such a via hole is disclosed in JP-A-58-58.
As described in Japanese Patent Laid-Open No. 64097 and Japanese Patent Laid-Open No. 4-148590, and as shown in FIG. 2, a multilayer wiring board having a plurality of insulating layers, a plurality of wiring layers, and via holes for connecting at least adjacent wiring layers. Is listed.

【0003】また、内層回路上に絶縁性樹脂層と、その
上にさらに金属層を形成し、その金属層のバイアホール
を形成する箇所を選択的にエッチング除去し、その除去
した箇所に露出した絶縁性樹脂層をケミカルエッチング
し、穴内壁を金属化して、バイアホールを形成する方法
が、特開平4−148590号公報、特開平5−259
649号公報等に開示されている。このうち、特開平5
−259649号公報には、絶縁性樹脂にアルカリ溶解
性樹脂を用い、ケミカルエッチング液としてアルカリを
用いることが記載され、特開平4−148590号公報
には、絶縁性樹脂にチバ・ガイギー社製の感光性エポキ
シ樹脂 Probimer 52を用い、ケミカルエッチング液と
してチバ・ガイギー社製の現像剤DY90(プロピレン
カーボネート、シクロヘキサノン及びガンマブチルラク
トンの混液)を用いることが記載されている。
Further, an insulating resin layer and a metal layer are further formed on the inner layer circuit, and a portion of the metal layer where a via hole is formed is selectively removed by etching, and the exposed portion is exposed. A method of chemically etching the insulating resin layer to metallize the inner wall of the hole to form a via hole is disclosed in JP-A-4-148590 and JP-A-5-259.
No. 649, etc. Of these, JP-A-5
JP-A-259649 describes that an alkali-soluble resin is used as an insulating resin and an alkali is used as a chemical etching liquid. JP-A-4-148590 discloses an insulating resin manufactured by Ciba-Geigy. It is described that a photosensitive epoxy resin Probimer 52 is used and a developer DY90 (mixed solution of propylene carbonate, cyclohexanone and gammabutyrolactone) manufactured by Ciba-Geigy is used as a chemical etching solution.

【0004】[0004]

【発明が解決しようとする課題】ところで、最近では、
電子機器、特にビデオカメラやノートパソコン等のよう
に、薄型化がより一層求められるようになってきてお
り、従来の特開昭58−64097号公報に記載されて
いるような、バイアホールを有する多層配線板では、対
応できなくなっている。
By the way, recently,
There is an increasing demand for thinner electronic devices such as video cameras and notebook computers, and they have via holes as described in Japanese Patent Application Laid-Open No. 58-64097. Multi-layer wiring boards are no longer available.

【0005】本発明は、薄型化に優れた配線板と、その
ような配線板を簡便に、より効率良く製造する方法を提
供することを目的とする。
An object of the present invention is to provide a wiring board excellent in thinning and a method for manufacturing such a wiring board simply and efficiently.

【0006】[0006]

【課題を解決するための手段】本発明の配線板は、複数
の絶縁層と、複数の配線層と、少なくとも隣接する配線
層の接続を行うバイアホールを有する多層配線板におい
て、チップ部品あるいは基板固定用螺子の搭載部分に、
凹部を有することを特徴とする。
A wiring board according to the present invention is a multilayer wiring board having a plurality of insulating layers, a plurality of wiring layers, and via holes for connecting at least adjacent wiring layers. On the mounting part of the fixing screw,
It is characterized by having a recess.

【0007】このような配線板は、銅箔に絶縁性接着剤
を塗布した銅箔付絶縁性接着層の、凹部を形成する箇所
に予め穴をあけ、その穴をあけた銅箔付絶縁性接着層の
接着剤面を内層回路側に接触するように重ね、加熱加圧
して積層一体化し、その積層一体化した積層板全面に無
電解めっきを行い、不要な箇所の銅箔を選択的にエッチ
ング除去することによって製造することができる。
In such a wiring board, a copper foil is coated with an insulating adhesive, and an insulating adhesive layer with a copper foil is preliminarily provided with holes at the portions where the recesses are to be formed. The adhesive side of the adhesive layer is laminated so as to contact the inner layer circuit side, and heat and pressure are applied to laminate and integrate, and electroless plating is performed on the entire surface of the laminate in which the laminate is integrated to selectively remove copper foil at unnecessary locations. It can be manufactured by etching away.

【0008】[0008]

【発明の実施の形態】また、銅箔に絶縁性接着剤を塗布
した銅箔付絶縁性接着層の接着剤面を、内層回路側に接
触するように重ね、加熱加圧して積層一体化し、その積
層一体化した積層板の凹部を形成する箇所の絶縁性接着
層を選択的にエッチング除去し、さらに全面に無電解め
っきを行い、不要な箇所の銅箔を選択的にエッチング除
去することによっても製造することができる。
BEST MODE FOR CARRYING OUT THE INVENTION Further, the adhesive surface of an insulating adhesive layer with a copper foil, which is obtained by applying an insulating adhesive to a copper foil, is laminated so as to be in contact with the inner layer circuit side, and is heated and pressed to be laminated and integrated. By selectively etching away the insulating adhesive layer at the place where the concave portion of the laminated integrated laminate is formed, and further performing electroless plating on the entire surface, and selectively removing the copper foil at unnecessary places by etching Can also be manufactured.

【0009】本発明の凹部は、図1に示すように、最外
層の配線層とそれを支持する絶縁層を除去して形成する
ことができ、この凹部に露出した内層回路と、最外層の
回路が、めっきによって接続することができる。
As shown in FIG. 1, the recess of the present invention can be formed by removing the outermost wiring layer and the insulating layer supporting it, and the inner layer circuit exposed in the recess and the outermost layer can be formed. Circuits can be connected by plating.

【0010】本発明に用いる銅箔に絶縁性接着剤を塗布
した銅箔付絶縁性接着層は、銅箔にプリント配線板もし
くは多層配線板で一般的に使用される電解銅箔、圧延銅
箔、極薄銅箔、Niを中央に挟んだ3層銅箔等が使用で
きる。この絶縁性接着剤には、二官能エポキシ樹脂とハ
ロゲン化二官能フェノール類の配合当量比をエポキシ基
/フェノール水酸基=1:0.9〜1.1とし、触媒の
存在下、加熱して重合させたフィルム形成能を有する分
子量100,000以上のハロゲン化高分子量エポキシ
重合体及び架橋剤、多官能エポキシ樹脂を構成成分とす
る熱硬化性エポキシ接着フィルムが使用できる。また、
ハロゲン化高分子エポキシ重合体に替えて、ブロム化フ
ェノキシ樹脂を使用した熱硬化性エポキシ接着樹脂絶縁
層も使用可能である。
The insulating adhesive layer with a copper foil obtained by applying an insulating adhesive to the copper foil used in the present invention is an electrolytic copper foil or a rolled copper foil generally used in a printed wiring board or a multilayer wiring board. An ultra-thin copper foil, a three-layer copper foil having Ni in the center can be used. In this insulating adhesive, the compounding equivalence ratio of the bifunctional epoxy resin and the halogenated bifunctional phenol is set to epoxy group / phenolic hydroxyl group = 1: 0.9 to 1.1, and heated to polymerize in the presence of a catalyst. A thermosetting epoxy adhesive film containing a halogenated high molecular weight epoxy polymer having a molecular weight of 100,000 or more, a cross-linking agent, and a polyfunctional epoxy resin having the above film-forming ability can be used. Also,
A thermosetting epoxy adhesive resin insulating layer using a brominated phenoxy resin can be used instead of the halogenated high molecular weight epoxy polymer.

【0011】凹部を形成する箇所に、予め穴をあけるた
めには、大面積もしくは複雑形状部では、歯型による打
ち抜きが最適である。円形では、ドリルによる穴あけも
適用できる。炭化による絶縁低下が問題にならない回路
仕様もしくは炭化物の除去が後プロセスで可能であるな
らば、レーザ加工も可能である。
In order to preliminarily form a hole in a portion where a concave portion is to be formed, punching with a tooth mold is most suitable for a large area or a complicated shape portion. With a circular shape, drilling can also be applied. Laser processing is also possible if the circuit specifications or the removal of carbide can be done in a post process where insulation degradation due to carbonization is not a problem.

【0012】その穴をあけた銅箔付絶縁性接着層の接着
剤面を内層回路側に接触するように重ね、加熱加圧して
積層一体化するには、クッションプレス法が必須ではな
いが、絶縁性接着剤層の樹脂の流動をほぼ抑制するとい
う点で最適である。絶縁性接着剤層の樹脂流動が、実質
上無視できる特性である場合もしくは無視できる凹部設
計仕様の場合には、鏡板プレス法も可能である。クッシ
ョン材としては、テドラ(デュポン社製、商品名)やT
PXフィルム(三井石油化学工業株式会社製、商品名)
等の耐熱性離型フィルムとポリエチレン、ポリプロピレ
ン等の熱可塑性フィルムの組み合わせが使用可能であ
る。また、ノボン(チッソ株式会社製、商品名)フィル
ム等の水溶性熱可塑性フィルムも使用できる。
The cushion press method is not essential for stacking the adhesive surface of the copper foil-insulating insulating adhesive layer so as to contact the inner layer circuit side and heating and pressurizing to laminate and integrate the layers. It is optimal in that it substantially suppresses the resin flow of the insulating adhesive layer. If the resin flow of the insulating adhesive layer has substantially negligible characteristics or has negligible recess design specifications, the end plate pressing method is also possible. Cushion materials include Tedra (trade name of DuPont) and T
PX film (Mitsui Petrochemical Industry Co., Ltd., trade name)
It is possible to use a combination of a heat-resistant release film such as and a thermoplastic film such as polyethylene and polypropylene. Further, a water-soluble thermoplastic film such as Nobon (manufactured by Chisso Corporation, trade name) film can also be used.

【0013】その積層一体化した積層板全面に無電解め
っきを行うには、CC−41等の厚付け無電解めっきが
使用できる。また、無電解めっきと電解めっきを併用す
る場合には、CUST−201(日立化成工業株式会社
製、商品名)等の下地無電解銅めっきもしくは無電解め
っき液CC−41(日立化成工業株式会社製、商品名)
等の厚付け無電解銅めっきが使用できる。電解銅めっき
としては、硫酸銅めっきやピロ燐酸銅めっきが使用でき
る。
To carry out electroless plating on the entire surface of the laminated and integrated laminated plate, thick electroless plating such as CC-41 can be used. When electroless plating and electrolytic plating are used in combination, a base electroless copper plating such as CUST-201 (manufactured by Hitachi Chemical Co., Ltd., trade name) or an electroless plating solution CC-41 (Hitachi Chemical Co., Ltd.) (Product name)
It is possible to use thick electroless copper plating. As the electrolytic copper plating, copper sulfate plating or copper pyrophosphate plating can be used.

【0014】不要な箇所の銅箔を選択的にエッチング除
去するには、プリント配線板の一般的な技術である。ド
ライフィルムによる露光・現像・エッチングによる銅箔
のエッチング除去ができる。エッチング液には塩化第二
鉄、塩化第二銅、アルカリのどれもが使用可能であり、
それぞれに適したドライフィルムが使用可能である。ま
た、NCルータによる銅箔の切削除去も可能である。
It is a general technique for printed wiring boards to selectively remove copper foil at unnecessary portions by etching. The copper foil can be removed by etching by exposing, developing and etching with a dry film. Any of ferric chloride, cupric chloride and alkali can be used as the etching solution,
A dry film suitable for each can be used. It is also possible to cut and remove the copper foil with an NC router.

【0015】また、銅箔に絶縁性接着剤を塗布した銅箔
付絶縁性接着層の接着剤面を内層回路側に接触するよう
に重ね、加熱加圧して積層一体化し、その積層一体化し
た積層板の凹部を形成する箇所の絶縁性接着層を選択的
にエッチング除去するには、内層回路基板の樹脂と絶縁
性接着剤層の樹脂との選択エッチング性が必要であり、
濃硫酸は不敵である。前述の高分子エポキシ重合体を配
合した絶縁性接着剤を用いた場合は、アミド系溶媒、ア
ルカリ金属化合物、アルコール系溶媒よりなるエッチン
グ液に浸漬することにより、エポキシ基板、ポリイミド
基板系基板及びBT基板において選択エッチング性が得
られ、絶縁樹脂層のエッチングができる。
Further, the insulating adhesive layer of the copper foil coated with an insulating adhesive is laminated so that the adhesive surface of the copper foil is in contact with the inner circuit side, heated and pressed to be laminated and integrated, and the laminated and integrated. In order to selectively remove the insulating adhesive layer at the location where the concave portion of the laminate is to be formed by etching, it is necessary to have selective etching properties between the resin of the inner layer circuit board and the resin of the insulating adhesive layer,
Concentrated sulfuric acid is invincible. When the insulating adhesive compounded with the above-mentioned high molecular weight epoxy polymer is used, the epoxy substrate, the polyimide substrate system substrate and the BT substrate are prepared by immersing the insulating adhesive in an etching solution composed of an amide solvent, an alkali metal compound and an alcohol solvent. Selective etching is obtained on the substrate, and the insulating resin layer can be etched.

【0016】[0016]

【実施例】【Example】

実施例1 図3(a)に示すように、銅張り積層板E−67(日立
化成工業株式会社製、商品名)の両面に、エッチングレ
ジストを形成し、エッチングレジストから露出した銅箔
を、塩化第二鉄/塩酸を主体とする化学エッチング液を
噴霧して、選択的にエッチング除去し、内層回路板を作
成した。次に、図3(b)に示すように、厚さ18μm
の銅箔に、高分子エポキシ重合体を特徴的に配合した絶
縁性接着剤であるAS−3000(日立化成工業株式会
社製、商品名)のワニスを、アプリケータで塗布し、1
30℃、10分間の条件で乾燥し、図3(c)に示すよ
うに、半硬化状態とした銅箔付絶縁性接着層の、凹部を
形成する箇所に、数値制御式ドリルマシンで穴をあけ、
図3(d)に示すように、その穴をあけた銅箔付絶縁性
接着層の接着剤面を、前記内層回路板の内層回路側に接
触するように重ね、図3(e)に示すように、保持温度
175℃、保持時間45分間、圧力2.5MPaの条件
で、加熱加圧して積層一体化し、図3(f)に示すよう
に、その積層一体化した積層板の必要な箇所にスルーホ
ールとなる穴をあけ、図3(g)に示すように、穴をあ
けた積層板を、CC−41めっき液(日立化成工業株式
会社製、商品名)に、70℃、18時間の条件で、浸漬
し、無電解めっきを行い、図3(h)に示すように、そ
の表面に、エッチングレジストを形成し、エッチングレ
ジストから露出した不要な箇所の銅箔を、選択的にエッ
チング除去して、配線板を製造した。この配線板の凹部
は、図3(h)に示すように、深さが0.05mm、幅
0.5mm、長さ1.0mmのものであった。また、ビ
ス止めする箇所は、直径1.5mmの範囲で、深さが
0.10mmの凹部となった。
Example 1 As shown in FIG. 3A, an etching resist was formed on both surfaces of a copper-clad laminate E-67 (manufactured by Hitachi Chemical Co., Ltd.), and a copper foil exposed from the etching resist was removed. A chemical etching solution mainly composed of ferric chloride / hydrochloric acid was sprayed and selectively removed by etching to prepare an inner layer circuit board. Next, as shown in FIG. 3B, the thickness is 18 μm.
A copper varnish of AS-3000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an insulating adhesive in which a high molecular epoxy polymer is characteristically blended, is applied to the copper foil with an applicator, and 1
After drying at 30 ° C. for 10 minutes, as shown in FIG. 3 (c), a hole is formed by a numerical control type drill machine in the semi-cured state of the insulating adhesive layer with copper foil where the recess is to be formed. Open
As shown in FIG. 3 (d), the adhesive surface of the copper foil-insulated insulating adhesive layer is laid so as to contact the inner layer circuit side of the inner layer circuit board, as shown in FIG. 3 (e). As shown in FIG. 3 (f), necessary portions of the laminated plate are integrated by heating and pressurizing under the conditions of a holding temperature of 175 ° C., a holding time of 45 minutes, and a pressure of 2.5 MPa. A hole to be a through hole is formed in the plate, and as shown in FIG. 3 (g), the laminated plate is formed in a CC-41 plating solution (Hitachi Chemical Co., Ltd., trade name) at 70 ° C. for 18 hours. Under the conditions, electroless plating is performed, and as shown in FIG. 3 (h), an etching resist is formed on the surface of the copper foil, and unnecessary portions of the copper foil exposed from the etching resist are selectively etched. After removal, a wiring board was manufactured. The recess of this wiring board had a depth of 0.05 mm, a width of 0.5 mm, and a length of 1.0 mm, as shown in FIG. The place where the screw was fastened was a recess having a diameter of 1.5 mm and a depth of 0.10 mm.

【0017】実施例2 実施例1と同様にして、図4(a)に示すように内層回
路板を作成した。次に、図4(b)に示すように、厚さ
18μmの銅箔に、絶縁性接着剤であるAS−3000
(日立化成工業株式会社製、商品名)フィルムを130
℃、2MPa、5分間の条件でプレスして銅箔付絶縁性
接着層を得た。次に、図4(c)に示すように、この銅
箔付絶縁性接着層の接着剤面を、前記内層回路板の内層
回路側に接触するように重ね、175℃、45分間、圧
力2.5MPaの条件で、加熱加圧して積層一体化し、
その積層一体化した積層板の必要な箇所に、数値制御式
ドリルマシンでスルーホールとなる穴をあけ、さらに積
層板の凹部を形成する箇所の絶縁性接着層を以下の組成
のケミカルエッチング液に60℃で30分間浸漬して、
選択的にエッチング除去した。 (ケミカルエッチング液の組成) ・N−メチル−2−ピロリドン・・・・・・・・・・・・・・・・81重量% ・水酸化カリウム・・・・・・・・・・・・・・・・・・・・・2.7重量% ・メチルアルコール・・・・・・・・・・・・・・・・・・・・6.3重量% ・水・・・・・・・・・・・・・・・・・・・・・・・・・・・・10重量% さらに、水酸化ナトリウム40g/l、過マンガン酸カ
リウム60g/lの溶液に、60℃で10分間浸漬し、
スミア処理を行った後、CC−41めっき液(日立化成
工業株式会社製、商品名)に、70℃で18時間浸漬
し、全面に無電解めっきを行い、真空ロールラミネータ
によるラミネートに引き続き真空クッション材プレス
(130℃、10分間)によりエッチングレジストを形
成し、露出・現像によりレジスト像を形成し、エッチン
グレジストから露出した不要な箇所の銅箔を、選択的に
エッチング除去して、配線板を作成した。この配線板の
凹部は、図4(h)に示すように、深さが0.05m
m、幅0.5mm、長さ1.0mmのものであった。ま
た、ビス止めする箇所は、直径1.5mmの範囲で、深
さが0.10mmの凹部となった。
Example 2 In the same manner as in Example 1, an inner layer circuit board was prepared as shown in FIG. Next, as shown in FIG. 4 (b), AS-3000 which is an insulating adhesive is applied to a copper foil having a thickness of 18 μm.
(Hitachi Chemical Co., Ltd., trade name) Film 130
The insulating adhesive layer with a copper foil was obtained by pressing at a temperature of 2 ° C. for 2 minutes. Next, as shown in FIG. 4 (c), the adhesive surface of the insulating adhesive layer with a copper foil is stacked so as to be in contact with the inner layer circuit side of the inner layer circuit board, and the pressure is 2 at 175 ° C. for 45 minutes. Under the condition of 0.5 MPa, heating and pressurizing to laminate and integrate,
A hole that will be a through hole is made with a numerically controlled drill machine at the required place of the laminated and integrated laminated plate, and the insulating adhesive layer at the place where the concave portion of the laminated plate is formed is changed to a chemical etching solution of the following composition. Immerse at 60 ℃ for 30 minutes,
It was selectively removed by etching. (Composition of chemical etching liquid) ・ N-methyl-2-pyrrolidone ・ 81% by weight ・ Potassium hydroxide ・ ・ ・ ・・ ・ ・ ・ ・ ・ ・ 2.7% by weight ・ Methyl alcohol ・ ・ ・ ・ ・ 6.3% by weight ・ Water ・ ・ ・ ・··································································· Forty-minute solution of sodium hydroxide 40 g / l and potassium permanganate 60 g / l Soak,
After smearing, it is dipped in CC-41 plating solution (Hitachi Chemical Co., Ltd., trade name) for 18 hours at 70 ° C., electroless plating is performed on the entire surface, and lamination with a vacuum roll laminator is followed by vacuum cushioning. An etching resist is formed by material pressing (130 ° C., 10 minutes), a resist image is formed by exposure and development, and unnecessary portions of the copper foil exposed from the etching resist are selectively removed by etching to form a wiring board. Created. The concave portion of this wiring board has a depth of 0.05 m as shown in FIG.
m, width 0.5 mm, length 1.0 mm. The place where the screw was fastened was a recess having a diameter of 1.5 mm and a depth of 0.10 mm.

【0018】[0018]

【発明の効果】以上に説明したように、本発明によっ
て、薄型化に優れた配線板と、このような配線板を簡便
に、かつ効率に優れた配線板の製造法を提供することが
できる。
As described above, according to the present invention, it is possible to provide a wiring board excellent in thinning and a method of manufacturing such a wiring board simply and efficiently. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】従来のバイアホール付配線板の一実施例を示す
断面図である。
FIG. 2 is a sectional view showing an example of a conventional wiring board with a via hole.

【図3】(a)〜(h)は、それぞれ本発明の一実施例
を説明するための各工程における断面図である。
3 (a) to 3 (h) are cross-sectional views in each step for explaining one embodiment of the present invention.

【図4】(a)〜(h)は、それぞれ本発明の他の実施
例を説明するための各工程における断面図である。
4A to 4H are cross-sectional views in each step for explaining another embodiment of the present invention.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/46 H05K 3/46 Q ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H05K 3/46 H05K 3/46 Q

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】複数の絶縁層と、複数の配線層と、少なく
とも隣接する配線層の接続を行うバイアホールを有する
多層配線板において、チップ部品あるいは基板固定用螺
子の搭載部分に、凹部を有することを特徴とする配線
板。
1. A multilayer wiring board having a plurality of insulating layers, a plurality of wiring layers, and via holes for connecting at least adjacent wiring layers, wherein a recess is provided in a mounting portion of a chip component or a board fixing screw. A wiring board characterized by the above.
【請求項2】凹部が、最外層の配線層とそれを支持する
絶縁層を除去したものであることを特徴とする請求項1
に記載の配線板。
2. The recess is formed by removing the outermost wiring layer and the insulating layer supporting it.
The wiring board described in.
【請求項3】凹部に露出した内層回路と、最外層の回路
が、めっきによって接続されていることを特徴とする請
求項1または2に記載の配線板。
3. The wiring board according to claim 1, wherein the inner layer circuit exposed in the recess and the outermost layer circuit are connected by plating.
【請求項4】銅箔に絶縁性接着剤を塗布した銅箔付絶縁
性接着層の、凹部を形成する箇所に予め穴をあけ、その
穴をあけた銅箔付絶縁性接着層の接着剤面を内層回路側
に接触するように重ね、加熱加圧して積層一体化し、そ
の積層一体化した積層板全面に、無電解めっきもしくは
無電解めっき及び電解めっきを行い、不要な箇所の銅箔
を選択的にエッチング除去することを特徴とする配線板
の製造法。
4. An adhesive for an insulating adhesive layer with a copper foil in which a hole is formed in advance in a place where a recess is formed in an insulating adhesive layer with a copper foil, which is obtained by applying an insulating adhesive to a copper foil. Stack the surfaces so that they contact the inner layer circuit side, heat and pressurize to laminate and integrate, and then perform electroless plating or electroless plating and electrolytic plating on the entire surface of the laminated and integrated laminate to remove unnecessary copper foil. A method of manufacturing a wiring board, characterized by selectively removing by etching.
【請求項5】絶縁性接着剤が、高分子エポキシ重合体で
あることを特徴とする請求項4に記載の配線板の製造
法。
5. The method for manufacturing a wiring board according to claim 4, wherein the insulating adhesive is a high molecular weight epoxy polymer.
【請求項6】銅箔に絶縁性接着剤を塗布した銅箔付絶縁
性接着層の接着剤面を内層回路側に接触するように重
ね、加熱加圧して積層一体化し、その積層一体化した積
層板の凹部を形成する箇所の銅箔を選択的にエッチング
除去した後、銅箔をエッチング除去した箇所に、露出し
た絶縁性接着層を選択的にエッチング除去し、さらに全
面に無電解めっきを行い、不要な箇所の銅箔を選択的に
エッチング除去することを特徴とする請求項1、2また
は3に記載の配線板の製造法。
6. An insulating adhesive layer with a copper foil, which is obtained by applying an insulating adhesive to a copper foil, is laminated so that the adhesive surface of the copper foil is in contact with the inner layer circuit side, and is heated and pressed to be laminated and integrated. After selectively etching away the copper foil at the place where the concave part of the laminated plate is formed, the exposed insulating adhesive layer is selectively removed by etching at the place where the copper foil is removed by etching, and further electroless plating is performed on the entire surface. The method of manufacturing a wiring board according to claim 1, 2 or 3, wherein the copper foil is selectively removed by etching at unnecessary portions.
JP7313815A 1995-12-01 1995-12-01 Wiring board and manufacture thereof Pending JPH09153661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7313815A JPH09153661A (en) 1995-12-01 1995-12-01 Wiring board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7313815A JPH09153661A (en) 1995-12-01 1995-12-01 Wiring board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH09153661A true JPH09153661A (en) 1997-06-10

Family

ID=18045852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7313815A Pending JPH09153661A (en) 1995-12-01 1995-12-01 Wiring board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH09153661A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002266087A (en) * 2001-03-07 2002-09-18 Hitachi Chem Co Ltd Etchant for copper and method for manufacturing printed circuit board using the same
EP1209959A3 (en) * 2000-11-27 2004-03-10 Matsushita Electric Works, Ltd. Multilayer circuit board and method of manufacturing the same
JP2007067243A (en) * 2005-08-31 2007-03-15 Sony Corp Circuit board and electronic apparatus
WO2008120280A1 (en) * 2007-03-29 2008-10-09 Fujitsu Limited Distortion reduction fixing structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209959A3 (en) * 2000-11-27 2004-03-10 Matsushita Electric Works, Ltd. Multilayer circuit board and method of manufacturing the same
US6833511B2 (en) 2000-11-27 2004-12-21 Matsushita Electric Works, Ltd. Multilayer circuit board and method of manufacturing the same
JP2002266087A (en) * 2001-03-07 2002-09-18 Hitachi Chem Co Ltd Etchant for copper and method for manufacturing printed circuit board using the same
JP2007067243A (en) * 2005-08-31 2007-03-15 Sony Corp Circuit board and electronic apparatus
WO2008120280A1 (en) * 2007-03-29 2008-10-09 Fujitsu Limited Distortion reduction fixing structure
JPWO2008120280A1 (en) * 2007-03-29 2010-07-15 富士通株式会社 Strain reduction fixed structure
US7978475B2 (en) 2007-03-29 2011-07-12 Fujitsu Limited Strain reduction fixing structure
JP5363308B2 (en) * 2007-03-29 2013-12-11 富士通株式会社 Semiconductor mounting structure

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