JPH09153582A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH09153582A JPH09153582A JP7312999A JP31299995A JPH09153582A JP H09153582 A JPH09153582 A JP H09153582A JP 7312999 A JP7312999 A JP 7312999A JP 31299995 A JP31299995 A JP 31299995A JP H09153582 A JPH09153582 A JP H09153582A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- area
- lead frame
- frame
- copper foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、樹脂層の両面に銅
箔を接着した厚みが０．５ｍｍ以下の回路板であって、
半導体チップを搭載して半導体装置を形成する回路域と
この回路域を包囲するフレーム域から成るリードフレー
ムに関する。TECHNICAL FIELD The present invention relates to a circuit board having a thickness of 0.5 mm or less in which copper foil is adhered to both surfaces of a resin layer,
The present invention relates to a lead frame including a circuit area on which a semiconductor chip is mounted to form a semiconductor device and a frame area surrounding the circuit area.
【０００２】[0002]
【従来の技術】従来、樹脂層の両面に銅箔を接着した回
路板であって、半導体チップを搭載して半導体装置を形
成する回路域とこの回路域を包囲するフレーム域から成
るリードフレームは、半導体装置の製造に賞用されてい
る。このリードフレームを用いて半導体チップを実装す
る際には、一般に搬送装置で連続的に搬送しながら実装
してなされるが故にリードフレームに反りがあると、搬
送にトラブルが発生したり、或いは半導体チップを定位
置に実装できず、さらには実装の際に加わる外圧に起因
して発生した反りは、後工程の封止工程での封止の信頼
性を低下し、いずれにしても半導体装置の生産性を阻害
する。この反りは、樹脂層の両面に銅箔を接着した回路
板の厚みが０．５ｍｍ以下になると、実装の際に加わる
外圧によって、フレーム域の銅箔の塑性変形が原因で反
りの発生する頻度が顕著である。2. Description of the Related Art Conventionally, a lead frame, which is a circuit board in which copper foil is adhered to both sides of a resin layer, and which comprises a circuit area for mounting a semiconductor chip to form a semiconductor device and a frame area surrounding the circuit area, , Is used for manufacturing semiconductor devices. When a semiconductor chip is mounted using this lead frame, it is generally carried out while being continuously carried by a carrying device, so that if the lead frame has a warp, a trouble occurs in carrying or The chip cannot be mounted at a fixed position, and the warp caused by the external pressure applied during mounting lowers the reliability of the sealing in the subsequent sealing process, and in any case Impede productivity. This warpage occurs when the thickness of the circuit board with the copper foil adhered to both sides of the resin layer becomes 0.5 mm or less and the warpage occurs due to the plastic deformation of the copper foil in the frame area due to the external pressure applied during mounting. Is remarkable.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記の事情に
鑑みてなされたもので、その目的とするところは、樹脂
層の両面に銅箔を接着した厚みが０．５ｍｍ以下の回路
板から成るリードフレームに実装する際に加わる外圧に
よって、フレーム域の銅箔の塑性変形が原因で発生する
反りを回避したリードフレームを提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to obtain a circuit board having a thickness of 0.5 mm or less in which copper foil is adhered to both surfaces of a resin layer. (EN) Provided is a lead frame which avoids warpage caused by plastic deformation of a copper foil in a frame area due to external pressure applied when the lead frame is mounted on the lead frame.
【０００４】[0004]
【課題を解決するための手段】本発明の請求項１に係る
リードフレームは、樹脂層１の両面に銅箔２を接着した
厚みが０．５ｍｍ以下の回路板３であって、半導体チッ
プを搭載して半導体装置を形成する回路域４とこの回路
域４を包囲するフレーム域５から成るリードフレームに
おいて、上記フレーム域５の全面を露出した樹脂層１ａ
で形成し、反りの発生の原因となるフレーム域５の全面
の銅箔を除去した構成により、本発明の請求項２に係る
リードフレームは、上記フレーム域５の全面を銅箔２と
露出した樹脂層１ａから成る縞状のスリット６で形成
し、反りの発生の原因となるフレーム域５の銅箔を部分
的に除去して外圧によって塑性変形する銅箔の面積を減
らした構成により、本発明の請求項３に係るリードフレ
ームは、上記フレーム域５の全面を露出した樹脂層１ａ
で形成し、且つこの樹脂層１ａの層厚を回路域３の樹脂
層１の層厚よりも薄くし、外圧によって塑性変形する銅
箔を全面除去した上にさらに樹脂層の塑性変形による、
回路域４に与える応力をさらに小さくした構成により課
題を解決したものである。A lead frame according to claim 1 of the present invention is a circuit board 3 having a thickness of 0.5 mm or less in which a copper foil 2 is adhered to both surfaces of a resin layer 1, and a semiconductor chip In a lead frame composed of a circuit area 4 mounted to form a semiconductor device and a frame area 5 surrounding the circuit area 4, a resin layer 1a exposing the entire surface of the frame area 5
In the lead frame according to claim 2 of the present invention, the entire surface of the frame area 5 is exposed to the copper foil 2 due to the structure in which the copper foil on the entire surface of the frame area 5 that causes warpage is removed. The striped slit 6 made of the resin layer 1a is formed to partially remove the copper foil in the frame region 5 that causes warpage to reduce the area of the copper foil plastically deformed by external pressure. The lead frame according to claim 3 of the present invention has a resin layer 1a in which the entire surface of the frame region 5 is exposed.
And the thickness of the resin layer 1a is made smaller than that of the resin layer 1 in the circuit area 3, the copper foil plastically deformed by external pressure is completely removed, and further the resin layer is plastically deformed,
The problem is solved by a structure in which the stress applied to the circuit area 4 is further reduced.
【０００５】[0005]
【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。図１（ａ）は本発明の請求項１に係るリー
ドフレームの実施の一形態を示す平面図で、図１（ｂ）
は本発明の請求項２に係るリードフレームの実施の一形
態を示す平面図で、図１（ｃ）は本発明の請求項３に係
るリードフレームの実施の一形態を示す平面図で、図２
（ａ）は図１（ａ）のリードフレームの断面図で、図２
（ｂ）は図１（ｂ）のリードフレームの断面図で、図２
（ｃ）は図１（ｃ）のリードフレームの断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1A is a plan view showing an embodiment of a lead frame according to claim 1 of the present invention, and FIG.
Is a plan view showing an embodiment of a lead frame according to claim 2 of the present invention, and FIG. 1 (c) is a plan view showing an embodiment of a lead frame according to claim 3 of the present invention. Two
2A is a sectional view of the lead frame shown in FIG.
2B is a sectional view of the lead frame shown in FIG.
1C is a cross-sectional view of the lead frame of FIG. 1C.
【０００６】図１（ａ）、図２（ａ）において、リード
フレームは、樹脂層１の両面に銅箔２を接着した厚みが
０．５ｍｍ以下の回路板３から成る。この樹脂層１は、
一例を挙げれば、ガラスクロス又はガラスぺーパーの如
き芯材にエポキシ樹脂、イミド樹脂、ビニルエステル樹
脂、フェノール樹脂の如き硬化性樹脂の硬化物が含浸し
た構成を備えたものである。この回路板３は、上記樹脂
層１の全面に銅箔が接着された銅張り積層板の銅箔にエ
ッチングを施して回路が形成されたものである。この回
路は具体的には、半導体チップを搭載して半導体装置を
形成する回路域４を構成するもので、この回路域４は回
路と断絶したフレーム域５によって包囲されている。こ
のフレーム域５は、図示の如く、上記フレーム域５の全
面を露出した樹脂層１ａで形成されている。1A and 2A, the lead frame is composed of a circuit board 3 having a thickness of 0.5 mm or less in which copper foils 2 are adhered to both surfaces of a resin layer 1. This resin layer 1 is
As an example, a core material such as glass cloth or glass paper is impregnated with a cured product of a curable resin such as an epoxy resin, an imide resin, a vinyl ester resin, or a phenol resin. The circuit board 3 is formed by etching a copper foil of a copper-clad laminate having a copper foil bonded to the entire surface of the resin layer 1 to form a circuit. Specifically, this circuit constitutes a circuit area 4 in which a semiconductor chip is mounted to form a semiconductor device, and the circuit area 4 is surrounded by a frame area 5 which is disconnected from the circuit. The frame region 5 is formed of a resin layer 1a exposing the entire surface of the frame region 5 as shown in the figure.
【０００７】したがって、外圧によって塑性変形する銅
箔が除去されているので、回路域４に与える変形に伴う
応力は減少する。Therefore, since the copper foil which is plastically deformed by the external pressure is removed, the stress caused by the deformation applied to the circuit area 4 is reduced.
【０００８】図１（ｂ）、図２（ｂ）において、このリ
ードフレームのフレーム域５は、上記フレーム域５の全
面を銅箔２と露出した樹脂層１ａから成る縞状のスリッ
ト６で形成されている。In FIGS. 1 (b) and 2 (b), the frame area 5 of the lead frame is formed by striped slits 6 made of the copper foil 2 and the exposed resin layer 1a on the entire surface of the frame area 5. Has been done.
【０００９】したがって、外圧によって塑性変形する銅
箔が部分的に除去されているので、回路域４に与える変
形に伴う応力は減少する。Therefore, since the copper foil which is plastically deformed by the external pressure is partially removed, the stress applied to the circuit area 4 due to the deformation is reduced.
【００１０】図１（ｃ）、図２（ｃ）において、このリ
ードフレームのフレーム域５は、全面を樹脂層１ａで形
成し、さらにこの樹脂層１ａの層厚を回路域４の樹脂層
１の層厚よりも薄くした構成で、この構成により、外圧
によって塑性変形する銅箔を全面除去した上にさらに樹
脂層の変形による応力はさらに小さくなる。In FIG. 1C and FIG. 2C, the frame area 5 of the lead frame is entirely formed of a resin layer 1a, and the thickness of the resin layer 1a is the resin layer 1 of the circuit area 4. The thickness of the resin layer is thinner than the layer thickness of 1., and by this configuration, the copper foil plastically deformed by external pressure is entirely removed, and the stress due to the deformation of the resin layer is further reduced.
【００１１】[0011]
【発明の効果】本発明の請求項１乃至請求項３のリード
フレームによると、いずれの構成によるもリードフレー
ムに実装する際に加わる外圧によって、フレーム域５の
銅箔の塑性変形が原因で発生する反りを回避できる。According to the lead frames of claims 1 to 3 of the present invention, in any structure, it is caused by the plastic deformation of the copper foil in the frame region 5 due to the external pressure applied when the lead frame is mounted on the lead frame. It is possible to avoid the warp.
【図１】（ａ）は本発明の請求項１に係るリードフレー
ムの実施の一形態を示す平面図で、（ｂ）は本発明の請
求項２に係るリードフレームの実施の一形態を示す平面
図で、（ｃ）は本発明の請求項３に係るリードフレーム
の実施の一形態を示す平面図である。FIG. 1 (a) is a plan view showing an embodiment of a lead frame according to claim 1 of the present invention, and FIG. 1 (b) shows an embodiment of a lead frame according to claim 2 of the present invention. In a plan view, (c) is a plan view showing an embodiment of a lead frame according to claim 3 of the present invention.
【図２】（ａ）は図１（ａ）のリードフレームの断面図
で、（ｂ）は図１（ｂ）のリードフレームの断面図で、
（ｃ）は図１（ｃ）のリードフレームの断面図である。2A is a cross-sectional view of the lead frame of FIG. 1A, FIG. 2B is a cross-sectional view of the lead frame of FIG. 1B,
1C is a cross-sectional view of the lead frame of FIG. 1C.
１ 樹脂層 １ａ 露出した樹脂層 ２ 銅箔 ３ 回路板 ４ 回路域 ５ フレーム域 ６ スリット 1 Resin Layer 1a Exposed Resin Layer 2 Copper Foil 3 Circuit Board 4 Circuit Area 5 Frame Area 6 Slit
Claims (3)
した厚みが０．５ｍｍ以下の回路板（３）であって、半
導体チップを搭載して半導体装置を形成する回路域
（４）とこの回路域（４）を包囲するフレーム域（５）
から成るリードフレームにおいて、上記フレーム域
（５）の全面を露出した樹脂層（１ａ）で形成したリー
ドフレーム。1. A circuit board (3) having a thickness of 0.5 mm or less, in which a copper foil (2) is adhered to both surfaces of a resin layer (1), and a circuit area in which a semiconductor chip is mounted to form a semiconductor device. (4) and the frame area (5) surrounding this circuit area (4)
A lead frame made of a resin layer (1a) which is entirely exposed in the frame area (5).
した厚みが０．５ｍｍ以下の回路板（３）であって、半
導体チップを搭載して半導体装置を形成する回路域
（４）とこの回路域（４）を包囲するフレーム域（５）
から成るリードフレームにおいて、上記フレーム域
（５）の全面を銅箔（２）と露出した樹脂層（１ａ）か
ら成る縞状のスリット（６）で形成したリードフレー
ム。2. A circuit board (3) having a thickness of 0.5 mm or less, in which a copper foil (2) is adhered to both surfaces of a resin layer (1), and a circuit area in which a semiconductor chip is mounted to form a semiconductor device. (4) and the frame area (5) surrounding this circuit area (4)
A lead frame made of a striped slit (6) made of a copper foil (2) and an exposed resin layer (1a) on the entire surface of the frame region (5).
した厚みが０．５ｍｍ以下の回路板（３）であって、半
導体チップを搭載して半導体装置を形成する回路域
（４）とこの回路域（４）を包囲するフレーム域（５）
から成るリードフレームにおいて、上記フレーム域
（５）の全面を露出した樹脂層（１ａ）から成り、且つ
この樹脂層（１ａ）の層厚を回路域（４）の樹脂層
（１）の層厚よりも薄くしたリードフレーム。3. A circuit board (3) having a thickness of 0.5 mm or less in which a copper foil (2) is adhered to both surfaces of a resin layer (1), and a circuit area in which a semiconductor chip is mounted to form a semiconductor device. (4) and the frame area (5) surrounding this circuit area (4)
A lead frame made of a resin layer (1a) exposing the entire surface of the frame region (5), and the layer thickness of the resin layer (1a) is the layer thickness of the resin layer (1) in the circuit region (4). A thinner lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7312999A JPH09153582A (en) | 1995-11-30 | 1995-11-30 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7312999A JPH09153582A (en) | 1995-11-30 | 1995-11-30 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09153582A true JPH09153582A (en) | 1997-06-10 |
Family
ID=18036019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7312999A Pending JPH09153582A (en) | 1995-11-30 | 1995-11-30 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09153582A (en) |
-
1995
- 1995-11-30 JP JP7312999A patent/JPH09153582A/en active Pending
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