JPH11102944A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11102944A
JPH11102944A JP28065397A JP28065397A JPH11102944A JP H11102944 A JPH11102944 A JP H11102944A JP 28065397 A JP28065397 A JP 28065397A JP 28065397 A JP28065397 A JP 28065397A JP H11102944 A JPH11102944 A JP H11102944A
Authority
JP
Japan
Prior art keywords
film
wiring
semiconductor device
resin
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28065397A
Other languages
Japanese (ja)
Inventor
Kenji Miyajima
賢治 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP28065397A priority Critical patent/JPH11102944A/en
Publication of JPH11102944A publication Critical patent/JPH11102944A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a small semiconductor device having high reliability at low cost wherein such wiring film as insulating resin film, etc., is used instead of a wiring board made of a copper clad laminated board. SOLUTION: On one surface of an insulating resin film 12 where a transportation hole, etc., is provided, such wirings as inner lead 17, etc., are formed, and after that, boring of a via hole is executed. Further, a cut line 15 for separation is formed along a profile line of a resin sealing layer. Then, a wiring film wherein wirings are formed and a hole is opened in this manner is temporarily fixed to an auxiliary board 21 where a punching return part 22 is formed, then a semiconductor element 24 is mounted and the mounted part is coated and sealed up with an insulating resin. Then, the punching return part 22 of the auxiliary board 21 is removed, a solder ball is array in lattice on a rear surface of an exposed wiring film, and a reflow generates a bump 24. Then, utilizing the cut line 15, a resin-sealed semiconductor device is cut out.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に係り、特に絶縁性樹脂フィルムまたはガラスクロ
ス−樹脂含浸フィルムの配線フィルムを使用し、ビデオ
カメラのような携帯用機器に好適する半導体装置を製造
する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device using a wiring film of an insulating resin film or a glass cloth-resin impregnated film and suitable for portable equipment such as a video camera. The present invention relates to a method for manufacturing a device.

【0002】[0002]

【従来の技術】一般に、半導体装置における半導体素子
の封止形態は、セラミックや金属などを使用した気密封
止と、樹脂封止(樹脂モールド封止)とに分類される。
後者の樹脂封止は、前者のセラミック等による気密封止
に比べて、信頼性が若干劣るものの量産性や経済性に優
れ、半導体素子の占拠率が極めて高いなど、生産性とコ
ストの面でメリットを有している。
2. Description of the Related Art In general, a semiconductor device in a semiconductor device is classified into a hermetic seal using ceramics or metal, and a resin seal (resin mold seal).
Compared with the former hermetic sealing with ceramics, the latter resin sealing is slightly less reliable, but is superior in mass productivity and economic efficiency, and has a very high occupancy rate of semiconductor elements. Has merits.

【0003】樹脂封止型の半導体装置の一つとして、従
来から、金属製のリードフレーム上に半導体素子を搭載
し、ワイヤボンディングなどにより電気的に接続すると
ともに、半導体素子とワイヤとの接合部を、エポキシ樹
脂などの樹脂材料のモールド成形により被覆・封止した
構造のものが知られている。
Conventionally, as one of the resin-sealed semiconductor devices, a semiconductor element is mounted on a lead frame made of metal and electrically connected by wire bonding or the like, and a bonding portion between the semiconductor element and a wire is conventionally formed. Is coated and sealed by molding a resin material such as an epoxy resin.

【0004】しかしこのような半導体装置では、複数の
素子を搭載することが難しいばかりでなく、外部取出し
電極となるアウターリードが変形しやすいという問題が
あった。そのため近年、ガラス−エポキシ銅張積層板の
ような銅張積層板を用いて、インナーリード等の配線群
とこれらの配線群を他面側に導出するスルーホール接続
部をそれぞれ形成し、得られた配線板の上に半導体素子
を搭載して、ワイヤボンディング等を行なうとともに、
モールド成形により樹脂封止層を形成した半導体装置が
開発されている。
However, in such a semiconductor device, not only is it difficult to mount a plurality of elements, but also there is a problem that an outer lead serving as an external extraction electrode is easily deformed. Therefore, in recent years, using a copper-clad laminate such as a glass-epoxy copper-clad laminate, a wiring group such as an inner lead and a through-hole connection portion for leading these wiring groups to the other side are formed, respectively. The semiconductor element is mounted on the wiring board, and wire bonding is performed.
Semiconductor devices having a resin sealing layer formed by molding have been developed.

【0005】そしてこのような半導体装置では、I/O
端子数の増加、外形の小型化、実装の容易性等の観点か
ら、配線板の裏面に外部接続端子として、はんだ等のボ
ールを格子(アレイ)状に配列してバンプを形成した、
ボールグリッドアレイ(以下、BGAと示す。)と呼ば
れる構造が多用されている。また、このようなBGAの
中でも、特に端子間のピッチの狭いものは、FBGA
(ファインピッチボールグリッドアレイ)と呼ばれ使用
が拡大しつつある。
In such a semiconductor device, I / O
From the viewpoints of increasing the number of terminals, downsizing of the outer shape, ease of mounting, etc., bumps are formed by arranging balls of solder or the like in a grid (array) as external connection terminals on the rear surface of the wiring board.
A structure called a ball grid array (hereinafter, referred to as BGA) is frequently used. Among such BGAs, particularly, those having a narrow pitch between terminals are FBGAs.
(Fine pitch ball grid array) and its use is expanding.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、このよ
うな配線板を用いた半導体装置においては、以下に示す
ような問題があった。
However, the semiconductor device using such a wiring board has the following problems.

【0007】すなわち、このような配線板において、両
面の配線群を電気的に接続するスルーホール接続部を形
成するには、細径のドリルを用いて所定の位置に一個一
個孔開けした後、孔の内壁面をめっき(スルーホールめ
っき)する方法が採られており、孔開け加工に非常に手
間がかかるため、半導体装置全体の価格を低減すること
が難しかった。
That is, in such a wiring board, in order to form a through-hole connecting portion for electrically connecting the wiring groups on both surfaces, holes are drilled one by one at predetermined positions using a small diameter drill. A method of plating the inner wall surface of the hole (through-hole plating) is used, and it takes a lot of time and labor to form the hole, so that it has been difficult to reduce the price of the entire semiconductor device.

【0008】特に、BGA型の半導体装置では、格子状
に配列されたはんだ等のバンプに導出するために、この
バンプの数以上のスルーホールを形成する必要がある。
そのため、孔開けに要する手間が配線板の原価構成に大
きな位置を占め、半導体装置のコスト低減に大きな障害
となっていた。
In particular, in the case of a BGA type semiconductor device, it is necessary to form through holes equal to or larger than the number of bumps in order to lead to bumps made of solder or the like arranged in a grid.
Therefore, the labor required for drilling holes occupies a large part in the cost structure of the wiring board, which has been a major obstacle to reducing the cost of the semiconductor device.

【0009】さらに近年、薄型化および小型化が図られ
た半導体装置として、外形を半導体素子(チップ)の大
きさに合わせて形成したチップサイズパッケージ(CS
P)があり、これらの中でも絶縁性樹脂フィルムを用い
たファインピッチのエリアパッケージが有望視されてい
る。
In recent years, as a semiconductor device which has been made thinner and smaller, a chip size package (CS) having an outer shape formed according to the size of a semiconductor element (chip) has been developed.
P), and among these, a fine pitch area package using an insulating resin film is considered promising.

【0010】そしてこのようなCSPの製造は、従来か
ら、絶縁性樹脂フィルムの片面または両面に銅箔を張り
付け、写真蝕刻法により配線パターンや導通用の孔を形
成し、得られた配線フィルムに、半導体チップのダイボ
ンディング、ワイヤーボンディング、トランスファモー
ルド等による樹脂封止、およびはんだバンプの取付け形
成を順に行なった後、樹脂封止層の外形線に合わせてフ
ィルムを切断し切り離す手順で行なわれている。
[0010] Conventionally, such a CSP is manufactured by pasting a copper foil on one or both surfaces of an insulating resin film, forming a wiring pattern or a hole for conduction by a photolithography method, and forming the wiring film on the obtained wiring film. After performing resin sealing by die bonding, wire bonding, transfer molding, etc. of the semiconductor chip, and attaching and forming the solder bumps in order, the film is cut and separated according to the outline of the resin sealing layer. I have.

【0011】ここで、切り離し用の切断線(カットライ
ン)を入れる位置を、図6に示す。図において、符号1
は配線フィルム、2は半導体チップの外形線、3は樹脂
封止層の外形線(トランスファモールドライン)、4は
カットライン、5はモールド時にゲートおよびエアーベ
ントの位置に形成された余剰樹脂フロー部をそれぞれ示
している。カットライン4は、トランスファモールドラ
イン3からLだけ離れた位置に形成される。切り出し代
に相当するこの長さLは、配線フィルム1の厚さとトラ
ンスファモールドライン3の位置精度および工具による
切断精度により決定され、 0.3〜 0.5mm程度の大きさが
必要とされている。また、余剰樹脂フロー部5の切断を
避けるために、さらに 0.2mm程度外側にカットライン4
が設定される。
FIG. 6 shows a position where a cutting line (cut line) for cutting is inserted. In FIG.
Is a wiring film, 2 is an outline of a semiconductor chip, 3 is an outline of a resin sealing layer (transfer mold line), 4 is a cut line, and 5 is a surplus resin flow portion formed at a position of a gate and an air vent during molding. Are respectively shown. The cut line 4 is formed at a position separated from the transfer mold line 3 by L. The length L corresponding to the cutting allowance is determined by the thickness of the wiring film 1, the positional accuracy of the transfer mold line 3 and the cutting accuracy by a tool, and is required to be about 0.3 to 0.5 mm. Further, in order to avoid cutting the excess resin flow portion 5, a cut line 4
Is set.

【0012】このように従来の半導体装置の製造方法で
は、より小型化を要するCSPにおいて、カットライン
4がトランスファモールドライン3から 0.5〜 0.7mm外
側に離れた位置に設けられるため、パッケージの外形が
樹脂封止層のそれより 1.0〜1.4mmも大きくなるという
問題があった。
As described above, in the conventional method of manufacturing a semiconductor device, the cut line 4 is provided at a position 0.5 to 0.7 mm outside the transfer mold line 3 in the CSP that requires further miniaturization. There is a problem that the thickness is 1.0 to 1.4 mm larger than that of the resin sealing layer.

【0013】また、最終工程で、樹脂封止層の全周に亘
ってフィルムの切断を行なっており、超硬工具のような
特殊な工具を使用することが難しいため、切断工具の摩
耗が早く、工具の管理が繁雑となっていた。さらに、切
断不良が生じやすく、それが原価低減が難しい原因の一
つとなっていた。
In the final step, the film is cut over the entire circumference of the resin sealing layer, and it is difficult to use a special tool such as a carbide tool. , The management of tools became complicated. Furthermore, cutting defects are likely to occur, which has been one of the causes of difficulty in reducing costs.

【0014】本発明は、このような問題を解消するため
になされたもので、銅張積層板から作製される配線板に
代わって、絶縁性樹脂フィルムまたはガラスクロス−樹
脂含浸フィルムの配線フィルムを使用し、小型で信頼性
の高い半導体装置を安価に製造する方法を提供すること
を目的とする。
The present invention has been made to solve such a problem. Instead of using a wiring board made of a copper-clad laminate, an insulating resin film or a glass cloth-resin impregnated wiring film is used. It is an object of the present invention to provide a method for manufacturing a small and highly reliable semiconductor device at a low cost.

【0015】[0015]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、絶縁性樹脂フィルムの少なくとも一主面に所
要の配線群を形成するとともに、導通用の孔開けを行な
う工程と、前記配線群が形成され孔開けがなされた配線
フィルムの前記一主面上の所定の位置に、半導体素子を
実装する工程と、前記配線群が形成され孔開けがなされ
た配線フィルムを、剛性を有する補助板上に配置し仮止
めする工程と、前記半導体素子の実装部を絶縁性樹脂に
より被覆し封止する工程と、前記絶縁性樹脂の封止層が
形成された樹脂封止体から、前記補助板の一部を取り外
す工程と、前記補助板が取り外されて露出した前記配線
フィルムの他主面に、外部接続端子を形成し、該外部接
続端子をヴィアホールを介して反対主面側の配線群と接
続する工程と、前記外部接続端子が形成された樹脂封止
体を、前記樹脂封止層の外形線に沿って切り出す工程と
を備えたことを特徴とする。
According to a method of manufacturing a semiconductor device of the present invention, a required wiring group is formed on at least one principal surface of an insulating resin film, and a hole for conducting is formed. A step of mounting a semiconductor element at a predetermined position on the one main surface of the wiring film on which the group is formed and perforated; A step of arranging and temporarily fixing the semiconductor element on a board, a step of covering and mounting the mounting portion of the semiconductor element with an insulating resin, and a step of forming the auxiliary from the resin sealing body on which the sealing layer of the insulating resin is formed. Removing a part of the board, forming an external connection terminal on the other main surface of the wiring film exposed by removing the auxiliary plate, and connecting the external connection terminal to a wiring on the opposite main surface side via a via hole. Before connecting to the group The resin sealing body on which the external connection terminals are formed, characterized in that a step of cutting along the outline of the resin sealing layer.

【0016】本発明の第2の発明の半導体装置の製造方
法は、ガラスクロス−樹脂含浸フィルムの少なくとも一
主面に所要の配線群を形成し、導通用の孔開けを行なう
とともに、所定の位置に切り離し用の切り線またはスリ
ットを形成する工程と、前記配線群が形成され孔開けが
なされた配線フィルムの前記一主面上の所定の位置に、
半導体素子を実装する工程と、前記半導体素子の実装部
を絶縁性樹脂により被覆し封止する工程と、前記絶縁性
樹脂の封止層が形成された樹脂封止体において、前記配
線フィルムの他主面に外部接続端子を形成し、該外部接
続端子をヴィアホールを介して反対主面側の配線群と接
続する工程と、前記外部接続端子が形成された樹脂封止
体を、前記樹脂封止層の外形線に沿って形成された前記
切り線またはスリットを用いて切り離す工程とを備えた
ことを特徴とする。
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a required wiring group is formed on at least one principal surface of a glass cloth-resin impregnated film, holes for conduction are formed, and a predetermined position is formed. Forming a cutting line or slit for separation into, at a predetermined position on the one main surface of the wiring film in which the wiring group is formed and perforated,
A step of mounting the semiconductor element; a step of covering and sealing the mounting portion of the semiconductor element with an insulating resin; and a step of mounting the semiconductor element with a sealing layer formed of the insulating resin. Forming an external connection terminal on the main surface, connecting the external connection terminal to a wiring group on the opposite main surface side via a via hole, and sealing the resin sealing body on which the external connection terminal is formed, And cutting using the cut lines or slits formed along the outline of the stop layer.

【0017】本発明の第1の発明において、絶縁性樹脂
フィルムとしては、例えばポリパラフェニレンテレフタ
ルアミドのような液晶ポリマーのフィルム、ポリエチレ
ンフィルム、ポリイミド系樹脂フィルム、あるいはエポ
キシ系樹脂フィルム等が挙げられ、その厚さは、製造す
る半導体装置の品種、形状、大きさ等にもよるが、75〜
100μm 程度とすることが好ましい。
In the first invention of the present invention, examples of the insulating resin film include a liquid crystal polymer film such as polyparaphenylene terephthalamide, a polyethylene film, a polyimide resin film, and an epoxy resin film. The thickness depends on the type, shape, size, etc. of the semiconductor device to be manufactured.
It is preferably about 100 μm.

【0018】また、第2の発明において、ガラスクロス
−樹脂含浸フィルムとしては、ガラス繊維を織成したガ
ラスクロスにエポキシ樹脂等の絶縁性樹脂を含浸させた
プリプレグを1枚または複数枚を、所望に応じて積層し
成形した薄型フィルムが挙げられ、0.05〜0.15mm(50〜
150μm )の厚さのものが使用される。
Further, in the second invention, as the glass cloth-resin impregnated film, one or more prepregs obtained by impregnating an insulating resin such as an epoxy resin into a glass cloth woven from glass fibers are preferably used. A thin film formed by laminating and molding according to the requirements is 0.05 to 0.15 mm (50 to
A thickness of 150 μm) is used.

【0019】本発明の第1および第2の発明において
は、これらの絶縁性樹脂フィルムまたはガラスクロス−
樹脂含浸フィルムの少なくとも一主面に、信号線やイン
ナーリード群などの配線群が形成され、これらの配線群
を他主面に導出するための導通孔(ヴィアホール)が開
けられる。ここで、インナーリード群のピッチおよび配
列は、実装される半導体素子の電極端子のピッチや配置
に対応して設定される。そして、このようなインナーリ
ード群を含めた配線群は、絶縁性樹脂フィルムまたはガ
ラスクロス−樹脂含浸フィルム面への蒸着パターニン
グ、あるいはこれらのフィルムの片面または両面に設け
られた銅箔等の導体金属層をフォトパターニングするこ
とにより形成される。
In the first and second aspects of the present invention, these insulating resin films or glass cloths are used.
A wiring group such as a signal line and an inner lead group is formed on at least one main surface of the resin-impregnated film, and a conduction hole (via hole) for leading these wiring groups to another main surface is formed. Here, the pitch and arrangement of the inner lead group are set in accordance with the pitch and arrangement of the electrode terminals of the semiconductor element to be mounted. A wiring group including such an inner lead group is formed by vapor deposition patterning on an insulating resin film or a glass cloth-resin impregnated film surface, or a conductive metal such as a copper foil provided on one or both surfaces of these films. It is formed by photo-patterning a layer.

【0020】本発明において、導通孔の孔開けは、液晶
ポリマーフィルムのような絶縁性樹脂フィルムでは、写
真蝕刻法などにより多数個同時にかつ短時間で行なうこ
とができ、非常に安価に加工を行なうことができる。ま
た、ガラスクロス−樹脂含浸フィルムの場合は、ドリル
等を用いて導通孔の孔開けを行なうが、複数枚を重ねて
孔開けすることができるので、従来から使用されている
配線板と比べて、孔開け作業の効率が高い。
In the present invention, a plurality of conductive holes can be formed simultaneously and in a short time by an etching method or the like in an insulating resin film such as a liquid crystal polymer film, and the processing is performed at very low cost. be able to. Further, in the case of a glass cloth-resin impregnated film, a hole is formed in a conduction hole using a drill or the like, but since a plurality of sheets can be formed and drilled, compared with a conventionally used wiring board, The efficiency of drilling work is high.

【0021】また、このような絶縁性樹脂フィルムまた
はガラスクロス−樹脂含浸フィルムには、製造すべき半
導体装置の外形寸法に合わせて、すなわち後工程でモー
ルド成形される樹脂封止層の外形線に合わせて、予め切
り離し用の切り線またはスリットを形成しておくことが
できる。なお、特にガラスクロス−樹脂含浸フィルムで
は、モールド成形後のフィルムの波打ちがないという点
から、切り線よりも0.5mm程度の幅を持つスリットを形
成する方が好ましい。また切り線の形成は、例えばナイ
フ刃による突き切りの方法により、寸法精度良く行なう
ことができ、溝付きの下敷きを用いることで、より良好
な切り口面が得られる。
Further, such an insulating resin film or a glass cloth-resin impregnated film is formed in accordance with the outer dimensions of a semiconductor device to be manufactured, that is, the outer shape of a resin sealing layer molded in a later step. In addition, a cutting line or slit for separation can be formed in advance. In particular, in the case of a glass cloth-resin impregnated film, it is preferable to form a slit having a width of about 0.5 mm from the cut line, since there is no waving of the film after molding. The cutting line can be formed with high dimensional accuracy by, for example, a parting-off method using a knife blade, and a better cut surface can be obtained by using a grooved underlay.

【0022】さらに、切り線またはスリット6の形状
は、図1(a)〜(c)に示すように、樹脂封止層の外
形線に合わせた矩形で、複数の短い連結部7が残存する
ような形状とすることが望ましい。特に、後の切り離し
工程での作業の容易性と切断端面の平滑性を考慮して、
図1(a)に示すように、四隅の矩形頂点部を連結部7
として残した形状とすることが最も望ましい。なお、図
中符号8は、絶縁性樹脂フィルムまたはガラス−樹脂積
層フィルム、9は搬送孔、10は位置決め孔、11は半
導体素子をマウントするためのアイランド(ベッド)部
をそれぞれ示している。
Further, as shown in FIGS. 1 (a) to 1 (c), the shape of the cut line or slit 6 is rectangular according to the outline of the resin sealing layer, and a plurality of short connecting portions 7 remain. It is desirable to have such a shape. In particular, considering the ease of work in the subsequent separation process and the smoothness of the cut end face,
As shown in FIG. 1A, the rectangular vertices at the four corners are
It is most desirable that the shape be left as is. In the drawing, reference numeral 8 denotes an insulating resin film or a glass-resin laminated film, 9 denotes a transport hole, 10 denotes a positioning hole, and 11 denotes an island (bed) portion for mounting a semiconductor element.

【0023】配線群の形成および孔開け工程で、絶縁性
樹脂フィルムまたはガラスクロス−樹脂含浸フィルム8
に、このような切り線またはスリット6を形成しておい
た場合には、四隅等の連結部7を切断するだけで、フィ
ルム周囲の枠部から内側の樹脂封止体を容易に切り離す
ことができる。また、このような切り線またはスリット
6の形成では、余白(切り出し代)をほとんど採る必要
がないので、CSP等の半導体装置の小型化をより一層
達成することができる。
In the step of forming wiring groups and forming holes, an insulating resin film or a glass cloth-resin impregnated film 8 is used.
In the case where such cut lines or slits 6 are formed, it is possible to easily separate the inner resin sealing body from the frame around the film only by cutting the connecting portions 7 such as the four corners. it can. Further, in the formation of such cut lines or slits 6, there is almost no need to take a margin (cut-out allowance), so that it is possible to further reduce the size of a semiconductor device such as a CSP.

【0024】さらに、最終工程でのフィルム切断作業が
連結部のみの切断で良いので、工程管理や作業法が著し
く容易になるうえに、切断に超硬工具のような精密工具
を用いることができるので、高い歩留まりを達成するこ
とができ、低価格化を図ることができる。
Further, since the film cutting work in the final step can be performed by cutting only the connecting portion, the process management and the working method are remarkably facilitated, and a precision tool such as a carbide tool can be used for cutting. Therefore, a high yield can be achieved, and a reduction in price can be achieved.

【0025】本発明の第1の発明において、補助板とし
ては、ステンレスやチタン等の金属の薄板が挙げられ
る。その厚さは、できるだけ薄くかつ十分な剛性および
靭性を有するような厚さとし、例えばステンレス板で
は、約 0.5mmの厚さとすることが望ましい。なお、この
ような補助板は、樹脂モールドによる被覆・封止工程の
終了後、少なくとも一部が配線フィルムから取り外し除
去されるので、取り外しを容易にするため、その部分を
打抜き戻し部としておくことが望ましい。すなわち、取
り外される部分と取り外されない枠部分との境界線に沿
って、切断線を入れ、内側部分を打ち抜いた後再び嵌め
戻することにより、打抜き戻し部いわゆるプシュバック
部としておくことが望ましい。
In the first aspect of the present invention, the auxiliary plate may be a thin plate of a metal such as stainless steel or titanium. It is desirable that the thickness be as thin as possible and have sufficient rigidity and toughness, for example, about 0.5 mm for a stainless steel plate. In addition, since such an auxiliary plate is at least partially removed from the wiring film after the completion of the covering / sealing step by the resin mold, the portion should be punched back to facilitate removal. Is desirable. That is, it is desirable that a cutting line is made along the boundary between the part to be removed and the frame part not to be removed, and the inside part is punched out and then fitted again to form a punch-back part, a so-called pushback part.

【0026】本第1の発明においては、前記した絶縁性
樹脂フィルムを用いた配線フィルムを、このような剛性
を有する薄い補助板に仮止めした後、半導体素子の搭載
・実装および樹脂モールドによる被覆・封止を順に行な
うようにすることが望ましい。このように構成すること
により、従来のリードフレームを用いた半導体装置と同
一の工程で、組み立て製造を行なうことができ、絶縁性
樹脂フィルムの使用により特別な工程を構築する必要が
ない。また補助板は、取り外された部分を嵌め込み元の
状態に戻してから、何度でも使用することができるの
で、補助板を用いることで余分なコストがかかることが
ない。
In the first aspect of the present invention, the wiring film using the insulating resin film is temporarily fixed to a thin auxiliary plate having such rigidity, and then the mounting and mounting of the semiconductor element and the covering with the resin mold are performed. -It is desirable to perform sealing in order. With this configuration, assembly and manufacturing can be performed in the same process as that of a conventional semiconductor device using a lead frame, and there is no need to construct a special process by using an insulating resin film. Further, since the auxiliary plate can be used any number of times after the removed portion is fitted back to the original state, no extra cost is required by using the auxiliary plate.

【0027】さらに本第1の発明では、配線フィルム上
に半導体素子を搭載・実装した後、この半導体素子が実
装された配線フィルムを補助板に仮止めするように構成
するもできる。このように、樹脂封止層のモールド工程
のみを補助板で裏打ちされた状態で行なっても、前記し
た効果を上げることができる。
Further, in the first invention, after the semiconductor element is mounted and mounted on the wiring film, the wiring film on which the semiconductor element is mounted may be temporarily fixed to the auxiliary plate. As described above, even if only the molding step of the resin sealing layer is performed in a state of being backed by the auxiliary plate, the above-described effect can be improved.

【0028】本第1の発明および第2の発明において、
絶縁性樹脂フィルムまたはガラス−樹脂積層フィルムを
用いた配線フィルムの他主面に形成される外部接続端子
としては、例えばPb/Sn系のはんだを主成分とする
ボール状のバンプがあり、これらは格子状に配列して形
成される。そして、このようなはんだバンプの形成は、
例えば、バンプ整列板上に形成されたバンプを、配線フ
ィルムの他主面に位置合わせし加熱・加圧して転写接合
する方法(転写バンプ方式)により行なうことができ
る。
In the first invention and the second invention,
As an external connection terminal formed on the other main surface of the wiring film using the insulating resin film or the glass-resin laminated film, for example, there is a ball-shaped bump mainly composed of a Pb / Sn-based solder. They are arranged in a lattice. And the formation of such solder bumps
For example, the bumps formed on the bump alignment plate can be aligned with the other main surface of the wiring film, and heated and pressed to transfer and bond them (transfer bump method).

【0029】[0029]

【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0030】第1の実施例においては、絶縁性樹脂フィ
ルムとして、液晶ポリマーフィルムであるベクトラン
(クラレ社の商品名、厚さ70〜 100μm )を使用し、こ
のフィルムの片面に銅箔を熱圧着により張り付けたもの
に、長さ方向に沿って所定の間隔で搬送用の孔と位置決
め用の孔とをそれぞれ開けた後、各半導体装置形成部に
おいて、銅箔をフォトパターニングするなどの方法で、
片面にインナーリード群とそれらに接続された信号線群
などの配線群をそれぞれ形成する。また、このフィルム
の所定の位置に、前記配線群をそれぞれ他主面に導出す
るための複数の孔を、写真蝕刻法により同時に形成す
る。さらに、樹脂封止層の外形線に合わせて、例えばナ
イフ刃による突き切りの方法により、四隅をそれぞれ切
り残して切り離し用の切り線を形成する。
In the first embodiment, a liquid crystal polymer film Vectran (trade name of Kuraray Co., thickness: 70 to 100 μm) is used as an insulating resin film, and copper foil is thermocompression-bonded to one side of the film. After opening a hole for transport and a hole for positioning at predetermined intervals along the length direction, in each semiconductor device forming portion, by a method such as photo-patterning a copper foil,
On one surface, an inner lead group and a wiring group such as a signal line group connected to the inner lead group are formed. In addition, a plurality of holes for leading the wiring groups to the other main surface are simultaneously formed at predetermined positions of the film by photolithography. Further, cut-off lines are formed in accordance with the outline of the resin sealing layer, for example, by cutting off with a knife blade, leaving four corners uncut.

【0031】こうして得られた配線フィルムの概略形状
を、図2に示す。また、図2における一部(A部)を拡
大したもの(配線パターンを含める)を図3に示す。こ
れらの図において、符号12は絶縁性樹脂フィルム(ベ
クトラン)、13は搬送孔、14は位置決め孔、15は
切り離し用切り線、16は半導体素子をマウントするた
めのアイランド部、17はインナーリード、18は後述
する補助板へ仮固定するための仮止め部をそれぞれ示し
ている。また、符号19はヴィアホール形成用の孔、2
0は信号線などの配線をそれぞれ示している。
FIG. 2 shows a schematic shape of the wiring film thus obtained. FIG. 3 is an enlarged view (including the wiring pattern) of a part (A part) in FIG. In these figures, reference numeral 12 denotes an insulating resin film (Vectran), 13 denotes a transport hole, 14 denotes a positioning hole, 15 denotes a cutting cut line, 16 denotes an island portion for mounting a semiconductor element, 17 denotes an inner lead, Numeral 18 denotes a temporary fixing portion for temporarily fixing to an auxiliary plate described later. Reference numeral 19 denotes a hole for forming a via hole;
0 indicates a wiring such as a signal line.

【0032】次いで、この配線フィルムを使用し、以下
に示すようにして半導体装置を製造する。すなわち、配
線フィルムの1区画を断面的に示した図4に示すよう
に、この配線フィルムを、インナーリード17および信
号線等の配線20の形成面を上にして、厚さ約 0.5mmの
ステンレス製の補助板21の上に載せ、仮止め部におい
て、はんだや樹脂系の接着剤を介して、あるいは接着剤
テープを用いて仮固定する(図4(a))。なお、補助
板21には、予め配線フィルムと同じ位置に搬送孔と位
置決め孔がそれぞれ設けられており、かつプシュバック
工法により、所定の位置に打抜き戻し部22が形成され
ている。すなわち、補助板21において、配線フィルム
の切り離し用切り線15より外側の位置に、プシュバッ
ク用の切断線23が入れられ、内側の打抜き部が嵌め戻
し(プシュバック)されている。
Next, a semiconductor device is manufactured using the wiring film as described below. That is, as shown in FIG. 4 showing one section of the wiring film in cross section, this wiring film is placed on a stainless steel sheet having a thickness of about 0.5 mm with the surface on which the wiring 20 such as the inner lead 17 and the signal line is formed upward. And is temporarily fixed at the temporary fixing portion via a solder or a resin-based adhesive or using an adhesive tape (FIG. 4A). The auxiliary plate 21 is provided with a transport hole and a positioning hole at the same position as the wiring film in advance, and a punch-back portion 22 is formed at a predetermined position by a pushback method. That is, in the auxiliary plate 21, a cutting line 23 for pushback is inserted at a position outside the cutting line 15 for separating the wiring film, and the inner punched portion is fitted back (pushback).

【0033】次に、図4(b)に示すように、補助板2
1に仮止めされた配線フィルムのアイランド部16に、
半導体素子24を配置し、エポキシ樹脂系等の絶縁性接
着剤(図示を省略。)により接着固定(ダイボンド)し
た後、この半導体素子24の電極端子24aと配線フィ
ルムのインナーリード17とを、それぞれ金線等のボン
ディングワイヤ25を用いて接続する。その後、図4
(c)に示すように、半導体素子24とボンディングワ
イヤ25およびそれらの接合部を被覆し封止する樹脂封
止層26を、エポキシ樹脂等のトランスファモールドに
より成形する。次いで、図4(d)に示すように、補助
板21の打抜き戻し部22を取り除いた後、図4(e)
に示すように、露出した配線フィルムの裏面に、格子状
に配列されたはんだバンプ27を形成する。すなわち、
Pb/Sn系のはんだボールを、配線フィルムに設けら
れた孔19に埋め込むように取付けた後、リフローする
ことにより、ヴィアホールを介して他面の配線20に接
続されたはんだバンプ27を形成する。しかる後、予め
配線フィルムに形成された切り離し用切り線15の四隅
の連結部をそれぞれ切断して、内側部分を外側の枠部か
ら切り離し、図4(f)に示す半導体装置を得る。
Next, as shown in FIG.
In the island portion 16 of the wiring film temporarily fixed to 1,
After the semiconductor element 24 is arranged and fixed (die-bonded) with an insulating adhesive (not shown) such as an epoxy resin, the electrode terminals 24a of the semiconductor element 24 and the inner leads 17 of the wiring film are respectively connected to each other. The connection is made using a bonding wire 25 such as a gold wire. Then, FIG.
As shown in (c), a resin sealing layer 26 that covers and seals the semiconductor element 24, the bonding wires 25, and their joints is formed by transfer molding of epoxy resin or the like. Next, as shown in FIG. 4D, after the punch-back portion 22 of the auxiliary plate 21 is removed, FIG.
As shown in (2), solder bumps 27 arranged in a grid are formed on the exposed back surface of the wiring film. That is,
After mounting the Pb / Sn-based solder ball so as to be embedded in the hole 19 provided in the wiring film, reflow is performed to form the solder bump 27 connected to the wiring 20 on the other surface via the via hole. . Thereafter, the connecting portions at the four corners of the separating cut line 15 formed in advance on the wiring film are cut off, and the inner portion is cut off from the outer frame portion to obtain the semiconductor device shown in FIG.

【0034】このように構成される実施例においては、
従来から使用されているプリント配線板に代わって、薄
い絶縁性樹脂フィルムからなる配線フィルムが使用され
ているので、ヴィアホール形成のための孔開けを、写真
蝕刻法等により多数個同時にかつ短時間で行なうことが
でき、安価な加工が可能である。具体的には、28mm×14
3mm(8p)程度のBGA基板で概算すると、工法や配線
規則によって幅があるが、従来の 5〜50%の価格で極め
て安価に半導体装置が提供される。
In the embodiment configured as described above,
Since a wiring film made of a thin insulating resin film is used in place of the conventionally used printed wiring board, a large number of holes for forming via holes can be formed simultaneously and in a short time by photo etching. And inexpensive processing is possible. Specifically, 28mm x 14
When roughly estimated for a BGA substrate of about 3 mm (8p), although there are widths depending on the construction method and wiring rules, a semiconductor device can be provided at a very low price at 5 to 50% of the conventional price.

【0035】なお、以上の実施例では、液晶ポリマーで
あるポリパラフェニレンテレフタルアミドのフィルムを
使用した例について説明したが、本発明に使用する絶縁
性樹脂フィルムはこれに限定されず、例えばポリイミド
系樹脂やエポキシ系樹脂からなるフィルムを使用して
も、同様な効果を得ることができる。
In the above embodiments, an example using a polyparaphenylene terephthalamide film as a liquid crystal polymer was described. However, the insulating resin film used in the present invention is not limited to this. The same effect can be obtained by using a film made of a resin or an epoxy resin.

【0036】また、補助板21上に仮固定された状態
で、樹脂封止層26のモールド工程のみを行なうように
しても良い。すなわち、配線フィルムのままで半導体素
子24のダイボンドおよびワイヤボンディングを行なっ
た後、補助板21に仮止めし、補助板21上に仮固定さ
れた状態で樹脂封止層26のモールドを行なうように構
成しても、作業性向上およびコスト低減の点で、十分な
改善効果を上げることができる。
Further, only the molding step of the resin sealing layer 26 may be performed in a state where the resin sealing layer 26 is temporarily fixed on the auxiliary plate 21. That is, after performing die bonding and wire bonding of the semiconductor element 24 with the wiring film as it is, the semiconductor element 24 is temporarily fixed to the auxiliary plate 21 and the resin sealing layer 26 is molded while being temporarily fixed on the auxiliary plate 21. Even with this configuration, a sufficient improvement effect can be achieved in terms of improving workability and reducing costs.

【0037】さらに実施例では、絶縁性樹脂フィルム1
2の片面にのみ、インナーリード17および信号線など
の配線20パターンを形成した片面配線フイルムを使用
した例について説明したが、両面にそれぞれ配線パター
ンを形成した両面配線フイルムの使用も可能である。す
なわち、絶縁性樹脂フィルムの片面にインナーリード群
と信号線などの配線群を形成するとともに、他面にも所
定の配線群と外部接続端子を接続するためのパッド群を
形成し、かつ両面の配線群を導通させるヴィアホールを
形成した両面配線フイルムを使用した場合でも、本発明
の方法を採ることで、信頼性の高い半導体装置を安価に
得ることができる。
Further, in the embodiment, the insulating resin film 1
Although an example in which the single-sided wiring film having the inner leads 17 and the wiring 20 patterns such as signal lines formed on only one side is described above, a double-sided wiring film having a wiring pattern formed on both sides can also be used. That is, a wiring group such as an inner lead group and a signal line is formed on one surface of the insulating resin film, and a pad group for connecting a predetermined wiring group and an external connection terminal is formed on the other surface. Even when a double-sided wiring film having via holes for conducting wiring groups is used, a highly reliable semiconductor device can be obtained at low cost by employing the method of the present invention.

【0038】次に、本発明の別の実施例について説明す
る。
Next, another embodiment of the present invention will be described.

【0039】第2の実施例においては、厚さ0.05〜0.15
mmのガラスクロス−エポキシ樹脂含浸フィルムの片面に
銅箔が張り付けられた銅張フィルムに、第1の実施例と
同様に搬送用の孔と位置決め用の孔とをそれぞれ開けた
後、フォトパターニング等の方法で、インナーリードお
よび信号線等の配線群を形成する。また、ドリル等を用
いて、配線群を他面に導出するための孔開けを行なう。
また、後工程でモールド成形される樹脂封止層の外形線
に合わせて、四隅をそれぞれ切り残した切り離し用スリ
ット(幅約 0.5mm)を形成する。
In the second embodiment, the thickness is 0.05 to 0.15
In the same manner as in the first embodiment, a hole for transport and a hole for positioning are respectively formed in a copper-clad film in which copper foil is adhered to one side of a glass cloth-epoxy resin impregnated film having a thickness of mm, and then photo-patterning and the like are performed. By the method described above, a wiring group such as an inner lead and a signal line is formed. Further, a hole is formed by using a drill or the like to lead the wiring group to the other surface.
In addition, according to the outline of the resin sealing layer to be molded in a later step, a separating slit (approximately 0.5 mm in width) is formed by leaving four corners.

【0040】次いで、こうして得られた配線フィルムの
アイランド部に、半導体素子をダイボンドし、半導体素
子の電極端子とインナーリードとをワイヤボンディング
した後、その外側に、エポキシ樹脂のトランスファモー
ルドにより樹脂封止層を形成する。次に、こうして樹脂
封止がなされた配線フィルムの裏面に、はんだボールを
格子状に取り付け、バンプを形成する。
Next, the semiconductor element is die-bonded to the island portion of the wiring film thus obtained, and the electrode terminals of the semiconductor element and the inner leads are wire-bonded, and the outside thereof is resin-sealed by epoxy resin transfer molding. Form a layer. Next, on the back surface of the wiring film thus resin-sealed, solder balls are attached in a grid pattern to form bumps.

【0041】しかる後、図5に示すように、予め配線フ
ィルム28に形成された切り離し用スリット29の連結
部30に、それぞれ斜め方向に切断線(カットライン)
31を入れて、内側部分を外側の枠部から切り離し、半
導体装置を得る。なおこの図において、符号32は半導
体素子の外形線、33は樹脂封止層の外形線(トランス
ファモールドライン)、34はモールド時にゲートおよ
びエアーベントの位置に形成された余剰樹脂フロー部を
それぞれ示している。
Thereafter, as shown in FIG. 5, the connecting portions 30 of the separating slits 29 formed in advance in the wiring film 28 are cut obliquely (cut lines).
The semiconductor device is obtained by inserting 31 and separating the inner portion from the outer frame portion. In this drawing, reference numeral 32 denotes an outline of the semiconductor element, 33 denotes an outline of the resin sealing layer (transfer molding line), and 34 denotes an excess resin flow portion formed at the position of the gate and the air vent during molding. ing.

【0042】このように構成される第2の実施例におい
ては、ヴィアホール形成のための孔開けを、多数枚重ね
て効率的に行なうことができるうえに、図5に示したよ
うに、スリット29の四隅に残る連結部30を切断する
だけで、樹脂封止済みの半導体脂装置を容易に切り離す
ことができる。また、予め配線フィルムに形成されたス
リット29が、そのまま切り離しに利用され、かつスリ
ット29の形成は、後工程でのトランスファモールドラ
イン33に沿って行なわれ、このラインからの余白長さ
Lをほとんど採る必要がないので、CSP等の半導体装
置の小型化をより一層達成することができる。
In the second embodiment constructed as described above, holes for forming via holes can be efficiently formed by stacking a large number of holes, and as shown in FIG. By simply cutting the connecting portions 30 remaining at the four corners 29, the resin-sealed semiconductor oil device can be easily cut off. Further, the slit 29 previously formed in the wiring film is used as it is for cutting off, and the slit 29 is formed along a transfer mold line 33 in a later step, and the margin length L from this line is almost reduced. Since it is not necessary to employ the semiconductor device, it is possible to further reduce the size of a semiconductor device such as a CSP.

【0043】さらに、このような配線フィルムの段階で
のスリット29等の形成により、半導体素子の搭載前に
配線群の短絡や欠如等を電気的に評価することが可能と
なり、検査工程の簡略化を図ることができるうえに、歩
留まり向上にも寄与する。
Further, the formation of the slit 29 and the like at the stage of the wiring film makes it possible to electrically evaluate a short circuit or lack of the wiring group before mounting the semiconductor element, thereby simplifying the inspection process. In addition to contributing to the improvement of the yield.

【0044】またさらに、最終工程でのフィルム切断作
業が連結部のみの切断で良いので、工程管理や作業法が
著しく容易になるうえに、切断に超硬工具のような精密
工具を用いることができるので、高い歩留まりを達成
し、低価格化を図ることができる。さらに、超硬工具等
の使用により、余剰樹脂フロー部34も同時に切断する
ことができ、高品質のCSPを得ることができる。
Further, since the film cutting work in the final step can be performed by cutting only the connection portion, the process management and the working method are remarkably facilitated, and a precision tool such as a carbide tool is used for cutting. As a result, a high yield can be achieved and a price reduction can be achieved. Further, by using a carbide tool or the like, the surplus resin flow portion 34 can be cut at the same time, and a high-quality CSP can be obtained.

【0045】[0045]

【発明の効果】以上の説明から明らかなように、本発明
の第1の発明によれば、配線フィルムの作製において、
ヴィアホール形成の孔開けを、写真蝕刻法等で多数個同
時にかつ短時間で行なうことができるので、非常に安価
な加工が可能であり、半導体装置の価格低減に有効であ
る。また、絶縁性樹脂フィルムをベースとする配線フィ
ルムを補助板に仮止めして使用することにより、従来か
らのリードフレームを基材とするものと同一の工程で、
半導体装置の組み立て製造を行なうことができ、信頼性
の高い半導体装置を安価に得ることができる。
As is apparent from the above description, according to the first aspect of the present invention, in the production of a wiring film,
Since a large number of via holes can be formed simultaneously and in a short time by photolithography or the like, extremely inexpensive processing is possible, which is effective in reducing the price of semiconductor devices. Also, by temporarily fixing the wiring film based on the insulating resin film to the auxiliary plate and using it, in the same process as that using the conventional lead frame as the base material,
A semiconductor device can be assembled and manufactured, and a highly reliable semiconductor device can be obtained at low cost.

【0046】さらに、第2の発明の製造方法によれば、
最終工程での切り離し作業が容易であるうえに、樹脂封
止層の外形線からの余白(切り離し代)をほとんど採る
必要がないので、CSP等の半導体装置の小型化をより
一層達成することができる。
Further, according to the manufacturing method of the second invention,
Separation work in the final step is easy, and there is almost no need to take a margin (separation allowance) from the outline of the resin sealing layer, so that further miniaturization of semiconductor devices such as CSP can be achieved. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明において、フィルムに形成する切り線ま
たはスリットの形状を示す平面図。
FIG. 1 is a plan view showing a shape of a cut line or a slit formed in a film in the present invention.

【図2】本発明の第1の実施例に使用する配線フィルム
の形状を示す平面図。
FIG. 2 is a plan view showing the shape of a wiring film used in the first embodiment of the present invention.

【図3】図2におけるA部を拡大して示す平面図。FIG. 3 is an enlarged plan view showing a portion A in FIG. 2;

【図4】本発明の第1の実施例の各工程を説明するため
の断面図。
FIG. 4 is a cross-sectional view for explaining each step of the first embodiment of the present invention.

【図5】本発明の第2の実施例において、切り離し用切
断線(カットライン)を入れる位置を示す平面図。
FIG. 5 is a plan view showing a position where a cutting line for cutting (cutting line) is inserted in the second embodiment of the present invention.

【図6】従来からの方法で、カットラインを入れる位置
を示す平面図。
FIG. 6 is a plan view showing a position where a cut line is to be inserted by a conventional method.

【符号の説明】[Explanation of symbols]

12………絶縁性樹脂フィルム 13………搬送孔 15………切り離し用切り線 17………インナーリード 19………ヴィアホール用孔 20………配線 21………補助板 22………打抜き戻し部 24………半導体素子 25………ボンディングワイヤ 26………樹脂封止層 27………はんだバンプ 28………配線フィルム 29………切り離し用スリット 31………カットライン 33………トランスファモールドライン 34………余剰樹脂フロー部 12 ... Insulating resin film 13 ... Conveying hole 15 ... Cut-off line 17 ... Inner lead 19 ... Hole for via hole 20 ... Wiring 21 ... Auxiliary plate 22 ... .. Punch-back portion 24 semiconductor element 25 bonding wire 26 resin sealing layer 27 solder bump 28 wiring film 29 slit 31 for cutting 31 cut line 33 ……… Transfer mold line 34 ……… Excess resin flow section

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性樹脂フィルムの少なくとも一主面
に所要の配線群を形成するとともに、導通用の孔開けを
行なう工程と、 前記配線群が形成され孔開けがなされた配線フィルムの
前記一主面上の所定の位置に、半導体素子を実装する工
程と、 前記配線群が形成され孔開けがなされた配線フィルム
を、剛性を有する補助板上に配置し仮止めする工程と、 前記半導体素子の実装部を絶縁性樹脂により被覆し封止
する工程と、 前記絶縁性樹脂の封止層が形成された樹脂封止体から、
前記補助板の一部を取り外す工程と、 前記補助板が取り外されて露出した前記配線フィルムの
他主面に、外部接続端子を形成し、該外部接続端子をヴ
ィアホールを介して反対主面側の配線群と接続する工程
と、 前記外部接続端子が形成された樹脂封止体を、前記樹脂
封止層の外形線に沿って切り出す工程とを備えたことを
特徴とする半導体装置の製造方法。
1. A step of forming a required wiring group on at least one main surface of an insulating resin film and making holes for conduction, and forming the wiring group and forming one of the holes in the wiring film. A step of mounting a semiconductor element at a predetermined position on the main surface; a step of arranging and temporarily fixing a wiring film in which the wiring group is formed and perforated on an auxiliary plate having rigidity; A step of covering and sealing the mounting portion of the insulating resin with an insulating resin, from a resin sealing body on which a sealing layer of the insulating resin is formed,
Removing the part of the auxiliary plate, forming an external connection terminal on the other main surface of the wiring film exposed by removing the auxiliary plate, and connecting the external connection terminal to the opposite main surface side via a via hole A method of manufacturing a semiconductor device, comprising: a step of connecting the wiring group; and a step of cutting out a resin sealing body on which the external connection terminals are formed, along an outline of the resin sealing layer. .
【請求項2】 前記補助板上に仮止めされた配線フィル
ム上の所定の位置に、半導体素子を実装した後、前記半
導体素子の実装部を絶縁性樹脂により被覆し封止するこ
とを特徴とする請求項1記載の半導体装置の製造方法。
2. A semiconductor device is mounted at a predetermined position on a wiring film temporarily fixed on the auxiliary plate, and then a mounting portion of the semiconductor device is covered with an insulating resin and sealed. The method for manufacturing a semiconductor device according to claim 1.
【請求項3】 前記配線群の形成工程で、前記絶縁性樹
脂フィルムの所定の位置に、切り離し用の切り線または
スリットを形成することを特徴とする請求項1または2
記載の半導体装置の製造方法。
3. A cutting line or a slit is formed in a predetermined position of the insulating resin film in the step of forming the wiring group.
The manufacturing method of the semiconductor device described in the above.
【請求項4】 前記補助板が、予め切断線を入れて打ち
抜かれ嵌め戻された打抜き戻し部を有しており、前記補
助板の取り外し工程で、この打抜き戻し部を抜き外すこ
とを特徴とする請求項1乃至3のいずれか1項記載の半
導体装置の製造方法。
4. The method according to claim 1, wherein the auxiliary plate has a punch-back portion that has been cut out and fitted and cut back in advance, and the punch-back portion is removed in a step of removing the auxiliary plate. The method for manufacturing a semiconductor device according to claim 1, wherein:
【請求項5】 ガラスクロス−樹脂含浸フィルムの少な
くとも一主面に所要の配線群を形成し、導通用の孔開け
を行なうとともに、所定の位置に切り離し用の切り線ま
たはスリットを形成する工程と、 前記配線群が形成され孔開けがなされた配線フィルムの
前記一主面上の所定の位置に、半導体素子を実装する工
程と、 前記半導体素子の実装部を絶縁性樹脂により被覆し封止
する工程と、 前記絶縁性樹脂の封止層が形成された樹脂封止体におい
て、前記配線フィルムの他主面に外部接続端子を形成
し、該外部接続端子をヴィアホールを介して反対主面側
の配線群と接続する工程と、 前記外部接続端子が形成された樹脂封止体を、前記樹脂
封止層の外形線に沿って形成された前記切り線またはス
リットを用いて切り離す工程とを備えたことを特徴とす
る半導体装置の製造方法。
5. A step of forming a required wiring group on at least one main surface of the glass cloth-resin impregnated film, forming a hole for conduction, and forming a cut line or slit for separation at a predetermined position. A step of mounting a semiconductor element at a predetermined position on the one main surface of the wiring film in which the wiring group is formed and perforated; and covering and sealing a mounting portion of the semiconductor element with an insulating resin. And a step of forming an external connection terminal on the other main surface of the wiring film in the resin sealing body on which the sealing layer of the insulating resin is formed, and connecting the external connection terminal to the opposite main surface side via a via hole. And a step of separating the resin sealing body on which the external connection terminals are formed using the cut lines or slits formed along the outline of the resin sealing layer. That The method of manufacturing a semiconductor device according to symptoms.
【請求項6】 前記外部接続端子の形成工程において、
Pb/Sn系はんだを主成分とするバンプを、前記配線
フィルムの他主面に格子状に配列して形成することを特
徴とする請求項1乃至5のいずれか1項記載の半導体装
置の製造方法。
6. In the step of forming the external connection terminal,
6. The semiconductor device according to claim 1, wherein bumps mainly composed of Pb / Sn-based solder are formed in a grid pattern on the other main surface of the wiring film. Method.
JP28065397A 1997-08-01 1997-10-14 Manufacture of semiconductor device Withdrawn JPH11102944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28065397A JPH11102944A (en) 1997-08-01 1997-10-14 Manufacture of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9-208040 1997-08-01
JP20804097 1997-08-01
JP28065397A JPH11102944A (en) 1997-08-01 1997-10-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11102944A true JPH11102944A (en) 1999-04-13

Family

ID=26516606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28065397A Withdrawn JPH11102944A (en) 1997-08-01 1997-10-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11102944A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791173B2 (en) 2002-05-21 2004-09-14 Hitachi, Ltd. Semiconductor device and its manufacturing method
JP2008181977A (en) * 2007-01-23 2008-08-07 Fujitsu Ltd Package, manufacturing method thereof, semiconductor device using the same, and manufacturing method of semiconductor device using the same
JP2012248897A (en) * 2012-09-18 2012-12-13 Dainippon Printing Co Ltd Manufacturing method of component built-in wiring board, and component built-in wiring board
CN103594425A (en) * 2012-08-15 2014-02-19 长华电材股份有限公司 Packaging technology and structure of flexible substrate
KR101415489B1 (en) * 2012-09-24 2014-08-06 창 와 일렉트로메터리얼 인컴퍼니 Process of encapsulating non-rigid substrate and the substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791173B2 (en) 2002-05-21 2004-09-14 Hitachi, Ltd. Semiconductor device and its manufacturing method
US7170153B2 (en) 2002-05-21 2007-01-30 Elpida Memory, Inc. Semiconductor device and its manufacturing method
JP2008181977A (en) * 2007-01-23 2008-08-07 Fujitsu Ltd Package, manufacturing method thereof, semiconductor device using the same, and manufacturing method of semiconductor device using the same
CN103594425A (en) * 2012-08-15 2014-02-19 长华电材股份有限公司 Packaging technology and structure of flexible substrate
CN103594425B (en) * 2012-08-15 2016-06-22 长华电材股份有限公司 The packaging technology of flexible substrate and structure thereof
JP2012248897A (en) * 2012-09-18 2012-12-13 Dainippon Printing Co Ltd Manufacturing method of component built-in wiring board, and component built-in wiring board
KR101415489B1 (en) * 2012-09-24 2014-08-06 창 와 일렉트로메터리얼 인컴퍼니 Process of encapsulating non-rigid substrate and the substrate

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