JPH09116779A - Clock generating circuit and pulse generating circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a synchronization clock in a short time even at a weak electric field strength by providing a clock oscillation circuit so as to generate a clock signal synchronously with a rise detection pulse based on a flyback pulse. SOLUTION: A rise/fall detection circuit 14 detects a rise/fall of a flyback pulse outputted from a horizontal oscillation circuit 12. The rise detection pulse is given to a clock oscillation circuit 16 and the fall detection pulse is given to a counter 18a. The clock oscillation circuit 16 outputs a clock synchronously with the rise detection pulse to the counter 18a. Thus, the counter 18a is increased by the clock and reset by a fall detection pulse. A count is given to a timing decoder 18b which generates various pulses depending on the count.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit and a pulse generation circuit using the same, and more particularly to a clock generation circuit for generating a clock based on a horizontal frequency signal and a pulse generation circuit using the same.

[0002]

2. Description of the Related Art A conventional television receiver 1 shown in FIG.
Then, the sync signal included in the composite video signal is separated by the sync separation circuit 2, and the sync separation signal is given to the clock oscillation circuit 3 and the one-shot IC 4. Therefore, the clock oscillation circuit 3 generates a clock synchronized with the sync separation signal, and the one-shot IC 4 outputs a reset pulse based on the sync separation signal except in the horizontal sync signal period. The counter 6 included in the pulse generation circuit 5 operates by a clock and a reset pulse, and the pulse generation circuit 5 generates various pulses based on the count value of the counter 6.

[0003]

However, in such a conventional technique, since the clock is synchronized with the sync separation signal, the sync separation circuit appropriately outputs the sync signal when the electric field is weak or noise is large. If they cannot be separated, there is a problem that the clock oscillation circuit also malfunctions. In order to solve such a problem, a method of using a PLL circuit to generate a clock that is phase-locked to a sync separation signal is also conceivable, but this takes time until the phase is locked, and
There is a problem that the circuit configuration becomes complicated.

Therefore, a main object of the present invention is to provide a clock generation circuit and a pulse generation circuit using the same which can generate a clock synchronized with a horizontal frequency signal with a simple circuit. is there.

[0005]

According to the present invention, there is provided horizontal oscillating means for outputting a horizontal frequency signal, first detecting means for detecting either rising or falling of the horizontal frequency signal, and output of the first detecting means. Is a clock generation circuit having a clock generation means for generating a clock synchronized with.

[0006]

The first detecting means detects, for example, a rising edge of the horizontal frequency signal output from the horizontal oscillating means and outputs a rising edge detection pulse, for example. The clock generation means receives this rising edge detection pulse and generates a clock synchronized with this rising edge detection pulse. In the pulse generation circuit using such a clock generation circuit, for example, the second detection means detects, for example, the falling edge of the horizontal frequency signal, and, for example, the reset pulse generation means generates the reset pulse based on the detection result. To do. The counter operates by these clocks and reset pulses, and the pulse generation means generates various pulses based on the count value of the counter.

[0007]

According to the present invention, since the clock is generated based on the horizontal frequency signal output from the horizontal oscillating means, the circuit is simple and the horizontal level is ensured without depending on the received electric field strength. A clock synchronized with the frequency signal can be generated. The above object of the present invention,
Other objects, features and advantages will become more apparent from the following detailed description of embodiments, which proceeds with reference to the accompanying drawings.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a television receiver 10 of this embodiment includes a horizontal oscillation circuit 12, which is 15.7.
It outputs a flyback pulse of 34 kHz. The rising / falling detection circuit 14 receives the flyback pulse and detects its rising and falling. The rising edge detection pulse is N included in the clock oscillation circuit 16.
The clock oscillation circuit 16 outputs the clock synchronized with the rising edge detection pulse to the one end of the AND circuit 16a, and supplies the clock to the counter 18a included in the pulse generation circuit 18. On the other hand, the falling detection pulse is given to the counter 18a as a reset pulse. The counter 18a is a clock-synchronous counter that is incremented by a clock and reset by the next clock to which a reset pulse is applied. The count value of the counter 18a is given to the timing decoder 18b, and the timing decoder 18b generates various pulses according to the count value.

The structure of the rising / falling detection circuit 14 is shown in FIG. The switches SW1 and SW2 are turned on / off by the flyback pulse, which changes the terminal voltage of the capacitor C1. That is, FIG.
When the flyback pulse shown in (A) is at a low level, the switch SW1 is turned off and the switch SW2 is turned on, and the terminal voltage of the capacitor C1 becomes 0V.
Switch SW when flyback pulse becomes high level
1 is turned on, the switch SW2 is turned off, and the capacitor C1 is charged. Therefore, the capacitor C
The terminal voltage of 1 changes as shown in FIG. The flyback pulse and the terminal voltage of the capacitor C1 are NAND
Circuit 14a and 14b, respectively from FIG.
The rising detection pulse and the falling detection pulse shown in (C) and (E) are output. That is, when the flyback pulse is at high level and the terminal voltage of the capacitor C1 does not exceed the threshold value of the NAND circuit 14a, N
When the low level rising detection pulse is output from the AND circuit 14a, the flyback pulse is low level, and the terminal voltage of the capacitor C1 exceeds the threshold value of the NAND circuit 14b, the low level falling detection pulse is output from the NAND circuit 14b. Is output.

Returning to FIG. 1, the clock oscillation circuit 16 stops oscillating while the rise detection pulse is at a low level, and when the rise detection pulse rises, generates a clock synchronized with the rise. Therefore, the clock changes as shown in FIG. The counter 18a is incremented by this clock and reset by the falling detection pulse. Timing decoder 1
8b receives the count value of the counter 18a and outputs, for example, a blanking pulse shown in FIG.

According to this embodiment, the clock is synchronized with the rising detection pulse based on the flyback pulse, so that the synchronization clock can be generated in a short time even in the weak electric field. Further, since the fall detection pulse based on the flyback pulse is used as the reset pulse of the counter 18a, the reset pulse is given to the counter 18a while the clock is being output, and as a result, the counter 18a is a clock synchronous counter. Can be used.

Although the flyback pulse is generated by the horizontal oscillation circuit in this embodiment, a pulse for phase comparison created by a PLL circuit included in another signal processing system may be used. Of course. Also,
Although the television receiver 10 has been described in this embodiment, the present invention can of course be applied to any device using a horizontal oscillation circuit such as a VTR.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of the embodiment shown in FIG.

3A is a waveform diagram showing a flyback pulse, FIG. 3B is a waveform diagram showing a terminal voltage of a capacitor C1, FIG. 3C is a waveform diagram showing a rising detection pulse, and FIG. ) Is a waveform diagram showing a clock, (E) is a waveform diagram showing a falling detection pulse, and (F) is a waveform diagram showing a blanking pulse.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10 ... Television receiver 12 ... Horizontal oscillation circuit 14 ... Rising / falling detection circuit 18 ... Pulse generation circuit

Claims (2)

[Claims] 1. A horizontal oscillating means for outputting a horizontal frequency signal, a first detecting means for detecting either one of a rising edge and a falling edge of the horizontal frequency signal, and a clock synchronized with an output of the first detecting means. A clock generation circuit comprising a clock generation means for 2. A pulse generation circuit using the clock generation circuit according to claim 1, wherein the second detection means detects one of rising and falling of the horizontal frequency signal, and the second detecting means. A pulse generation circuit comprising: reset pulse generation means for generating a reset pulse based on an output; a counter operated by the clock and the reset pulse; and pulse generation means for generating a pulse based on a count value of the counter.