JPH10285428A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate stably a PLL circuit by inserting an optional random signal for a vertical blanking period of an input signal, so as to make an operating rate in the semiconductor integrated circuit thereby making consumption of current stable. SOLUTION: A vertical synchronization signal separator circuit lextracts a vertical synchronization signal from an input video signal and a pulse generating circuit 2 provides an output of a pulse for a vertical blanking period of the input video signal. A selector 4 inserts an output of a PN (pseudo-random noise) circuit 3 to the input video signal for the vertical blanking period. A delay circuit 6 delays the vertical blanking pulse by a delay time in a signal processing circuit 5 to extract the inserted PN signal, and a selector 8 inserts an output of a blanking level setting means 7 for a period which is equivalent to the vertical blanking period of the output signal. A horizontal synchronization signal separator circuit 9 separates a horizontal synchronization signal from the input signal, and a PLL circuit 10 recovers the clock signal to activate the entire circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, such as an audio processing device, which incorporates a PLL circuit in an electronic video device or is used as a peripheral circuit, or performs audio processing for reproducing audio data inserted during a vertical blanking period. Things.

[0002]

2. Description of the Related Art Conventional clock generation circuits are disclosed in
As disclosed in Japanese Patent Publication No. 309778, an attempt has been made to stabilize the operation of the PLL by performing a work during the vertical blanking period.

FIG. 9 shows an example of a conventional clock generation circuit. In FIG. 9, reference numeral 101 denotes a mono-multi vibrator, 1
02 is a sampling and holding circuit, 103 is a trazobaid generating circuit, 104 is a low-pass filter, 105 is a voltage controlled transmitting circuit, 106 is a counter, 111 and 112 are separating circuits, 118 is a selector, and 119 is a pulse generating circuit. FIG. 10 shows the operation at that time. The vertical synchronization signal separated by the synchronization signal separation circuit 111 (FIG.
Based on 0 (B)), the pulse generation circuit 119 generates a pulse indicating the vertical blanking period. (FIG. 10 (F)) Further, a period corresponding to the vertical blanking period of the horizontal synchronizing signal detected by the mono-multivibrator 101 is extracted by the selector 118 by the pulse. The output of the selector 118 is as shown in FIG. During the vertical blanking period of the input signal, there may be inserted a factor that makes clock recovery unstable, such as an equivalent pulse or a dubbing prevention signal. Therefore, even if such a signal is inserted, the sampling and holding circuit 102 , The PLL circuit including the trazobide generation circuit 103, the low-pass filter 104, the voltage control transmission circuit 105, and the counter 106 can be stably operated.

[0004]

However, according to the conventional clock generation circuit, since there is no signal during the vertical blanking period, when a large-scale system is integrated into a semiconductor integrated circuit and a PLL circuit is generated, an effective screen is generated. The operating ratio of the signal in the region and the operating ratio of the signal significantly change during the vertical blanking period, and the current consumption changes.
A change in current consumption leads to instability of the power supply voltage, and particularly in the case of a large-scale and high-frequency PLL circuit, it becomes an unstable factor in the operation of the PLL. And so on. Also,
In audio signal processing and the like, there is a problem that noise is synchronized with the vertical synchronization frequency.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a PLL circuit by inserting an arbitrary random signal during a vertical blanking period of an input signal, thereby stabilizing an operation rate in a semiconductor integrated circuit and stabilizing current consumption. And a semiconductor integrated circuit characterized by stable operation.

[0006]

According to the present invention, there is provided a vertical synchronizing signal separating circuit for extracting a vertical synchronizing signal from an input signal;
A pulse generation circuit for generating a blanking signal indicating a vertical blanking period of the input signal; a pseudo-random signal generation circuit for generating a pseudo-random signal; and a vertical blanking period in response to the blanking signal. A first selector for inserting a signal into an input signal, a signal processing circuit for performing some signal processing, a delay circuit for adjusting a delay time of the blanking pulse in the signal processing circuit, and an arbitrary blanking level. A second selector that inserts the blanking level into the output of the signal processing circuit during a vertical blanking period in response to the output of the delay unit; A horizontal synchronization signal separation circuit for extracting a synchronization signal, and a PLL for generating a clock from the horizontal synchronization signal
And a circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, there is provided a vertical synchronizing signal separating circuit for extracting a vertical synchronizing signal from an input signal, and a vertical blanking of the input signal when the vertical synchronizing signal is inputted. A pulse generating circuit for generating a blanking signal indicating a period, a pseudo random signal generating circuit for generating a pseudo random signal, and inserting the pseudo random signal into an input signal during a vertical blanking period in response to the blanking signal A first selector, a signal processing circuit for performing some signal processing, a delay circuit for adjusting the delay time of the blanking pulse in the signal processing circuit, and a blanking level for setting an arbitrary blanking level Setting means for inserting the blanking level into the output of the signal processing circuit during a vertical blanking period in response to the output of the delay unit. A second selector, and the horizontal synchronizing signal separating circuit for extracting a horizontal synchronizing signal from the input signal,
A PLL circuit for generating a clock from the horizontal synchronizing signal, wherein an arbitrary random signal is inserted during a vertical blanking period of an input signal to keep an operation rate in the semiconductor integrated circuit constant. By stabilizing the current consumption, the PLL circuit can operate stably.

Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to FIGS.

(Embodiment 1) In FIG. 1, 1 is a vertical synchronizing signal separation circuit, 2 is a pulse generation circuit, 3 is a PN circuit, 4 is a first selector, 5 is a signal processing circuit, and 6 is a delay circuit. , 7 are blanking level setting means, 8 is a second selector, 9 is a horizontal synchronizing signal separation circuit, and 10 is a PLL circuit. FIG. 2 is a diagram showing the internal structure of the PN circuit, wherein 11, 12, and 13 are flip-flops, 14 is an AND circuit, and 15 is an exclusive-logic NOR circuit. 3A and 3B are diagrams showing the operation of the present invention. FIG. 3A shows an input video signal, FIG. 3B shows a power supply voltage waveform when a semiconductor integrated circuit is operated in a large-scale system,
(C) is a vertical blanking pulse, (D) is an input signal to the signal processing circuit, and (E) is an output video signal.

The operation of the semiconductor integrated circuit configured as described above will be described. The vertical sync signal is extracted from the input video signal by the vertical sync separation circuit 1. On the basis of the extracted vertical synchronizing signal, the pulse generation circuit 2 outputs a pulse corresponding to the vertical blanking period of the input video signal. The PN circuit 3 is a circuit that generates a PN signal (PseudoNoise = pseudo random), and can generate a signal at random. The PN circuit of FIG. 2 is the most commonly known M
It is an example of a sequence PN code. The selector 4 inserts the output of the PN circuit 3 into the input video signal during the vertical blanking period in response to the output pulse of the pulse generation circuit 2 ((C) in FIG. 3). The input signal to the signal processing circuit 5 for performing main signal processing is as shown in FIG. In the case where the inside of a semiconductor integrated circuit is a CMOS, power consumption usually changes according to the operation rate of a signal. Therefore, in the effective screen area, the inside of the semiconductor integrated circuit operates according to the data of the video signal, but during the vertical blanking period, the inside of the semiconductor integrated circuit does not operate because the video signal is fixed data. Therefore, the power supply voltage waveform is affected by the circuit operation in the effective screen area as shown in FIG. 3B, but is not affected during the vertical blanking period. Therefore, when a PLL circuit is built in the same semiconductor integrated circuit, or when a PLL circuit is
When the LL circuit is installed, the operating point of the PLL differs between the effective screen area and the vertical blanking period, and the PLL circuit becomes unstable. By inserting noise, the inside of the semiconductor integrated circuit always operates in the same manner as in the effective screen area, so that the PLL circuit is stabilized.

The delay circuit 6 delays the vertical blanking pulse by a delay unit for delaying the inserted PN signal by a delay time in the signal processing circuit 5 so that the PN signal is output during a period corresponding to the vertical blanking period of the output signal. Since the blanking level at the blanking level 7 is inserted by the selector 8, the output signal is not affected. The horizontal synchronizing signal separating circuit 9 separates a horizontal synchronizing signal from an input signal, and reproduces a clock for operating the entire circuit in the PLL circuit 10 based on the separated synchronizing signal.

According to this configuration, an arbitrary random signal is inserted into the vertical blanking period of the input signal,
By stabilizing the operation rate in the semiconductor integrated circuit and stabilizing the current consumption, the PLL circuit can operate stably.

Next, another embodiment of the present invention will be described with reference to FIG. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 2) In FIG. 4, reference numeral 16 denotes a video signal detection circuit for detecting video information of an input signal, and 17 denotes a microcomputer for controlling a pseudo random signal generation circuit based on the result of the video detection circuit. . The operation of the semiconductor integrated circuit configured as described above will be described. The video signal detection circuit 16 detects video information of the input signal. For example, detection of a high frequency component of a signal is performed. The microcomputer 17 controls the PN circuit 3 based on the detection result of the video signal detection circuit 16. The PN circuit 3 can generate a plurality of PN signals, and switches the PN signals according to the content of the video information. For example, when the video signal is all white, the PN signal is also all bi.
The t-high level is fixed, and in the case of all black, the order of the PN signal and the bit to be inserted are changed to the low level of all bits in accordance with the ratio of the high frequency components when the frequency components are large. By doing so, a PN signal closer to the video signal can be inserted in the vertical blanking period, and the PLL circuit 10 can operate stably.

According to this configuration, by inserting an arbitrary random signal corresponding to the video signal during the vertical blanking period of the input signal, the operation rate in the semiconductor integrated circuit is made constant, and the current consumption is stabilized. Thus, the PLL circuit can be operated stably.

Next, another embodiment of the present invention will be described with reference to FIGS. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 3) In FIG. 5, reference numeral 4 denotes a selector for selecting an input video signal and an output signal obtained by delaying at least one line input signal of the signal processing circuit 5. FIG. 6 is an internal configuration diagram of the signal processing circuit 5, 18 is a line memory for delaying an input signal, and 19 is a main signal processing circuit. The operation of the semiconductor integrated circuit configured as described above will be described. The input video signal is a vertical sync separation circuit 1
Extracts the vertical synchronization signal. On the basis of the extracted vertical synchronizing signal, the pulse generation circuit 2 outputs a pulse corresponding to the vertical blanking period of the input video signal. In the selector 4, the output pulse of the pulse generation circuit 2 ((C) in FIG. 3)
, The output of the signal processing circuit 5 is inserted into the input video signal during the vertical blanking period. When a line memory is used inside the signal processing circuit 5 for performing main signal processing, the line data is used to select the image data of the last line of the effective screen from the selector 4 → the line memory 18 →
It is made to go around like a selector 4. By doing so, the inside of the semiconductor integrated circuit can be operated under the operating conditions substantially equal to the image data in the effective screen during the vertical blanking period. As described above, the PLL can be stabilized as in the first embodiment. When the first line information in the effective screen area is cyclically delayed by using a frame memory as an element for delaying an input signal, the data in the upper part of the screen and the data in the vertical blanking period can be more approximated. Can be further stabilized.

According to such a configuration, by circulating and inserting the signal in the effective screen area during the vertical blanking period of the input signal, the operation rate in the semiconductor integrated circuit is made constant and the current consumption is stabilized. Thus, the PLL circuit can be operated stably.

Next, another embodiment of the present invention will be described with reference to FIGS. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 4) In FIG. 7, reference numeral 20 denotes an audio processing circuit for reproducing audio from a signal in which audio data or the like is inserted during a vertical blanking period in an input video signal. FIG. 8 is a diagram showing the internal configuration of the audio processing circuit, where 21 is a main audio processing circuit, and 22 is a FIFO (First-
in, first-out). The operation of the semiconductor integrated circuit configured as described above will be described. The input video signal is a signal to which audio data is added during a vertical blanking period like a MUSE signal, for example. If the video signal is a video with little change, for example, all black, the audio data does not depend on the video data, and therefore, as shown in FIG. is there. The audio processing circuit 20 includes a main processing circuit 21 and a FIFO 22, and the main processing circuit performs, for example, frequency conversion and DPCM decoding in the case of a MUSE signal. The audio data in the vertical blanking period is expanded on the time axis using the FIFO 22, and is output as audio data. At this time, in the case of a signal such as the above-mentioned all black, the operation rate in the vertical blanking period is significantly increased as compared with the video signal period, so that the power supply voltage is fluctuated, resulting in vertical frequency audio noise. Will appear. When the PN signal is added to the video signal period by the PN circuit 3 (input signal in FIG. 8), the operation rate of the signal is maintained substantially the same over the entire period, and the above-described problem can be avoided.

According to such a configuration, by inserting an arbitrary random signal other than the additional information period such as audio data inserted in the vertical blanking period of the input signal, the operation rate in the semiconductor integrated circuit can be made constant. By stabilizing the current consumption, the audio signal processing circuit can be operated stably.

[0022]

As described above, according to the semiconductor integrated circuit of the present invention, the vertical synchronizing signal separating circuit for extracting the vertical synchronizing signal from the input signal, A pulse generating circuit for generating a blanking signal indicating a ranking period, a pseudo random signal generating circuit for generating a pseudo random signal, and inserting the pseudo random signal into an input signal during a vertical blanking period in response to the blanking signal A first selector, a signal processing circuit for performing some kind of signal processing, a delay circuit for adjusting the delay time of the blanking pulse in the signal processing circuit, and blanking for setting an arbitrary blanking level Level setting means for controlling the blanking level during the vertical blanking period in response to the output of the delay unit. An operating rate in the semiconductor integrated circuit by including a second selector to be inserted, a horizontal synchronizing signal separating circuit for extracting a horizontal synchronizing signal from the input signal, and a PLL circuit for generating a clock from the horizontal synchronizing signal And the current consumption is stabilized, whereby the PLL circuit can be operated stably.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a PN circuit according to the first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is an internal configuration diagram of a signal processing circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is an internal configuration diagram of an audio signal processing circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional clock generation circuit.

FIG. 10 is a diagram illustrating the operation of a conventional clock generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 vertical synchronization signal separation circuit 2 pulse generation circuit 3 PN circuit 4, 8 selector 5 signal processing circuit 6 delay circuit 7 blanking level setting means 9 horizontal synchronization signal separation circuit 10 PLL circuits 11, 12, 13 flip-flop 14 AND circuit Reference Signs List 15 Exclusive logic NOR circuit 16 Video signal detection circuit 17 Microcomputer 18 Line memory 19 Main processing circuit 20 Audio processing circuit 21 Main processing circuit 22 FIFO circuit

Claims (8)

[Claims] A vertical synchronizing signal separating circuit for extracting a vertical synchronizing signal from an input signal; a pulse generating circuit receiving the vertical synchronizing signal and generating a blanking signal indicating a vertical blanking period of the input signal; A pseudo-random signal generation circuit for generating a pseudo-random signal, a first selector for inserting the pseudo-random signal into an input signal during a vertical blanking period in response to the blanking signal, and a signal processing for performing some signal processing A delay circuit for adjusting a delay time of the blanking pulse in the signal processing circuit; a blanking level setting means for setting an arbitrary blanking level; and a vertical circuit in response to an output of the delay unit. During a blanking period, a second selector that inserts the blanking level into the output of the signal processing circuit and a horizontal selector based on the input signal. A horizontal synchronizing signal separating circuit for extracting a clock signal, and a P for generating a clock from the horizontal synchronizing signal.
A semiconductor integrated circuit comprising an LL circuit. 2. An arbitrary random signal is inserted in a vertical blanking period of an input signal to make an operation rate in a semiconductor integrated circuit constant and stabilize current consumption, thereby achieving a PL.
A semiconductor integrated circuit characterized by operating an L circuit stably. 3. A video signal detection circuit for detecting video information of an input signal, a microcomputer for controlling a pseudo random signal generation circuit based on a result of the video detection circuit, and extracting a vertical synchronization signal from the input signal. A vertical synchronization signal separation circuit,
A pulse generating circuit that receives the vertical synchronization signal and generates a blanking signal indicating a vertical blanking period of the input signal; and a pseudo random signal that generates at least two types of pseudo random signals under the control of the microcomputer. A first selector for inserting the pseudo-random signal into the input signal during a vertical blanking period in response to the blanking signal; a signal processing circuit for performing some signal processing; A delay circuit for adjusting a delay time in the signal processing circuit; blanking level setting means for setting an arbitrary blanking level; and a vertical blanking period in response to an output of the delay unit. A second selector inserted into an output of the signal processing circuit; and a horizontal synchronization signal extracting a horizontal synchronization signal from the input signal. The semiconductor integrated circuit comprising: the release circuit, and a PLL circuit for generating a clock from the horizontal sync signal. 4. A PLL circuit is provided by inserting an arbitrary random signal corresponding to a video signal during a vertical blanking period of an input signal to stabilize an operation rate in a semiconductor integrated circuit and stabilize current consumption. A semiconductor integrated circuit characterized by stable operation. 5. A vertical synchronizing signal separating circuit for extracting a vertical synchronizing signal from an input signal, a pulse generating circuit receiving the vertical synchronizing signal and generating a blanking signal indicating a vertical blanking period of the input signal, A signal processing circuit having at least a one-line delay unit and performing some kind of signal processing; and inserting an output of the one-line delay unit of the signal processing circuit into an input signal during a vertical blanking period in response to the blanking signal A first selector, a delay circuit for adjusting a delay time of the blanking pulse in the signal processing circuit, blanking level setting means for setting an arbitrary blanking level, and an output of the delay unit. And a second selector for inserting the blanking level into the output of the signal processing circuit during a vertical blanking period in response to the input signal. A horizontal synchronizing signal separating circuit for extracting a clock signal, and a P for generating a clock from the horizontal synchronizing signal.
A semiconductor integrated circuit comprising an LL circuit. 6. A PLL circuit that circulates and inserts a signal in an effective screen area during a vertical blanking period of an input signal to stabilize an operation rate in a semiconductor integrated circuit and stabilize current consumption. A semiconductor integrated circuit characterized by stable operation. 7. A vertical synchronizing signal separation circuit for extracting a vertical synchronizing signal from an input signal, and a source other than an additional information unit such as audio data to which the vertical synchronizing signal is input and inserted during a vertical blanking period of the input signal. A pulse generating circuit for generating a pulse indicating the following, a pseudo-random signal generating circuit for generating at least one kind of pseudo-random signal, and addition of audio data or the like inserted in a vertical blanking period in response to the pulse. A semiconductor integrated circuit comprising: a first selector that inserts the pseudo-random signal into an input signal except during an information period; and a signal processing circuit that reproduces audio data inserted during the vertical blanking period. 8. An operation rate in a semiconductor integrated circuit is made constant by inserting an arbitrary random signal other than an additional information period such as audio data inserted in a vertical blanking period of an input signal, thereby reducing current consumption. A semiconductor integrated circuit characterized by stably operating an audio signal processing circuit by stabilization.