KR0147315B1 - Synchronizing circuit for a video camera - Google Patents

Abstract

When inputting the reference signal to lock the video signal synchronization of the video camera from an external system from the outside, not only a separate signal line is required, but also the same reference signal must be supplied to each video camera when multiple video cameras are used together. This improves the length of the signal line and the complicated circuit configuration. To this end, a frequency of a commercial AC power source is detected to generate a power frequency signal having a detected frequency, and a phase difference between the two signals is detected by comparing a phase of the power frequency signal and a vertical synchronization signal generated inside the video camera. In response to the change in the phase difference, the oscillator generates a signal having a variable frequency and generates various synchronization signals of the video camera in synchronization with the oscillated signal. Therefore, the video signal synchronization between a plurality of video cameras is simply locked by using a commercial AC power supplied to the video camera without supplying a separate reference signal from the outside.

Description

Video recording circuit of video camera

1 is a block diagram of a conventional copper writing circuit.

2 is a circuit diagram of one embodiment of a copper writing circuit according to the present invention.

3A and 3B are operational waveform diagrams of respective parts of FIG.

4 is a circuit diagram of another embodiment of a copper writing circuit according to the present invention.

5 is a circuit diagram of yet another embodiment of a copper writing circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

16: power supply frequency detection circuit 18: waveform shaping circuit

20: phase comparator 22: oscillation control circuit

24, 28: lock kill oscillation circuit 26: timing signal generating circuit

30: selection circuit 32: internal oscillation circuit

34: level setting circuit 36: switch

38: VCO

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video cameras used in various video systems, and more particularly, to a copper recording circuit for locking video signal synchronization of a video camera with an external system.

In general, video systems used in closed circuit television or broadcasting studios use many video cameras. When using a plurality of video cameras as described above, if the video signal synchronization is not locked between video cameras, the video system cannot correctly process the signals transmitted from the video cameras. For example, when switching screens using a frame switcher or sequential switcher, noise will appear on the screen every time the screen is switched unless vertical synchronization is locked. Here, the frame switcher refers to a device that randomly selects a screen transmitted from one video camera among a plurality of video cameras and displays it on one monitor screen. A sequential switcher is a screen switcher that transmits a screen transmitted from a plurality of video cameras. A device that selects one by one and displays them on one monitor.

[0003] Conventionally, a video recording circuit as shown in FIG. 1 is employed in a video camera to lock horizontal synchronization, vertical synchronization, and color synchronization between video cameras in synchronization with a reference signal input from the outside of the video camera. As a video signal input as a reference signal in FIG. 1, a composite video signal normally processed in a video system is used. The composite video signal is a signal in which a horizontal sync signal, a vertical sync signal, a burst signal, and a video signal are combined. On the other hand, a signal in which only a horizontal synchronous signal, a vertical synchronous signal, and a burst signal are combined may be generated using a separate signal generator and input as a reference signal.

In FIG. 1, the video signal input from the outside of the video camera is commonly applied to the horizontal synchronous signal separation circuit 2 and the BPF (Band Pass Filter) 6.

The horizontal synchronous signal separation circuit 2 then separates the horizontal synchronous signal from the video signal and outputs it to the vertical synchronous signal separation circuit 4 and the timing signal generating circuit 14. The vertical synchronizing signal separating circuit 4 separates the vertical synchronizing signal from the horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit 2 and outputs it to the timing signal generating circuit 14.

In addition, the BPF 6 extracts the color signal carried on the color carrier of the video signal and applies it to the burst signal extraction circuit 8. Here, the pass band of the BPF 6 is set to the color carrier frequency band. For example, when the video signal is an NTSC video signal, the pass band of the BPF 6 is set to 3.58 MHz. The burst signal extraction circuit 8 extracts only the burst signal from the color signal output from the BPF 6 and applies it to the phase comparator 10. At this time, the color comparator carrier signal generated by the clock generation circuit 12 is applied to the phase comparator 10. Accordingly, the phase comparator 10 detects the phase difference between the two signals by comparing the phase of the burst signal extracted from the burst signal extraction circuit 8 with the color carrier signal generated by the clock generation circuit 12 and clocks the detected phase difference. The circuit 12 is fed back. Then, the clock generation circuit 12 generates a signal whose frequency is changed in response to the change in the phase difference input, and applies it to the timing signal generation circuit 14 as a reference clock signal.

The timing signal generation circuit 14 is a circuit for generating various synchronization signals required by the video camera. The timing signal generation circuit 14 is separated by the horizontal synchronous signal separation circuit 2 and the vertical synchronous signal separation circuit 4. The synchronization signal is generated in synchronization with the vertical synchronization signal and the reference clock signal generated by the clock generation circuit 12. In this way, the synchronization signals generated by the timing signal generation circuit 14 are locked to the video signals input as the reference signals.

Accordingly, the video camera having the copper recording locking circuit of FIG. 1 locks the video signal to the video signal input from the outside, thereby enabling accurate interworking with each other when connected to another video system.

However, as described above, when a reference signal for locking the video signal synchronization of the video camera with an external system is externally input, a separate signal line for the reference signal is required. In addition, when multiple video cameras are used in conjunction with a closed circuit television for surveillance, the same reference signal must be supplied to each video camera, so the signal line becomes longer and the circuit configuration of the video camera becomes complicated. There was a problem that a lot of restrictions on the circuit configuration.

Accordingly, an object of the present invention is to provide a recording recording circuit capable of locking video signal synchronization between a video camera and an external system without supplying a separate reference signal from the outside.

Another object of the present invention is to provide a recording recording circuit capable of locking video signal synchronization between a plurality of video cameras using a commercial AC power supply.

It is still another object of the present invention to provide a dynamic recording circuit capable of selectively locking the video signal synchronization of a camera to an external system.

The circuit of the present invention for achieving the above objects is a power frequency detection circuit for generating a power frequency signal having a detected frequency by detecting the frequency of a commercial AC power supply, the power frequency signal and the vertical synchronization generated inside the video camera A phase comparator for comparing the phases of the signals to detect phase differences between the two signals, an oscillation control circuit for generating an oscillation control voltage whose level changes in response to a change in the phase difference detected by the phase comparator, and corresponding to the level of the oscillation control voltage And a locking oscillation circuit for oscillating a signal having a variable frequency, and a timing signal generating circuit for generating synchronization signals in synchronization with the oscillation signal from the locking oscillation circuit. In addition, an internal oscillation circuit for oscillating a predetermined frequency signal and a selection circuit for selectively providing an output signal of any one of the rocking oscillation circuit and the internal oscillation circuit to a timing signal generation circuit in response to a locking mode in which a selection is set. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, it should be noted that like elements in the drawings represent like reference numerals wherever possible.

Also in the following description, numerous specific details such as specific circuit configurations and components are shown to provide a more general understanding of the invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

2 shows a circuit diagram of one embodiment of a copper writing circuit according to the present invention. In FIG. 2, the warping frequency detection circuit 16 detects the frequency of the commercial AC power supplied to the video camera and generates a power frequency signal having the detected frequency. The power frequency detection circuit 16 is a filter circuit that removes high frequency noise by low-pass filtering commercial AC power ACin and separates only the power frequency, and is connected between the filter circuit and the waveform shaping circuit 18 and outputted from the filter circuit. It consists of a waveform conversion circuit that converts the waveform of the waveform into a square wave signal and insulates it from the AC-side of the commercial AC power supply. The filter circuit consists of resistors R1 and R2 and capacitor C1 connected in series between the commercial AC power supply ACin and ground, and a capacitor C2 connected in parallel with the resistor R2. The waveform conversion circuit is composed of a photocoupler PT1 and a resistor R3 connected in parallel with the resistor R2.

The waveform shaping circuit 18 forms a waveform of the power frequency signal generated by the power frequency detecting circuit 16 and applies it to the reference signal input terminal R of the phase comparator 20.

The phase comparator 20 compares the phase of the vertical synchronization signal inputted to the comparison signal input terminal S and the power frequency signal inputted to the reference signal input terminal R, detects the phase difference between the two signals, and outputs the detected phase difference signal to the output terminal PBout. Output through The phase comparator 20 generally uses a widely used phase comparator IC. For example, TC5081, MC4046, etc. may be used. The vertical synchronization signal input to the phase comparator 20 is generated by the timing signal generation circuit 26 as described later.

The oscillation control circuit 22 generates an oscillation control voltage whose level changes in response to the change in the phase difference detected by the phase comparator 20. The oscillation control circuit 22 includes an integrating circuit for integrating the voltage level of the phase difference signal output from the phase comparator 20, and a voltage output circuit for outputting an oscillation control voltage having a level corresponding to the voltage level integrated in the integrating circuit. do. The integrating circuit consists of resistors R4 and R5 and capacitor C3 connected in series between the output terminal PBout of the phase comparator 20 and ground. The voltage output circuit includes a transistor Q1 at which a gate terminal is connected to a connection point of the resistors R4 and R5 through a resistor R6, a drain terminal is connected to a power supply voltage Vcc, and a source terminal is grounded through a resistor R7, It consists of a capacitor C4 connected between the gate terminal of transistor Q1 and ground. Here, the transistor Q1 uses a field effect transistor (FET).

The locking oscillation circuit 24 oscillates a reference clock signal whose frequency varies in accordance with the level of the oscillation control voltage and outputs it to the timing signal generation circuit 26. The locking oscillation circuit 24 includes an inverter IN1 having an output terminal connected to an input terminal of the timing signal generating circuit 26, a variable coil VL1 connected between an input terminal and an output terminal of the inverter IN1, and a variable coil. Between coil L1 connected in parallel with VL1, capacitor C5 and capacitive diode VD1 connected in series between the input terminal and ground of inverter IN1, and between the output terminal and ground of inverter IN1. A capacitor (C6) and a capacitance diode (VD2) connected in series with each other, a resistor (R8) connected between an output terminal of the oscillation control circuit (22) and a connection point of the capacitor (C5) and the capacitance diode (VD1), and an oscillation. The resistor R9 is connected between the output terminal of the control circuit 22 and the connection point of the capacitor C6 and the capacitance diode VD2.

The timing signal generation circuit 26 is a circuit for generating various synchronization signals required by a video camera like the timing signal generation circuit 14 of FIG. 1 described above, and locks and synchronizes the synchronization signals including the vertical synchronization signal 24. It is generated in synchronization with the reference clock signal input from the system.

3A and 3B are operation waveform diagrams of the respective parts of FIG.

3A illustrates waveforms of power frequency components of the commercial AC power supply ACin input to the power frequency detection circuit 16.

3A illustrates a waveform of a power frequency signal output from the power frequency detection circuit 16.

3B illustrates a waveform of a signal input to the reference signal input terminal R of the phase comparator 20 after the waveform is shaped by the waveform shaping circuit 18.

3B illustrates the waveform of the vertical synchronization signal generated by the timing signal generation circuit 26 and input to the comparison signal input terminal S of the phase comparator 20.

3B illustrates a waveform of a signal output from the output terminal PBout of the phase comparator 20. The portion shown in dotted lines in FIG. 3B (C) shows a high impedance state.

An operation example of FIG. 2 according to the present invention will now be described in detail with reference to the waveform diagrams of FIGS. 3A and 3B.

First, when the commercial AC power supply ACin is input to the power frequency detecting circuit 16, only the power frequency components of the commercial AC power supply ACin as shown in FIG. 3A by the resistors R1-R2 and the capacitors C1-C2. It is separated and applied to the light emitting diode of the photocoupler PT1. Accordingly, the emitter terminal of the light receiving transistor of the photocoupler PT1 outputs a power frequency signal having a square wave shape as shown in FIG. 3A (B). At this time, the photocoupler PT1 is insulated from the commercial AC power supply ACin side. The power frequency signal is applied to the reference signal input terminal R of the phase comparator 20 after shaping in the waveform shaping circuit 18 as shown in FIG. At this time, the waveform shaping circuit 18 shapes the power frequency signal in the same form as the waveform of the vertical synchronization signal. In addition, the vertical synchronization signal generated by the timing signal generation circuit 26 is applied to the comparison signal input terminal S of the phase comparator 20. Accordingly, the phase comparator 20 detects the phase difference by comparing the phase of the power frequency signal and the vertical synchronization signal. If the vertical synchronization signal changes as shown in FIG. 3B (B), a phase difference signal according to the phase difference is output as shown in FIG. 3B (C).

The output of the phase comparator 20 is input to the oscillation control circuit 22, which is integrated by the resistors R4 and R5 and the capacitor C8 and is current limited by the resistor R6 to the gate terminal of the transistor Q1. Is approved. As a result, an oscillation control voltage having a level corresponding to the change of the phase difference signal is output from the source terminal of the transistor Q1 and applied to the locking oscillation circuit 24. At this time, if the phase of the vertical synchronization signal becomes slower than the phase of the power frequency signal, the level of the oscillation control voltage is lowered, and if it is faster than the phase of the power frequency signal, the level of the oscillation control voltage is increased.

The locking oscillation circuit 24 outputs a signal whose oscillation is changed in frequency in response to the change of the oscillation control voltage level input from the oscillation control circuit 22 to the timing signal generation circuit 26 as a reference clock signal. The lower the control voltage, the lower the frequency of the reference clock signal, and the higher the oscillation control voltage, the higher the frequency of the reference clock signal. Thus, the reference clock signal is synchronized with the power frequency signal.

Accordingly, the synchronization signals generated by the timing signal generation circuit 26 are synchronized with the power frequency of the commercial AC power supply ACin. Therefore, the video signal synchronization between the video cameras or the video system employing the same recording recording circuit as described above is all locked to the power frequency. At this time, the vertical synchronization signal among the synchronization signals generated by the timing signal generation circuit 26 is also applied to the phase comparator 20 as described above.

Therefore, it is possible to lock video signal synchronization between a plurality of video cameras using a commercial AC power supply ACin without supplying a separate reference signal from the outside.

FIG. 4 is a circuit diagram of another embodiment of the same copper recording circuit according to the present invention, in which the selection circuit 30 and the internal oscillation circuit 32 are added in the circuit of FIG. Unlike the locking oscillation circuit 24 of FIG. 1, the operation can be controlled externally. Therefore, the power source frequency detecting circuit 16, the waveform shaping circuit 18, the phase comparator 20, the oscillation control circuit 22, and the timing signal generating circuit 26 are all the same as in Fig. 2 and the same reference numerals are used. Fill in. In addition, the power supply frequency detection circuit 16, the waveform shaping circuit 18, the phase comparator 20, and the oscillation control circuit 22 are abbreviate | omitted not shown.

In FIG. 4, the selection circuit 30 provides an output signal of any one of the locking oscillation circuit 28 and the internal oscillation circuit 32 to the timing signal generation circuit 26 selectively by the selection signal SEL. The locking mode is divided into an internal locking mode and an external locking mode, and is selected and set by the operator. The selection signal SEL is input in a different logic state depending on the selection setting of the locking mode. Generating the selection signal SEL to different logic states as the operator selects the locking mode generates a logic signal using a switch or the output of the switch through a processor for video camera control. The selection circuit 30 selects an output signal of the internal oscillation circuit 32 and outputs it to the timing signal generation circuit 26 when the locking mode is selected as the internal locking mode, and selects the output signal of the locking oscillation circuit 28 when the locking mode is selected as the external locking mode. The output signal is selected and output to the timing signal generation circuit 26. In addition, the selection circuit 30 operates the internal oscillation circuit 32 when the locking mode is selected as the internal locking mode, and operates the locking oscillation circuit 28 when the external locking mode is selected. When the selection signal SEL is input to the first logic state, the selection circuit 30 supplies power to the internal oscillation circuit 32 to operate the same, and blocks the operation of the locking oscillation circuit 28, and the selection signal SEL is the second logic. When inputted in the state, the operation selection circuit which cuts off the power supply to the internal oscillation circuit 32 and operates the locking oscillation circuit 28, and timings the outputs of the internal oscillation circuit 32 and the locking oscillation circuit 28. It consists of an output circuit applied to the signal generation circuit 26. The operation selection circuit is connected between the transistor Q2 having the emitter terminal connected to the power supply voltage Vcc and the collector terminal connected to the power input terminal of the internal oscillation circuit 32, and the emitter terminal and the base terminal of the transistor Q2. The inverter R2 connected between the selected resistor R12, the select signal SEL side and the base terminal of the transistor Q2, and the logic state of the select signal SEL to be applied to the locking oscillation circuit 28. ). The output circuit is composed of a negative logic gate NOR2 that negatively combines the outputs of the internal oscillation circuit 32 and the locking oscillation circuit 28.

The internal oscillation circuit 32 is operated by the power supply voltage Vcc supplied through the selection circuit 30 to oscillate a signal of a predetermined frequency.

The locking oscillation circuit 28 includes a negative logic gate NOR1 and a negative logic gate NOR1 having one input terminal connected to an output terminal of the inverter IN2 and an output terminal connected to one input terminal of the negative logic gate NOR2. Is connected in series between the variable coil VL2 connected between the other input terminal and the output terminal, the coil L2 connected in parallel with the variable coil VL2, and the other input terminal of the negative logic gate NOR1 and ground. Capacitor C7 and capacitive diode VD3, capacitor C8 and capacitive diode VD4 connected in series between the output terminal of negative logic gate NOR1 and ground, and the output terminal of oscillation control circuit 22 Connected between the connection point of the capacitor C7 and the capacitor diode VD3, and between the output terminal of the oscillation control circuit 22 and the connection point of the capacitor C8 and the capacitance diode VD4. It consists of a resistor R11.

Hereinafter, the operation example of FIG. 4 according to the present invention will be described in detail.

First, in FIG. 4, the oscillation control voltage applied from the oscillation control circuit 22 to the locking oscillation circuit 28 is the same as described in FIG. In addition, it is assumed that the selection signal SEL is applied to a logic high when the external locking mode is selected and is applied to a logic low when the internal locking mode is selected.

When the selection signal SEL is applied to the logic low in the above state, the transistor Q2 is turned on and the power supply voltage Vcc is supplied to the internal oscillation circuit 32 to operate the internal oscillation circuit 32. Since the output of the inverter IN2 that inverts the selection signal SEL becomes logic high, the output of the negative logic gate NOR1 of the locking oscillation circuit 28 is always logic low. Accordingly, the oscillation signal is output from the internal oscillation circuit 32, but oscillation does not occur in the locking oscillation circuit 28. The oscillation output signal from the internal oscillation circuit 32 is applied as a reference clock signal to the timing signal generation circuit 26 via the negative logic gate NOR2.

In contrast to the above, when the selection signal SEL is applied to a logic high, the transistor Q2 is turned off to block the supply of the power supply voltage Vcc to the internal oscillation circuit 32, thereby preventing the internal oscillation circuit 32 from operating. . Since the output of the inverter IN2 becomes a logic low, the negative logic gate NOR1 of the locking oscillation circuit 28 operates to generate oscillation. In the rocking oscillation circuit 28, as in the rocking oscillation circuit 24 of FIG. 2 described above, a signal whose oscillation is changed in frequency in response to a change in the oscillation control voltage level input from the oscillation control circuit 22 is used as a reference clock signal. Output The reference clock signal output from the locking oscillation circuit 28 is applied to the timing signal generation circuit 26 via the negative logic gate NOR2.

Therefore, the synchronization signals generated by the timing signal generator 26 are synchronized with the signals output from the internal oscillator circuit 32 according to the locking mode or by the power frequency of the commercial AC power supply ACin to synchronize the video signal of the video camera with the external system. Can be selectively locked on.

FIG. 5 is a circuit diagram of still another embodiment of the copper recording king circuit according to the present invention. Unlike FIG. 4, the locking oscillation circuit 28 and the internal oscillation circuit 32 are separately configured. Voltage Controlled Oscillator (hereinafter referred to as VCO) only. 5, the power source frequency detecting circuit 16, the waveform shaping circuit 18, the phase comparator 20, the oscillation control circuit 22, and the timing signal generating circuit 26 are the same as in FIG. Also written in the same manner. In addition, the power supply frequency detection circuit 16, the waveform shaping circuit 18, the phase comparator 20, and the oscillation control circuit 22 are abbreviate | omitted not shown.

In FIG. 5, the level setting circuit 34 generates a predetermined level of voltage. The level setting circuit 34 is composed of a resistor R14 and a variable resistor VR1 which divide a power supply voltage and set a voltage of a predetermined level.

The switch 36 selects the output of any one of the oscillation control circuit 22 and the level setting circuit 34 by the selection signal SEL and applies it to the VCO 38. The switch 36 uses an analog switch, such as MC4053, which is generally widely used.

The VCO 38 oscillates a signal having a frequency corresponding to the level of the voltage selected by the switch 36 and provides the oscillated signal to the timing signal generation circuit 26 as a reference clock signal.

Hereinafter, an operation example of FIG. 5 according to the present invention will be described in detail.

First, the oscillation control voltage is applied to one input terminal of the switch 36 from the oscillation control circuit 22 shown in FIG. 2 and the voltage of a predetermined level is applied from the level setting circuit 34 to the other input terminal of the switch 36. do. The switch 36 is also switched by the selection signal SEL as described above.

In the above state, if the selection signal SEL is applied to the logic low, the switch 36 selects the output of the level setting circuit 34 and applies it to the VCO 38. The VCO 38 then oscillates a signal having a frequency corresponding to a voltage at a predetermined level selected by the switch 36 and provides the oscillated signal to the timing signal generation circuit 26 as a reference clock signal.

Unlike the above, when the selection signal SEL is applied to the logic high, the switch 36 selects the output of the oscillation control circuit 22 and applies it to the VCO 38. The VCO 38 then oscillates a signal whose frequency changes in response to the level change of the oscillation control voltage selected by the switch 36 and provides the oscillated signal to the timing signal generation circuit 26 as a reference clock signal.

Therefore, the internal oscillation and external locking can be selected using only one VCO, thereby simplifying the configuration.

As described above, the present invention has the advantage that it is possible to simply lock the video signal synchronization of the video camera with an external system using a commercial AC power supply without supplying a separate reference signal from the outside.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, the present invention is illustrated to be applied to a video camera, but can be applied to all video systems using commercial AC power. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalents of the claims and the claims.

Claims (7)

A synchronization recording circuit for locking video signal synchronization of a video camera with an external system, comprising: a power frequency detection means for detecting a frequency of a commercial AC power source and generating a power frequency signal having a detected frequency; and a vertical synchronization signal; Timing signal generating means for synchronizing signals to a predetermined reference clock signal, phase comparing means for detecting a phase difference between two signals by comparing phases of the vertical synchronization signal and the power frequency signal, and detecting by the phase comparing means Oscillation control means for generating an oscillation control voltage whose level changes in response to the changed phase difference, locking oscillation means for oscillating the reference clock signal having a frequency corresponding to the level of the oscillation control voltage, and a predetermined frequency The internal oscillation means for oscillating the signal of Operating the internal oscillation means when it is selected and operating the locking oscillation means when it is selected as the external locking mode, and generating the timing signal by selecting an output signal of one of the locking oscillation means and the internal oscillation means according to the locking mode. And means for selecting which means is provided as said reference clock signal to said means. 2. The method according to claim 1, wherein the selection means supplies power to the internal oscillation means to operate when the selection signal indicating the locking mode is input to the first logic state, and blocks the operation of the locking oscillation means. Is input to the second logic state, the operation selection circuit which cuts off the power supply to the internal oscillation means and operates the locking oscillation means, and outputs the outputs of the internal oscillation means and the locking oscillation means to the timing signal generating means. And an output circuit to be applied as the reference clock signal. The negative logic gate NOR1 of claim 2, wherein the locking oscillation means comprises: a negative logic gate NOR1 having one input terminal connected to an output terminal of the operation selection circuit and an output terminal connected to one input terminal of the output circuit. Between the variable coil VL2 connected between the other input terminal and the output terminal of < RTI ID = 0.0 >), < / RTI > the coil L2 connected in parallel with the variable coil VL2, and the other input terminal of the negative logic gate NOR1 and ground. A capacitor C7 and a capacitance diode VD3 connected in series, a capacitor C8 and a capacitance diode VD4 connected in series between an output terminal of the negative logic gate NOR1 and a ground, and the oscillation control means. A resistor R10 connected between an output terminal of the output terminal and a connection point of the capacitor C7 and the capacitance diode VD3, and between an output terminal of the oscillation control means and a connection point of the capacitor C8 and the capacitance diode VD4. R11 connected And a recording recording circuit of a video camera. A synchronization recording circuit for locking video signal synchronization of a video camera with an external system, comprising: a power frequency detection means for detecting a frequency of a commercial AC power source and generating a power frequency signal having a detected frequency; and a vertical synchronization signal; A timing signal generating means for synchronizing signals to a predetermined reference clock signal, a waveform shaping means for shaping a waveform of the power frequency signal, a phase of the vertical synchronization signal and the waveform shaped power frequency signal, Phase comparison means for detecting a phase difference between signals, oscillation control means for generating an oscillation control voltage whose level changes in response to a change in the detected phase difference, level setting means for generating a predetermined level of voltage, and selection When the locking mode to be set is selected as the internal locking mode, the output voltage of the level setting means is selected. And when the external locking mode is selected, selecting means for selecting an output voltage of the oscillation control means corresponding to the selection, oscillating a signal having a frequency corresponding to the voltage level selected by the selecting means, and generating the oscillated signal. And a voltage controlled oscillation means for providing the timing signal generating means as the reference clock signal. 5. The filter circuit according to claim 4, wherein the power supply frequency detecting means is connected between the filter circuit and the waveform shaping means, the filter circuit being low-pass filtered the commercial AC power supply to remove high frequency noise and separating only the power supply frequency. And a waveform conversion circuit for converting a waveform of a signal output from the waveform into a square wave form. The oscillation control means according to claim 5, wherein the oscillation control means integrates the voltage level of the signal output from the phase comparing means, and a voltage outputting the oscillation control voltage having a level corresponding to the voltage level integrated in the integration circuit. A video recording circuit of a video camera, comprising: an output circuit. 7. The dynamic recording circuit of a video camera according to claim 6, wherein said level setting means comprises a resistor (R14) and a variable resistor (VR1) for setting a voltage of said predetermined level by dividing a power supply voltage by a predetermined voltage.