JPS62294282A - Personal computer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a video processing device for a personal computer (hereinafter referred to as a personal computer), and relates to a video processing device for a personal computer (hereinafter referred to as a personal computer). This is related to synchronizing the processing units.

[Conventional technology]

Recently, there has been a function to import video signals from TVs, VCRs, and other video equipment as still images (hereinafter referred to as digitization), and a function to display a computer screen overlaid on images from a video etc. (superimpression). (called a pose)
Many personal computers equipped with these functions are appearing on the market.

[Problem that the invention seeks to solve]

However, many of these conventional PCs only realize their functions when combined with a dedicated monitor, and in order to realize AV functions when connected to a home TV, they require the intermediary of an interface device that processes video. There were problems such as having to do it.

The present invention has been made in order to solve the problems of the above-mentioned conventional methods, and enables the basic functions of digitizing and superimposing to be realized even on a home television without the need for the intermediary of the above-mentioned interface device. The purpose is to provide a highly expandable personal computer that can

[Means for solving problems]

A personal computer according to the present invention includes a separating means for extracting a composite synchronizing signal from a received video signal, a separating means for extracting a vertical synchronizing signal from the composite synchronizing signal, and a separating means for extracting a vertical synchronizing signal from the received video signal, and a separating means for extracting the frequency and phase of the pseudo horizontal synchronizing signal from the horizontal synchronizing signal. It is equipped with a phase synchronization means that controls the frequency and phase to match, and enables the video processing section of the personal computer to be synchronized with an external video signal.

[Effect]

The personal computer of the present invention extracts a composite synchronization signal from a video signal in a synchronization signal separation section, further extracts a vertical synchronization signal from the extracted composite synchronization signal, and calculates the phase difference between these signals and a pseudo synchronization signal. A synchronizing means detects 17 and controls the frequencies and phases of both to match.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1 to 4.

FIG. 1 is a circuit diagram of the main parts of an embodiment of a personal computer according to the present invention, in which 1 is a reference oscillator (hereinafter referred to as O3C), 2 is a frequency dividing circuit that divides the OSCL output by N, and 3 is a phase In the synchronous circuit, 3a is a phase difference detection circuit that detects the frequency phase difference Δθ, 3b is a low-pass filter circuit (hereinafter referred to as an LPF circuit), and 3C is a voltage that changes the oscillation frequency according to the Vli!i pressure value from the LPF circuit 3b. Control detector (hereinafter referred to as v
4 is a frequency divider circuit to make the output of vCO3C the same frequency as the output of 08C1, 5 is the above frequency divider circuit 2, a frequency divider circuit that divides the frequency by N in the same way as 2, 6 is an external image A synchronization signal separation unit extracts a synchronization signal from the signal ■ (hereinafter referred to as ■ signal), 6a is a composite synchronization signal separation circuit that extracts a composite synchronization signal (hereinafter referred to as C5yne) from No. 743, and 6b is a vertical part in C5yne. Synchronization signal (hereinafter referred to as V
This is a vertical synchronization signal separation circuit that extracts the vertical synchronization signal (referred to as 5yne).

7a, the V signal has a period, phase, pulse 11 due to jitter etc.
7b is a pulse timing generation circuit that performs pulse conversion based on the ■ signal when @ is different from a predetermined value (standard *), and 7b similarly generates a pseudo horizontal synchronization signal (hereinafter referred to as Hsyne) from a pseudo synchronization signal generation circuit 8, which will be described later. ), and 8 is a pseudo synchronization circuit 9 for generating Hsync based on the output signal from the frequency dividing circuit 4.
This is a signal generation circuit.

Also shown are SW□, SW, and lf analog switches in the figure, which are switched by commands of the SEL signal.

2 to 4 are signal waveform diagrams of each part in FIG. 1, 31. S,,R,,Ryo,Δθ.

VI etc. correspond to each other.

The operation of this embodiment will be described below with reference to FIGS. 2 to 4. First, the operation of the synchronous circuit will be explained based on the waveform diagram in FIG.

In Figure 1, the output signal from oscl is divided by the frequency dividing circuit
A signal S1 whose frequency is divided by N by 2 and a signal R whose frequency is divided by the frequency dividing circuit 4 and the frequency dividing circuit 5 of the VCO 3c output.
The frequency and phase difference Δθ with respect to 1 is detected by the phase difference detection circuit 3a, and by passing through the LPF circuit 3b, Vl shown in FIG. do.

In VCO3c, a predetermined reference voltage value (not shown) and the above V
The oscillation frequency is changed by the difference in the voltage value of l. That is,
■C03C performs a follow-up operation so that S,=R□.

Next, the operation of extracting the synchronizing signal from video No. 48 and generating the timing (No. 6) based on the waveform diagram of FIG. 3 will be explained.

V signal from video equipment, etc.: C5yne is extracted at the composite sync signal separation circuit f3 t+ section of the sync signal separation section 6, and Vsyn is extracted at the vertical sync signal separation circuit 65 section.
c is extracted. (Figure 2 shows a vertical IRJ period signal diagram in the vicinity of the first field) Furthermore, the C
5ync is used to match the equivalent pulse near the vertical synchronization signal to the period of the horizontal synchronization signal, and to ensure that the period of the horizontal synchronization signal due to signal jitter etc. , Csy+1c are shown in Figure 3 (
It is converted by "rR!'I 'I' + pulse timing generation II!I approximately 711. of H No. S2.

Next, based on Fig. 4, the analog switch s is activated by the SEL signal.
When w,,sw,changes its contact point to the signal S,side, that is,
Explain how external synchronization works.

As can be seen from the figure, the signal (2) does not come at a constant cycle due to jitter, etc., but has fluctuations in the cycle. However, based on the pseudo Hsyne obtained by frequency dividing the VCO 3c, the pulse timing generation circuit 7b generates the signal R2, and as described above, the phase synchronization circuit 3 let S ,=
R* + (changes the oscillation frequency of vCo3c.

■Since the signal cycle becomes faster or slower,
As shown in FIG. 4, in order for signal R8 to follow signal St, it is necessary to detect the time difference between signal S and signal R. , if the signal S2 is faster than the signal R2, it is set to the old gh level, and if the signal S2 is slower than the signal Rt, it is set to the LOW level, so that vl becomes as shown in the figure, and vCo3
Voltage values above and below a predetermined reference voltage value of c are given to vCo3c.

As a result, the oscillation frequency is changed so that vCo3c becomes S,=R.

External synchronization can be achieved by the above operations.

Note that in this embodiment, the pulse timing generation circuit 7
If a and 7b are configured with monostable multi-oscillators, they will only be affected by the time constant of this oscillator, and will be less of a problem than signal jitter, etc., and stable operation can be expected.

In addition, in this example, the minimum necessary configuration was shown, but
Alternatively, there is no problem in configuring it using a video display processor IC, display controller IC, etc. that can generate pseudo C5ync or H5ynelt.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, stable external synchronization and internal synchronization can be achieved with a simple circuit configuration, and digitizing and superimposition functions can be performed without the need for an intermediary interface device. In addition, it can be realized even with a general home television, and it is possible to provide a personal computer that is simple and highly expandable, unlike conventional computers.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a circuit diagram of a main part of an embodiment of the present invention, and Figs.
FIG. 4 is a signal waveform diagram for explaining the operation. In the figure, 3 is a phase synchronization circuit, 3a is a phase difference detection circuit, 3
a If T-P F circuit, 3b is vCo, 9 is a sync signal separation section, 6A is a composite sync signal separation circuit, 6b is a vertical sync signal separation circuit, 7n and 7hl are pulse timing generation circuits, 8 is a pseudo sync signal generation Shows the circuit. Agent Masuo Oiwa (2 others); l-1 times 6 Domo 1i Yoshiaki Kensai 2 Figure 80 ■ :) r3 Figure 4 Figure ■

Claims (1)

[Claims] Composite synchronization signal separation means for extracting a composite synchronization signal from a received video signal, vertical synchronization signal separation means for extracting a vertical synchronization signal from the composite synchronization signal, and pseudo horizontal synchronization obtained by dividing the reference oscillator output. and phase synchronization means for controlling the pseudo horizontal synchronization signal by detecting the phase difference between the two so that the frequency and phase of the signal match the frequency and phase of the horizontal synchronization signal from the synchronization signal separation means, A personal computer characterized in that a video processing unit of the computer can be synchronized with an external video signal.