JPH0897484A - Gainas hetero-junction hall device - Google Patents

Gainas hetero-junction hall device

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Publication number
JPH0897484A
JPH0897484A JP6235589A JP23558994A JPH0897484A JP H0897484 A JPH0897484 A JP H0897484A JP 6235589 A JP6235589 A JP 6235589A JP 23558994 A JP23558994 A JP 23558994A JP H0897484 A JPH0897484 A JP H0897484A
Authority
JP
Japan
Prior art keywords
layer
gainas
inp
heterojunction
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6235589A
Other languages
Japanese (ja)
Inventor
Takashi Udagawa
隆 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP6235589A priority Critical patent/JPH0897484A/en
Publication of JPH0897484A publication Critical patent/JPH0897484A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To relieve a displacement force which is introduced into a GaInAs magneto-sensitive layer by a thermal process, etc., and avoid the decline of the electron mobility of the base material by a method wherein the GaInAs layer is provided between two compound semiconductor layers which have a specific difference between their thicknesses, are made of the same material and are formed on a semiconductor substrate. CONSTITUTION: A buffer layer 102 which is made of undoped n-type InP epitaxial crystal and has a thickness about 100nm is formed on a substrate 101 by a normal pressure MOVPE method. An n-type Gax In1-x As layer (wherein (x) is 0<=x<=1) which is a magneto-sensitive layer 103 is formed on the buffer layer 102 by an atmospheric pressure MOVPE method. An n-type InP layer which is made of the same compound semiconductor as the layer 102 is formed on the magneto-sensitive layer 103 as a contact layer 104. With this constitution, an InP/GaInAs/InP double-hetero-junction can be formed. The difference between the thickness of the contact layer 104 and the thickness of the buffer layer 102 is less than 65%, for instance 120nm.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】化合物半導体ホール素子に係わ
り、特にGax In1-x Asを含んでなる2重(ダブ
ル)ヘテロ接合ホール素子の高感度化に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor Hall element, and more particularly to high sensitivity of a double (double) heterojunction Hall element containing Ga x In 1-x As.

【0002】[0002]

【従来の技術】ホール(Hall)素子は磁束密度に応
じて電圧を発生する磁電変換素子である。ホール素子は
一種の磁気センサーであり、回転検出センサーや電流セ
ンサー等として産業界で既に利用されている。
2. Description of the Related Art A Hall element is a magnetoelectric conversion element that generates a voltage according to a magnetic flux density. The Hall element is a kind of magnetic sensor and is already used in industry as a rotation detection sensor, a current sensor, and the like.

【0003】ホール素子は従来からSi等の元素半導体
の他、GaAsやInSbなどの化合物半導体で構成さ
れている。最近では、高性能ホール素子の要望に対応し
てGaInAsとInPとのヘテロ接合からなる新たな
高感度ホール素子も報告されている(奥山 忍他、19
92年秋季第53回応用物理学会学術講演会予稿集N
o.3(応用物理学会発行)、講演番号16a−SZC
−16、1078頁)。このGaInAsヘテロ接合系
では12,000cm2 /V・s程度の高い室温電子移
動度が得られるため(小沼 賢二郎他、第53回応用物
理学会学術講演会予稿集、18a−ZE−3)、ホール
素子の高感度化に優位である。
Hall elements have conventionally been composed of compound semiconductors such as GaAs and InSb in addition to elemental semiconductors such as Si. Recently, in response to the demand for high-performance Hall elements, a new high-sensitivity Hall element composed of a heterojunction of GaInAs and InP has been reported (Okuyama Shinobu et al., 19
1992 Autumn 53rd Annual Meeting of the Japan Society of Applied Physics Proceedings N
o. 3 (Published by Japan Society of Applied Physics), Lecture No. 16a-SZC
-16, 1078). Since this GaInAs heterojunction system can obtain room temperature electron mobility as high as about 12,000 cm 2 / V · s (Kenjiro Onuma et al., Proc. Of the 53rd Annual Meeting of the Society of Applied Physics, 18a-ZE-3), Hall. This is advantageous for increasing the sensitivity of the device.

【0004】従来のGaInAsホール素子は、高抵抗
の半絶縁性InP単結晶基板上に堆積した一層のInP
と一層のGaInAsとからなる単一(シングル)ヘテ
ロ接合から構成されている(奥山 忍他、1992年秋
季第53回応用物理学会学術講演会予稿集No.3(応
用物理学会発行)、講演番号16a−SZC−16、1
078頁)。通常、この単一ヘテロ接合系はInP等の
緩衝層を先ず基板上に設け、その後、バンドギャップの
小さいGaInAsを堆積する。緩衝層は基板結晶から
の不純物等の感磁層への侵入を軽減するため設けるもの
である。バンドギャップの小さいGaInAsを最表層
とするのは、オーミック性電極を得易くするためであ
る。
A conventional GaInAs Hall element is a layer of InP deposited on a high-resistance semi-insulating InP single crystal substrate.
And a single layer of GaInAs (single) heterojunction (Okuyama Shinobu et al., Autumn 1992 53rd Annual Meeting of the Society of Applied Physics, Proceedings No. 3 (published by the Society of Applied Physics), Lecture No. 16a-SZC-16, 1
078). Typically, this single heterojunction system first provides a buffer layer, such as InP, on the substrate and then deposits GaInAs with a small bandgap. The buffer layer is provided to reduce the penetration of impurities and the like from the substrate crystal into the magnetic sensing layer. GaInAs having a small band gap is used as the outermost layer in order to easily obtain an ohmic electrode.

【0005】また、単一ヘテロ接合ではなく、GaIn
As層との2重(ダブル)のヘテロ接合を擁するGaI
nAsダブルヘテロ接合ホール素子も知られている
(Y.Sugiyama、Technical Dig
est of the 11thSensor Sym
posium(1992)、79頁)。このホール素子
はGaInAs層をAl0.48In0.52As層で挟み込ん
だ、GaInAs/AlInAsダブルヘテロ接合を含
んでいる。即ち、GaInAs層の上下両面共に同じA
0.48In0.52As層がヘテロ接合している。但し、G
aInAs層とのダブルヘテロ接合を構成するAl0.48
In0.52As層の膜厚は大幅に異なっている。GaIn
As層の直下でヘテロ接合しているAl0.48In0.52
s層の膜厚は400nmである。一方、GaInAs層
の上面側でヘテロ接合するAl0.48In0.52As層の膜
厚は5nmとなっている。従って、GaInAs層の下
面側のAl0.48In0.52As層の膜厚の1.25%の薄
さとなっている。現在迄に、ヘテロ接合ホール素子用と
してのGaInAs感磁層の上下にヘテロ接合させる化
合物半導体層の膜厚を規定した例は知られていない。
Further, it is not a single heterojunction but GaIn.
GaI with a double (double) heterojunction with the As layer
An nAs double heterojunction Hall element is also known (Y. Sugiyama, Technical Dig).
est of the 11th Sensor Sym
podium (1992), p. 79). This Hall element includes a GaInAs / AlInAs double heterojunction in which a GaInAs layer is sandwiched by Al 0.48 In 0.52 As layers. That is, the same A on both upper and lower sides of the GaInAs layer
l 0.48 In 0.52 As layers are heterojunctions. However, G
Al 0.48 forming a double heterojunction with the aInAs layer
The thickness of the In 0.52 As layer is significantly different. GaIn
Al 0.48 In 0.52 A heterojunction directly under the As layer
The film thickness of the s layer is 400 nm. On the other hand, the film thickness of the Al 0.48 In 0.52 As layer heterojunction on the upper surface side of the GaInAs layer is 5 nm. Therefore, the thickness is 1.25% of the thickness of the Al 0.48 In 0.52 As layer on the lower surface side of the GaInAs layer. Up to the present, there is no known example in which the film thickness of the compound semiconductor layer to be heterojunctioned above and below the GaInAs magnetosensitive layer for the heterojunction Hall element is defined.

【0006】シングル或いはダブルヘテロ接合系に拘ら
ず、感磁層とするGaInAs層とそれとヘテロ接合を
構成するために用いられている従来の化合物半導体層と
では熱膨張率には差がある。例えばInPの線膨張率は
4.6×10-6/℃である(永井 治男 他著、『 III
−V族半導体混晶』(昭和63年10月25日、コロナ
社発行)、52頁参照)。また、Al0.48In0.52As
層のそれは、ほぼ5.2×10-6/℃と算出される。一
方、Ga0.47In0.53Asのそれは、5.8×10-6
℃と計算される。この線膨張率の差に起因して、化合物
半導体層の成長に必要な昇温、降温過程でGaInAs
感磁層に歪が導入される。特に、従来の如くGaInA
sとInPとのシングルヘテロ構造に於いては、GaI
nAs感磁層の一面は線膨張率の異なるInPと接合
し、他の面は開放されているため、GaInAs感磁層
が変位を被り易い欠点があった。
Regardless of the single or double heterojunction system, there is a difference in the coefficient of thermal expansion between the GaInAs layer serving as the magnetic sensing layer and the conventional compound semiconductor layer used for forming the heterojunction with the GaInAs layer. For example, the linear expansion coefficient of InP is 4.6 × 10 −6 / ° C. (Hario Nagai et al., “III.
-Group V semiconductor mixed crystals "(October 25, 1988, published by Corona Publishing Co.), p. 52). In addition, Al 0.48 In 0.52 As
That of the layer is calculated to be approximately 5.2 × 10 −6 / ° C. On the other hand, that of Ga 0.47 In 0.53 As is 5.8 × 10 −6 /
Calculated as ° C. Due to this difference in the coefficient of linear expansion, GaInAs is generated during the temperature rising / falling process necessary for growing the compound semiconductor layer.
Strain is introduced into the magnetosensitive layer. Especially, as in the past, GaInA
In the single heterostructure of s and InP, GaI
Since one surface of the nAs magnetosensitive layer is bonded to InP having a different linear expansion coefficient and the other surface is open, there is a drawback that the GaInAs magnetosensitive layer is easily displaced.

【0007】感磁層に歪が導入されると電子移動度の低
下を招く。電子移動度が低下するとホール素子の重要な
特性である積感度が低下する。また、特にシングルヘテ
ロ接合では一面が開放されているGaInAs感磁層が
変位し歪み、母体材料に「反り」を生ずる。この「反
り」が大きいとフォトリソグラフィー用の露光マスクと
被パターニング体、即ち母体材料との密着度が不均一と
なる。これにより、感磁層の均一な精密パターニングが
困難となり、感磁層の形状の非対称性等に起因する不平
衡電圧も悪化する。不平衡電圧とは、零磁界下で発生す
るホール電圧を指す(片岡 照栄著、「磁電変換素子」
(昭和46年2月、日刊工業新聞社発行)、61頁)。
When strain is introduced into the magnetosensitive layer, electron mobility is lowered. When the electron mobility decreases, the product sensitivity, which is an important characteristic of the Hall element, decreases. Further, particularly in a single heterojunction, the GaInAs magnetosensitive layer whose one surface is open is displaced and distorted, causing "warpage" in the base material. If this "warp" is large, the degree of adhesion between the exposure mask for photolithography and the object to be patterned, that is, the base material becomes non-uniform. As a result, it becomes difficult to perform uniform and precise patterning of the magnetosensitive layer, and the unbalanced voltage due to the asymmetry of the shape of the magnetosensitive layer also deteriorates. Unbalanced voltage refers to the Hall voltage generated under zero magnetic field (Kataoka Teruei, "Magnetic-electric conversion element").
(Published by Nikkan Kogyo Shimbun, February 1972), p. 61).

【0008】[0008]

【発明が解決しようとする課題】GaInAs感磁層が
被る変位の量はワープ(warp)として定量的に計測
できる。ワープとは図3に模式的に示す様に、例えばG
aInAsの感磁層(103)とInPの緩衝層(10
2)とからなるシングルヘテロ構造に「反り」がある場
合、「反り」の最下点(110)と最高点(111)と
の高低差(112)で定義される変位量である。基板と
なるInP或いはGaAs結晶のワープは概ね10-3
m未満である。しかしながら、本発明者が鋭意検討した
結果では、例えばInP単結晶基板上に形成したInP
/GaInAsシングルヘテロ接合材料のワープは基板
結晶自体のそれの2〜5倍に到達することがあった。こ
の様にワープが大きくなると、上記の如くGaInAs
ヘテロ接合ホール素子の特性の劣化を招く。従って、本
発明では感度特性に優れ且つ不平衡電圧を低く抑制した
高性能のGaInAsヘテロ接合ホール素子を得るべ
く、従来のヘテロ接合構造材料に於いてGaInAs感
磁層が被る変位を軽減できる、新たな積層構成を見出
す。
The amount of displacement that the GaInAs magnetosensitive layer undergoes can be quantitatively measured as a warp. The warp is, for example, G as shown in FIG.
aInAs magnetic sensitive layer (103) and InP buffer layer (10
When the single heterostructure consisting of 2) has a “warp”, it is the amount of displacement defined by the height difference (112) between the lowest point (110) and the highest point (111) of the “warp”. The warp of the InP or GaAs crystal used as the substrate is about 10 -3 c
It is less than m. However, as a result of earnest studies by the present inventors, for example, InP formed on an InP single crystal substrate
The warp of the / GaInAs single heterojunction material could reach 2-5 times that of the substrate crystal itself. When the warp becomes large like this, as described above, GaInAs
This causes deterioration of the characteristics of the heterojunction Hall element. Therefore, in the present invention, in order to obtain a high-performance GaInAs heterojunction Hall element having excellent sensitivity characteristics and suppressing unbalance voltage to a low level, it is possible to reduce the displacement of the GaInAs magnetosensitive layer in the conventional heterojunction structure material. Find a simple laminated structure.

【0009】[0009]

【課題を解決するための手段】即ち、本発明はGax
1-x As(xは組成比を表し、0<x<1である。)
を含むヘテロ接合を具備してなるGaInAsヘテロ接
合ホール素子に於いて、該Gax In1-x Asが膜厚の
差異が±65%以内である同一の化合物半導体層の中間
に挿入した、ダブルヘテロ接合材料からホール素子を構
成する。上記の同一の化合物半導体層としてはInP、
AlInAs、GaInP若しくはAlInPのいずれ
かが利用できる。
That is, the present invention provides Ga x I
n 1-x As (x represents a composition ratio, and 0 <x <1.)
In a GaInAs heterojunction Hall element comprising a heterojunction including a double bond, the Ga x In 1-x As is inserted in the middle of the same compound semiconductor layer having a thickness difference of ± 65% or less. A Hall element is made of a heterojunction material. As the same compound semiconductor layer, InP,
Either AlInAs, GaInP or AlInP can be used.

【0010】例えば感磁層のGax In1-x Asをn形
のInP層の中間に挿入させると、Gax In1-x As
とInPとのダブルヘテロ接合を得ることができる。同
じく、Gax In1-x As層の上下両側にn形GaIn
Pを設ければ、同一の化合物半導体積層の中間にGax
In1-x Asが配置されたダブルのヘテロ接合構造を構
成できる。また、Gax In1-x As層の直下の化合物
半導体層をGa0.51In0.49Pとした場合は、Gax
1-x As層の上側にヘテロ接合させる化合物半導体層
もGa0.51In0.49Pとする。GaInPやAlInA
s等の3元化合物半導体層でGax In1-x Asを挟み
込む場合、GaやAl等の組成比も同一とするのが好ま
しい。同様に、AlInAs層若しくはAlInP層を
Gax In1-x As感磁層の両側に配置すれば、AlI
nAs/Gax In1-x As/AlInAs、AlIn
P/Gax In1-x As/AlInPからなるダブルヘ
テロ接合構造を形成できる。
For example, when Ga x In 1-x As of the magnetic sensitive layer is inserted in the middle of the n-type InP layer, Ga x In 1-x As is formed.
A double heterojunction between InP and InP can be obtained. Similarly, n-type GaIn is formed on both upper and lower sides of the Ga x In 1-x As layer.
If P is provided, Ga x is formed in the middle of the same compound semiconductor stack.
A double heterojunction structure in which In 1-x As is arranged can be formed. When the compound semiconductor layer immediately below the Ga x In 1-x As layer is Ga 0.51 In 0.49 P, Ga x I
The compound semiconductor layer to be heterojunction above the n 1-x As layer is also Ga 0.51 In 0.49 P. GaInP and AlInA
When Ga x In 1-x As is sandwiched by ternary compound semiconductor layers such as s, it is preferable that the composition ratios of Ga and Al are also the same. Similarly, if an AlInAs layer or an AlInP layer is arranged on both sides of the Ga x In 1-x As magneto - sensitive layer, AlI
nAs / Ga x In 1-x As / AlInAs, AlIn
A double heterojunction structure composed of P / Ga x In 1-x As / AlInP can be formed.

【0011】上記の様にGax In1-x As層の上下に
は同一の化合物半導体層を設ける。即ち、Gax In
1-x As層を同一の化合物半導体層で挟み込んだ構造と
する。Gax In1-x As層の両側に同一の化合物半導
体層を配置することにより、膨張率が同一の物質で挟み
込めばGax In1-x As感磁層に掛かる歪応力を軽減
できる。キャリア濃度は感磁層の両側で必ずしも同一と
する必要はない。
As described above, the same compound semiconductor layer is provided above and below the Ga x In 1-x As layer. That is, Ga x In
The 1-x As layer is sandwiched between the same compound semiconductor layers. By arranging the same compound semiconductor layer on both sides of the Ga x In 1-x As layer, can reduce the distortion stress expansion coefficients is applied to the Ga x In 1-x As feeling free layer if Hasamikome the same material. The carrier concentration does not necessarily have to be the same on both sides of the magnetosensitive layer.

【0012】Gax In1-x As層の上下双方にダブル
ヘテロ接合を形成するために設けるInP、AlInP
等の膜厚の差は、双方共65%以内の差異内に収納させ
る。ここで、膜厚の差異はGax In1-x As層に対し
て下方側に在る基板側でヘテロ接合させている化合物半
導体層の膜厚を基準にして次の式(1)の如く定義す
る。 膜厚の差異(%)=|(tu −t1 )/t1 |×100 ・・・・式(1) ここで、tu はGax In1-x As感磁層の上側に設け
る化合物半導体層の膜厚である。t1 は基準とするGa
x In1-x As感磁層の下側に設ける化合物半導体層の
膜厚である。従って、膜厚の差異はtu とt1 の差の絶
対値を基に求められる。例えば、InP/Gax In
1-x As/InPヘテロ系では、Gax In1-x As感
磁層の直下のInP緩衝層の膜厚を100nmとし、感
磁層の直上に膜厚が35nm以上で165nm以下のI
nP層を設ければ本発明の規定を満足できる。感磁層の
上下に設ける化合物半導体層の膜厚が本発明の規定を越
えると線膨張率の差に起因してGax In1-x As層が
被る歪の導入量が顕著に増加する。Gax In1-x As
層の両側に設ける化合物半導体層の膜厚が双方で極端に
異なるとGax In1-x As層に「反り」が発生するた
め、好ましくない。
InP and AlInP provided to form a double heterojunction both above and below the Ga x In 1-x As layer.
The difference in film thickness between the two is accommodated within the difference within 65%. Here, the difference in film thickness is expressed by the following formula (1) based on the film thickness of the compound semiconductor layer which is hetero-junctioned on the substrate side below the Ga x In 1-x As layer. Define. Film thickness difference (%) = | (t u −t 1 ) / t 1 | × 100 (1) where t u is provided on the upper side of the Ga x In 1 -x As magnetosensitive layer. It is the film thickness of the compound semiconductor layer. t 1 is the standard Ga
x In 1-x As is the film thickness of the compound semiconductor layer provided below the magnetosensitive layer. Therefore, the difference in film thickness is obtained based on the absolute value of the difference between t u and t 1 . For example, InP / Ga x In
In the 1-x As / InP hetero system, the film thickness of the InP buffer layer immediately below the Ga x In 1-x As magnetosensitive layer is 100 nm, and the film thickness immediately above the magnetosensitive layer is 35 nm or more and 165 nm or less.
The provision of the nP layer can satisfy the requirements of the present invention. When the film thickness of the compound semiconductor layers provided above and below the magnetosensitive layer exceeds the regulation of the present invention, the amount of strain introduced into the Ga x In 1-x As layer due to the difference in linear expansion coefficient increases remarkably. Ga x In 1-x As
If the compound semiconductor layers provided on both sides of the layer have extremely different film thicknesses, “warp” occurs in the Ga x In 1-x As layer, which is not preferable.

【0013】上記のダブルヘテロ接合の内、InP/G
x In1-x As/InPとAlInAs/Gax In
1-x As/AlInAs接合系は基板としてInPを利
用するのが好ましい。InPは勿論のこと、Gaの組成
比を0.47としたGa0.47In0.53AsやAl組成比
を0.48としたAl0.48In0.52As層はInPと格
子整合するからである。格子整合系とすればヘテロ構成
層の成長が容易となる利点がある。一方、GaInPや
AlInPはGaAsとの格子整合組成を持つため、基
板としてGaAsを利用すると良い。例えば、Gaの組
成比を0.51としたGa0.51In0.49PがGaAsと
格子整合する。
Of the above double heterojunctions, InP / G
a x In 1-x As / InP and AlInAs / Ga x In
The 1-x As / AlInAs junction system preferably utilizes InP as the substrate. This is because not only InP but also Ga 0.47 In 0.53 As having a Ga composition ratio of 0.47 and an Al 0.48 In 0.52 As layer having an Al composition ratio of 0.48 are lattice-matched with InP. The lattice-matched system has an advantage that the hetero-structure layer can be easily grown. On the other hand, since GaInP and AlInP have a lattice matching composition with GaAs, GaAs should be used as the substrate. For example, Ga 0.51 In 0.49 P having a Ga composition ratio of 0.51 lattice-matches with GaAs.

【0014】InPに格子整合する化合物半導体層によ
りダブルヘテロ接合を構成する場合、Gax In1-x
sの混晶比(x)は、0.37≦x≦0.57とするの
が望ましい。何故ならば、InPに格子整合するGax
In1-x Asの組成比(x)=0.47から組成比がず
れるに伴い格子不整合度も顕著となり多量の結晶欠陥等
を誘発し結晶性の低下を招くからである。また、電子移
動度等の電気的特性をも悪化させ、ホール素子の特性
上、積感度の改善に多大な支障を来すからである。
When a double heterojunction is formed by a compound semiconductor layer that lattice-matches InP, Ga x In 1-x A
The mixed crystal ratio (x) of s is preferably 0.37 ≦ x ≦ 0.57. Because Ga x lattice-matched to InP
This is because as the composition ratio of In 1-x As (x) = 0.47 deviates, the degree of lattice mismatch becomes noticeable and a large amount of crystal defects are induced, resulting in deterioration of crystallinity. Also, the electrical characteristics such as electron mobility are deteriorated, and the characteristics of the Hall element greatly hinder the improvement of product sensitivity.

【0015】InPに格子整合する化合物半導体層から
なるダブルヘテロ接合を構成する場合、感磁層とするG
x In1-x As層の膜厚は、GaAsヘテロ接合系の
格子不整合型のGax In1-x Asとは事情が異なり、
特段の制限はない。しかし、10-3cmを越えた厚さと
すると感磁層をメサ型に加工する際に、結晶軸の違いに
よるメサエッチング形状の差異が助長され、不平衡率の
悪化を招き兼ねない。従って、感磁層とするGax In
1-x As層の膜厚は、通常は1〜2×10-4cmとする
のが適当である。
When a double heterojunction composed of a compound semiconductor layer lattice-matched to InP is formed, G is used as a magnetic sensitive layer.
The film thickness of the a x In 1-x As layer is different from that of the lattice mismatched Ga x In 1-x As of GaAs heterojunction system.
There are no special restrictions. However, if the thickness exceeds 10 −3 cm, the difference in the mesa etching shape due to the difference in the crystal axis is promoted when the magnetosensitive layer is processed into the mesa type, and the unbalance ratio may be deteriorated. Therefore, Ga x In used as the magnetic sensitive layer
The film thickness of the 1-x As layer is usually 1 to 2 × 10 -4 cm.

【0016】GaAs基板上に格子整合するGa0.51
0.49P層やAl0.52In0.48P層とGax In1-x
s層とからなるダブルヘテロ接合を構成する場合、Ga
x In1-x AsのGa組成比は0.2前後とするのが好
ましい。Gax In1-x AsはGa組成比(x)の如何
に拘らず、GaAsとは格子整合せず、しかも(x)の
増大に伴い、格子の不整合度は増加する。従って、
(x)を極端に増加させるのは、高い電子移動度を得る
には不利となるからである。
Ga 0.51 I lattice-matched on a GaAs substrate
n 0.49 P layer or Al 0.52 In 0.48 P layer and Ga x In 1-x A
When forming a double heterojunction consisting of an s layer, Ga
The Ga composition ratio of x In 1-x As is preferably about 0.2. Ga x In 1-x As does not lattice match with GaAs regardless of the Ga composition ratio (x), and the degree of lattice mismatch increases as (x) increases. Therefore,
The reason why (x) is extremely increased is that it is disadvantageous to obtain high electron mobility.

【0017】GaAs基板に成長させたダブルヘテロ接
合させる(x)が0.2前後のGax In1-x Asの膜
厚は10nm程度以下とするのが好ましい。膜厚が厚く
なると格子の不整合に伴う歪が層内に内包できなくな
り、電子移動度等の電気的特性の向上等が困難となる。
The film thickness of Ga x In 1 -x As having a double heterojunction (x) of about 0.2 grown on a GaAs substrate is preferably about 10 nm or less. When the film thickness becomes thick, strain due to lattice mismatch cannot be contained in the layer, and it becomes difficult to improve electrical characteristics such as electron mobility.

【0018】感磁層とするGax In1-x As層は一般
的にはn形とする。p形に比較し、高い電子移動度が得
られ、ホール素子の高感度化に優位となるからである。
また、n形のGax In1-x As感磁層の直上にp形の
InP層を設け、感磁層の直下には反対の伝導形である
n形のInPを配置した構造であると、感磁層とp形I
nPヘテロ接合はpn接合となり、静電容量の増加をも
たらし、ホール素子の高速応答性を悪化させる。従っ
て、Gax In1-x As感磁層の上下両側に設ける化合
物半導体層の伝導形は、感磁層と同一のn形とするのが
高い電子移動度を得る観点から望ましい。例えばAlI
nAs/Gax In1-x As/AlInAsダブルヘテ
ロ接合系で、Gax In1-x Asの直下のAlInAs
層がn形であれば、Gax In1-x As層の直上のAl
InAs層もn形とする。
The Ga x In 1-x As layer serving as the magnetic sensitive layer is generally n-type. This is because a higher electron mobility can be obtained as compared with the p-type, which is advantageous in increasing the sensitivity of the Hall element.
In addition, a p-type InP layer is provided directly above the n-type Ga x In 1-x As magnetosensitive layer, and an n-type InP that is the opposite conductivity type is arranged immediately below the magnetosensitive layer. , Magnetic sensitive layer and p-type I
The nP heterojunction becomes a pn junction, which causes an increase in capacitance and deteriorates the high-speed response of the Hall element. Therefore, the conduction type of the compound semiconductor layers provided on the upper and lower sides of the Ga x In 1 -x As magnetic sensitive layer is preferably the same n type as the magnetic sensitive layer from the viewpoint of obtaining high electron mobility. For example AlI
nAs / Ga x In 1-x As / AlInAs double heterojunction system, AlInAs immediately below Ga x In 1-x As
If the layer is n -type , Al immediately above the Ga x In 1-x As layer
The InAs layer is also n-type.

【0019】感磁層とするGax In1-x As層やそれ
とヘテロ接合させるInP、AlInAs、GaInP
やAlInPの各層は液相エピタキシャル成長法(LP
E法)、分子線エピタキシャル成長法(MBE法)や有
機金属熱分解気相成長法、いわゆるMOVPE(MOC
VD法とかOMVPE法とも呼ばれる場合もある。)な
どで成長させることができる。或いはMOVPEとMB
E双方を複合させたMO・MBE法などで成長させるこ
とができる。また、層毎に成長方法を異にしても支障は
無く、本発明に係わるヘテロ接合を唯一の成長法で形成
する各層を設ける必要はない。また、本発明に係わるダ
ブルヘテロ構造からGaInAsヘテロ接合ホール素子
を得るには、公知のプロセス技術を利用すれば製作でき
る。
A Ga x In 1-x As layer serving as a magnetically sensitive layer and InP, AlInAs, and GaInP heterojunction therewith.
And each layer of AlInP are liquid phase epitaxial growth (LP
E method), molecular beam epitaxial growth method (MBE method), metalorganic pyrolysis vapor phase growth method, so-called MOVPE (MOC)
It may also be called the VD method or the OMVPE method. ) And so on. Or MOVPE and MB
It can be grown by the MO / MBE method or the like in which both E are combined. There is no problem even if the growth method is different for each layer, and it is not necessary to provide each layer for forming the heterojunction according to the present invention by the only growth method. Further, in order to obtain a GaInAs heterojunction Hall element from the double heterostructure according to the present invention, it can be manufactured by using a known process technique.

【0020】[0020]

【作用】ダブルヘテロ接合のクラッド層の膜厚を特定す
ることにより、熱プロセス等に伴うGax In1-x As
感磁層の変位を軽減して、熱歪の発生を抑制する。
By specifying the film thickness of the clad layer of the double heterojunction, the Ga x In 1-x As associated with the thermal process etc.
The displacement of the magnetic sensitive layer is reduced, and the generation of thermal strain is suppressed.

【0021】[0021]

【実施例】以下、本発明を実施例を基に具体的に説明す
る。図1は本発明に係わるInP/Ga0.47In0.53
s/InPダブルヘテロ接合ホール素子の平面模式図で
ある。また、図2は図1の破線A−A’に沿う断面模式
図である。当該ヘテロ接合を形成するにあたっては、基
板(101)としてFeを添加した半絶縁性の{10
0}InP単結晶を使用した。InP単結晶基板(10
1)の比抵抗は1×107 Ω・cmであり、厚さは約3
50μmであった。
EXAMPLES The present invention will be specifically described below based on examples. FIG. 1 shows InP / Ga 0.47 In 0.53 A according to the present invention.
It is a plane schematic diagram of an s / InP double heterojunction Hall element. 2 is a schematic cross-sectional view taken along the broken line AA ′ of FIG. In forming the heterojunction, a semi-insulating {10
0} InP single crystal was used. InP single crystal substrate (10
The resistivity of 1) is 1 × 10 7 Ω · cm, and the thickness is about 3
It was 50 μm.

【0022】(102)は基板(101)上にシクロペ
ンタジエニルインジウム(分子式:C55 In)をI
n源とする常圧(大気圧)のMOVPE法で成長させ
た、膜厚が約100nmのアンドープのn形InPエピ
タキシャル結晶からなる緩衝層である。緩衝層(10
2)は温度610℃にて成長させた。キャリア濃度は2
×1015cm-3であった。
(102) is cyclopentadienyl indium (molecular formula: C 5 H 5 In) I formed on the substrate (101).
It is a buffer layer made of undoped n-type InP epitaxial crystal having a film thickness of about 100 nm, which is grown by MOVPE method of atmospheric pressure (atmospheric pressure) using n source. Buffer layer (10
2) was grown at a temperature of 610 ° C. Carrier concentration is 2
It was × 10 15 cm -3 .

【0023】緩衝層(102)上にはGa組成比が0.
47で、約400nmの膜厚のn形Ga0.47In0.53
sの感磁層(103)を上記の常圧MOVPE成長法で
設けた。この感磁層(103)の成長温度もInP緩衝
層(102)と同じく610℃とした。感磁層(10
3)のキャリア濃度は2×1016cm-3であった。感磁
層(103)のキャリア濃度はn形ドーパントの硫黄
(S)の添加量を調節することで得た。
On the buffer layer (102), a Ga composition ratio of 0.
47, n-type Ga 0.47 In 0.53 A with a thickness of about 400 nm
The magnetic sensitive layer (103) of s was provided by the atmospheric pressure MOVPE growth method described above. The growth temperature of this magnetic sensitive layer (103) was also set to 610 ° C., like the InP buffer layer (102). Magnetic layer (10
The carrier concentration of 3) was 2 × 10 16 cm −3 . The carrier concentration of the magnetic sensing layer (103) was obtained by adjusting the amount of sulfur (S) added as an n-type dopant.

【0024】感磁層(103)の上には、緩衝層(10
2)を構成する化合物半導体層と同一のInP層をコン
タクト層(104)として堆積した。このコンタクト層
(104)もn形とした。これにより、InP/GaI
nAs/InPのダブルヘテロ接合を形成した。コンタ
クト層(104)の膜厚は120nmとした。従って、
本文中のtu は120nmで、t1 は100nmとな
り、前記の式(1)で定義される膜厚の差異は20%と
なった。コンタクト層(104)はSiをドーピングし
たn形層で、キャリア濃度は1.2×1018cm-3であ
った。キャリア濃度をこの様に高くしたのは、この層を
オーミックコンタクト層として利用するためである。
A buffer layer (10) is formed on the magnetic sensing layer (103).
The same InP layer as the compound semiconductor layer constituting 2) was deposited as the contact layer (104). This contact layer (104) was also n-type. As a result, InP / GaI
A double heterojunction of nAs / InP was formed. The thickness of the contact layer (104) was 120 nm. Therefore,
In the text, t u was 120 nm, t 1 was 100 nm, and the difference in film thickness defined by the above formula (1) was 20%. The contact layer (104) was an n-type layer doped with Si and had a carrier concentration of 1.2 × 10 18 cm −3 . The reason for increasing the carrier concentration in this way is to utilize this layer as an ohmic contact layer.

【0025】得られたダブルヘテロ接合材料を母体材料
として、公知のフォトリソグラフィー技術を駆使し、電
極(105)、スクライブライン(106)、絶縁膜
(107)等を形成し、GaInAsダブルヘテロ接合
ホール素子を形成した。電極はAuGe合金から構成
し、温度420℃で3分間、アロイングすることによ
り、オーミック電極とした。
A GaInAs double heterojunction hole is formed by using the obtained double heterojunction material as a base material and using well-known photolithography technology to form electrodes (105), scribe lines (106), an insulating film (107), and the like. The device was formed. The electrode was made of AuGe alloy and was alloyed at a temperature of 420 ° C. for 3 minutes to form an ohmic electrode.

【0026】上記のダブルヘテロ接合材料では、110
0Ωの入力抵抗で750V/A・Tの積感度が得られ
た。この積感度の値は電子移動度やシート抵抗等を基に
素子のパターン形状から計算される理論積感度から、平
均して5%低い値となった。不平衡率は±6%であっ
た。一方、GaInAs感磁層の一面が開放された従来
のシングルヘテロ構造から得られる積感度の平均値は6
60V/A・Tと理論積感度値より約16%低かった。
また、不平衡率は±12%であった。従来のシングルヘ
テロ接合構造の電子移動度は、加熱を要する電極のオー
ミックアロイング工程で特に低下した。
In the above double heterojunction material, 110
A product sensitivity of 750 V / A · T was obtained with an input resistance of 0Ω. The value of this product sensitivity was 5% lower on average from the theoretical product sensitivity calculated from the pattern shape of the device based on electron mobility, sheet resistance and the like. The imbalance rate was ± 6%. On the other hand, the average value of product sensitivity obtained from the conventional single hetero structure in which one surface of the GaInAs magnetosensitive layer is opened is 6
The value was 60 V / AT, which was about 16% lower than the theoretical product sensitivity value.
The unbalance rate was ± 12%. The electron mobility of the conventional single heterojunction structure is particularly lowered in the ohmic alloying process of the electrode which requires heating.

【0027】[0027]

【発明の効果】感度並びに不平衡率の熱プロセス等によ
る劣化を抑制できる。
EFFECTS OF THE INVENTION It is possible to suppress the deterioration of sensitivity and unbalance rate due to a thermal process or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わるGaInAsホール素子の平面
模式図である。
FIG. 1 is a schematic plan view of a GaInAs Hall element according to the present invention.

【図2】図1の破線A−A’に沿う断面模式図である。FIG. 2 is a schematic cross-sectional view taken along the broken line A-A ′ in FIG.

【図3】GaInAs/InPヘテロ接合材料を例にし
てワープを説明する図である。
FIG. 3 is a diagram illustrating warping by taking a GaInAs / InP heterojunction material as an example.

【符号の説明】[Explanation of symbols]

(101) 結晶基板 (102) 緩衝層 (103) 感磁層 (104) コンタクト層 (105) 電極 (106) スクライブライン (107) 絶縁膜 (110) 「反り」の最下点 (111) 「反り」の最高点 (112) ワープ量に相当する高低差 (101) Crystal substrate (102) Buffer layer (103) Magnetosensitive layer (104) Contact layer (105) Electrode (106) Scribe line (107) Insulating film (110) Lowest point of "warp" (111) "Warp" Highest point (112) Height difference equivalent to warp amount

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に載置された膜厚の差異が
65%以内である同一の元素から構成される2層の化合
物半導体層の中間に、Gax In1-x As層(ただし、
xは組成比を表し、0<x<1である)を挿入してなる
ダブルヘテロ接合を含むことを特徴とするGaInAs
ヘテロ接合ホール素子。
1. A Ga x In 1-x As layer (provided that a Ga x In 1 -x As layer is provided between two compound semiconductor layers composed of the same element and having a thickness difference of 65% or less mounted on a semiconductor substrate). ,
x represents a composition ratio, and 0 <x <1) is included in the double heterojunction, which is characterized by including GaInAs.
Heterojunction Hall element.
【請求項2】 上記の同一の元素から構成される化合物
半導体層はInP、AlInAs、GaInP若しくは
AlInPである請求項1に記載のGaInAsヘテロ
接合ホール素子。
2. The GaInAs heterojunction Hall element according to claim 1, wherein the compound semiconductor layer composed of the same element is InP, AlInAs, GaInP or AlInP.
JP6235589A 1994-09-29 1994-09-29 Gainas hetero-junction hall device Pending JPH0897484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6235589A JPH0897484A (en) 1994-09-29 1994-09-29 Gainas hetero-junction hall device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6235589A JPH0897484A (en) 1994-09-29 1994-09-29 Gainas hetero-junction hall device

Publications (1)

Publication Number Publication Date
JPH0897484A true JPH0897484A (en) 1996-04-12

Family

ID=16988245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6235589A Pending JPH0897484A (en) 1994-09-29 1994-09-29 Gainas hetero-junction hall device

Country Status (1)

Country Link
JP (1) JPH0897484A (en)

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