JPH089192A - Field discrimination device - Google Patents

Abstract

PURPOSE:To provide a correct field discrimination signal at all times even when odd-numbered fields and even-numbered fields cannot be correctly discriminated due to deterioration in S/N or noise of video signals. CONSTITUTION:A field discrimination signal generating circuit generates a field discrimination signal of a video signal from a composite synchronizing signal. The device is provided with a compensation circuit 20 having latch circuits 21, 22 latching two fields of consecutive field discrimination signals to be generated and compensation field discrimination signal generating circuits 23, 28 to generate a compensation discrimination signal based on the two fields of the latched field discrimination signals, a discrimination circuit 27 discriminating the propriety based on the two fields of the field discrimination signals latched by the latch circuits, and a selection circuit 26 providing an output of the field discrimination signal generated by the field discrimination signal generating circuit or the compensation field discrimination signal from the generating circuits 23, 28 alternately. Then the selection circuit 26 is controlled by an output of the discrimination circuit 27 to provide the compensation field discrimination signal when the field discrimination signal is not correct.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating apparatus for generating a field discriminating signal for discriminating between an odd field and an even field of an interlace type (interlaced scanning type) video signal.

[0002]

2. Description of the Related Art As is well known, the current television system such as the NTSC system employs an interlace system, so that, for example, 525/2 lines are provided in an odd field and an even field of a video signal. There are lines of each.

Then, as shown in FIGS. 3A and 4A, in the odd field, equalizing pulses are inserted before and after the vertical synchronizing signal in a period (3H) three times the horizontal period (H), and in the even field. , The period of the equalizing pulse to be inserted before the vertical synchronizing signal is 3.5H, and the period of the equalizing pulse to be inserted after the vertical synchronizing signal is 2.5H.
By doing so, the states before and after the vertical synchronization signal are made the same in each of the odd field and the even field.

[0004]

By the way, as described above, in the interlace type video signal, in the even field and the odd field, it is 1/2 before and after the vertical blanking period.
Since the presence or absence of the video signal on the line is different, it may be necessary to determine whether the field is an odd field or an even field and perform signal processing according to each field.

Therefore, conventionally, the field discrimination signal is generated from the composite synchronizing signal in the vicinity of the vertical synchronizing signal.

However, when the composite sync signal is not separated due to bad S / N of the signal or the like, the field discrimination signal cannot be generated, and the system utilizing this discrimination signal does not operate properly. There was a problem.

Further, there is a problem that the field discrimination signal cannot be generated even when a signal that does not comply with the television system is input, such as a video game machine.

In view of the above point, an object of the present invention is to discriminate between an odd field and an even field of a video signal, and when they cannot be discriminated, a compensation field discrimination signal is generated using past discrimination information. There is a field discriminating device that can be used.

[0009]

In order to solve the above-mentioned problems, a field discriminating apparatus according to the present invention discriminates an odd field and an even field of an interlace type video signal by associating the reference numerals of the embodiments described later with each other. A field discriminating signal generation circuit 10 for generating a field discriminating signal from the composite sync signal of the video signal,
Discrimination signal holding circuits 21 and 22 for holding two consecutive fields of the field discrimination signal generated by the field discrimination signal generation circuit 10 and field discrimination signals for two fields held by the discrimination signal holding circuit are provided. A compensation field discrimination signal generation circuit 23 for generating a compensation field discrimination signal based on the above, a discrimination circuit 27 for discriminating the correctness of the field discrimination signals for the two fields held by the discrimination signal holding circuit, the field discrimination signal and the above A selection circuit 26 that selectively outputs one of the compensation field discrimination signal is provided, and the selection circuit 26 is controlled by the output of the discrimination circuit 27. When the field discrimination signal is incorrect, the compensation field discrimination signal is output. It is characterized by doing so.

[0010]

According to such a configuration, when the odd field and the even field of the video signal cannot be correctly discriminated, based on the field discrimination signals for the past two fields held by the discrimination signal holding means 21 and 22. Then, the compensation field discrimination signal generated by the compensation field discrimination signal generating means 23 is output.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the field discriminating apparatus according to the present invention will be described below with reference to FIGS.

FIG. 1 shows the overall construction of an embodiment of the present invention, and FIG. 2 shows the construction of the essential parts.

In FIG. 1, 10 is a field discrimination circuit and 20 is a compensation circuit. The compensation circuit 20 will be described later.

In the field discriminating circuit 10, a vertical synchronizing signal (V
D) Separation circuit 11 and horizontal sync signal (HD) separation circuit 12
, The composite synchronizing signal Ssy is input, the vertical synchronizing signal VD from the separating circuit 11 and the horizontal synchronizing signal H from the separating circuit 12.
D is obtained.

Then, the vertical synchronizing signal VD from the separation circuit 11 is supplied to the reset terminal of the counter 13. A clock having a frequency sufficiently higher than the horizontal frequency is supplied to the counter 13 from the clock generation circuit 14, and the output signal of the counter 13 is supplied commonly to the pair of decoders 15 and 16.

In both decoders 15 and 16, H / 2 width, 1
H-width window signals S15 and S16 are formed,
The output signal S15 of one decoder 15 is supplied to the data input terminal of the D flip-flop circuit 17, and the output signal S16 of the other decoder 16 is supplied to the AND gate 18. The horizontal synchronizing signal HD from the separation circuit 12 is supplied to the AND gate 18, the output signal S18 of the AND gate 18 is used as the enable input terminal of the D flip-flop circuit 17, and the control terminal 2 of the compensation circuit 20 is also supplied.
It is supplied to 0s.

The output signal S17 of the D flip-flop circuit 17 is supplied to the input terminal 20i of the compensation circuit 20, and the horizontal synchronizing signal HD from the separation circuit 12 is supplied to the clock terminal 20k of the compensation signal generation circuit 20. It

As shown in FIG. 2, the compensation circuit 20 includes three D flip-flop circuits 21, 22, 23 and three changeover switch circuits 24a, 24b, 24c, and the D flip-flop circuit. The horizontal synchronizing signal HD from the terminal 20k is supplied to 21 to 23 as a clock, and the signal S18 from the terminal 20s is supplied to the switch circuits 24a, 24b and 24c as a switching control signal.

The output terminals and the input terminal u side of the switch circuits 24a, 24b, 24c are connected to the input terminals and output terminals of the first to third D flip-flop circuits 21, 22, 23, respectively. In addition, the input terminal d of the switch circuit 24a
The side is connected to the input terminal 20i, and the input end d side of the switch circuit 24b is connected to the input end u side of the switch circuit 24a.

The output terminal of the second D flip-flop circuit 22 is connected to the input terminal n side of the changeover switch circuit 26, and the first and second D flip-flop circuits 21,
The output of 22 is supplied as a control signal to the changeover switch circuit 26 constituting the selection circuit via the exclusive OR circuit 27.

The output end of the changeover switch circuit 26 is commonly connected to the output terminal 20o and the input end d side of the switch circuit 24c, and the knot circuit 28 is connected to the input end f side of the changeover switch circuit 26. Then, the output of the third D flip-flop circuit 23 is supplied.

Next, the field discrimination signal generation and the compensation field discrimination signal generation according to the embodiment of the present invention will be described with reference to FIGS.

In both separation circuits 11 and 12 of the field discrimination circuit 10 of FIG. 1, from the input composite sync signal as shown in FIGS. 3A and 4A to the vertical sync signal VD as shown in FIGS. 3B and 4B, The horizontal synchronizing signal HD as shown in FIGS. 3C and 4C is separated. Separated vertical sync signal V
The rising of D resets the counter 13, and the counter 13 starts counting clocks at this time ts.

Based on the output of the counter 13 at the time when the predetermined counting is finished, the decoders 16 and 15 respectively show the rising timing of the vertical synchronizing signal VD as shown in FIGS. 3D and E and 4D and E. starting from ts,
Window signals S16 and S15 having a width of 1H and a width of H / 2 are formed.

As shown in FIGS. 3C, D and 4C, D, since the first HD pulse Ps is within the period of the 1H width window signal S16 from the rising time ts of the vertical synchronizing signal VD, FIG. 3F, As shown in FIG. 4F, the HD pulse Ps is extracted from the output signal S18 of the AND gate 18, and this HD pulse Ps is at a high level (hereinafter "Hi").
During the period), the D flip-flop circuit 17 is enabled.

Then, in the odd field, FIG.
As shown in C and E, since the first HD pulse Ps from the rising time ts of the vertical synchronizing signal VD is within the period of the H / 2 width window signal S15, "Hi" of this window signal S15 is D The output signal S of the D flip-flop circuit 17 is taken in by the flip-flop circuit 17.
As shown in FIG. 3G, 17 indicates “H” after the HD pulse Ps.
i ".

In the even field, FIG.
As shown in C and E, since the first HD pulse Ps from the rising time ts of the vertical synchronizing signal VD is not within the period of the H / 2 width window signal S15, the low level of the window signal S15 (hereinafter "Lo") is taken into the D flip-flop circuit 17, and the output signal S17 of the D flip-flop circuit 17 becomes "Lo" after the HD pulse Ps, as shown in FIG. 4G.

As described above, in this embodiment, D is determined according to whether the first HD pulse Ps from the rising time ts of the vertical synchronizing signal VD is within H / 2 from the time ts.
The output signal S17 of the flip-flop circuit 17 becomes "Hi" or "Lo", the current field is an odd field,
It is determined whether the field is an even field. That is,
The output signal S17 of the D flip-flop circuit 17 becomes a field discrimination signal.

In the compensating circuit 20 of FIG. 2, the changeover switch circuits 24a, 24b, 24c are controlled by the signal S18 from the terminal 20s, and are connected to the illustrated state during the period when the signal S18 is "Lo". At the same time, the signal S18 is "Hi".
During the period of, the connection state is switched to that shown in the figure.

When the connection of the switch circuits 24a to 24c is switched in the opposite manner to that shown in the figure, the field discrimination signal S17 from the terminal 20i is fetched into the first D flip-flop circuit 21. At this time, the second D flip-flop circuit 22 takes in the field discrimination signal of one field before, which was held by the first D flip-flop circuit 21 immediately before taking in the field discrimination signal S17. After that, when the signal S18 goes to the "L" state, the switch circuits 24a and 24b go to the illustrated state, and the output states of the D flip-flops 21 and 22 are held.

Thus, the D flip-flop circuit 21 holds the discrimination signal of the current field, and the D flip-flop 22 holds the discrimination signal of the field one field before the current field. Therefore, when the field discrimination is performed correctly, the discrimination output of the odd field (“Hi” in this example) and the discrimination output of the even field (“Lo” in this example) alternately appear every one field. Both D flip-flop circuits 21,
The output of 22 is always different from "Hi" on one side and "Lo" on the other side.

Therefore, when the field discrimination is correctly performed, the output of the exclusive OR circuit 27 becomes "Hi" as shown in FIG. 5D, and the switch circuit 26 is switched to the state opposite to that shown in the figure. The output of the D flip-flop circuit 22 is led to the output terminal 20o as a field discrimination signal.

On the other hand, in the D flip-flop circuit 23,
The output signal of the switch circuit 26 is fetched and held by the horizontal synchronizing signal HD (HD pulse Ps) immediately after the vertical synchronizing signal VD. The output of the D flip-flop circuit 23 is inverted by the knot circuit 28 and supplied to the input terminal f of the switch circuit 26. That is, the output of the knot circuit 28 has a polarity opposite to that of the discrimination output of the current field, and this predicts the discrimination output of the next field.

In FIG. 5, for example, when the discrimination signal generating circuit 10 cannot generate a correct field discrimination signal for some reason such as bad S / N of the input video signal at time tf, As shown by the thin lines in FIGS. 5A and 5C, the D flip-flop circuits 21 and 22 are shown.
Output becomes "Lo", and the output of the exclusive OR circuit 27 becomes "Lo", as shown in FIG. 5D, and the switch circuit 26 enters the illustrated state. Then, the switch circuit 24c and the switch circuit 2
6, D flip-flop circuit 23 and knot circuit 28
To form a closed loop.

In this state, the control signal S18 causes the switch circuit 24c to switch to a state opposite to that shown in the figure for each "H" period, and the D flip-flop circuit 23 inverts every field. Output a discrimination signal. At this time, so to speak, the D flip-flop circuit 23 is in the free-run state.

The D flip-flop circuit 23
Is output to the output terminal 20o via the knot circuit 28 and the switch circuit 26 as a compensation field discrimination signal as indicated by a thick line in FIG. 5E.

As a result, even when the discrimination signal generation circuit 10 cannot generate the field discrimination signal, the compensation field discrimination signal can be output.

When the discriminant signal generating circuit 10 can again generate the correct field discriminating signal, the output of the exclusive OR circuit 27 is "Hi".
Then, the switch circuit 26 is switched to the state opposite to that shown in the drawing, and the normal field discrimination signal is output to the output terminal 20o.
Be derived to.

When the input video signal does not comply with the television system, such as the output video signal of the game machine, the output of the D flip-flop circuit 23 in the free running state is inverted by the knot circuit 28. Figure 5
A compensation signal as shown by E is derived at the output terminal 20o. By this, the field is specified in a pseudo manner,
It can be operated properly as a system.

Although not shown, an OR gate is inserted in the output side of the exclusive OR circuit 27, and the output signal of the circuit 27 is supplied to the switch circuit 26 through one input side of this OR gate, while the other of the OR gates is supplied. It is also possible to turn on / off the automatic switching of the switch circuit 26 by the output signal of the circuit 27 by supplying another switching control signal, for example, a switching control signal according to the operation of the operation key switch, to the input side of it can.

In the above example, the horizontal synchronizing signal HD is used as the clock signal for the D flip-flop circuits 21-23.
However, the horizontal synchronizing signal HD is not particularly required as long as the field discrimination signal can be held. Further, although the above-mentioned example has explained the video signal of the NTSC system, the present invention can be applied to the video signal of the PAL system or the SECAM system.

[0042]

As described above, according to the present invention, when the field discriminating signal is incorrect, the compensation field discriminating signal generated from the past field discriminating signal is output. Even when they are not separated, the system using the field discrimination signal can operate properly.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of an embodiment of a field discrimination device according to the present invention.

FIG. 3 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the embodiment of the present invention.

[Explanation of symbols]

 10 Field Discrimination Circuit 11 Vertical Sync Signal (VD) Separation Circuit 12 Horizontal Sync Signal (HD) Separation Circuit 15, 16 Decoder 17 D Flip-Flop Circuit 20 Compensation Circuit 21-23 D Flip-Flop Circuit 26 Selection Switch Circuit 27 Exclusive OR Circuit

Claims (2)

[Claims] 1. A field discrimination signal generation circuit for generating a field discrimination signal for discriminating an odd field and an even field of an interlaced video signal from a composite synchronizing signal of the video signal, and the field discrimination signal generation circuit. A discrimination signal holding circuit for holding two consecutive field discrimination signals of the field discrimination signal generated by the above, and a compensation field discrimination signal is generated based on the field discrimination signals of the two fields held by the discrimination signal holding circuit. Compensation field discrimination signal generation circuit, discrimination circuit for discriminating whether the field discrimination signals for the two fields held by the discrimination signal holding circuit are correct, or one of the field discrimination signal and the compensation field discrimination signal And a selection circuit for selectively outputting And controls the selection circuit by force, when the field determination signal is not correct field determination device is characterized in that so as to output the compensation field discrimination signal. 2. The compensating field discrimination signal generating circuit is
A holding circuit that holds the output of the selection circuit and a polarity inversion circuit that inverts the polarity of the output signal of the holding circuit are provided, and the output signal of the polarity inversion circuit is supplied to the selection circuit as a compensation field determination signal. The field discriminating device according to claim 1, characterized in that.