JPS6284669A - Field order deciding device for video printer - Google Patents

Abstract

PURPOSE:To obtain a printed picture without blurring and double profiles by deciding a field to be odd or even from the phase relationship between the leading phase of a vertical synchronizing signal and a horizontal synchronizing signal or a signal synchronizing with said horizontal one and outputting a dummy frame signal when the field is decided to be wrong. CONSTITUTION:The output pulse of an AFC circuit part 3 is waveform-shaped by a waveform shaping circuit part 4 at a duty ratio 1:1 into a field deciding pulse at a frequency H, and inputted to a field odd and even deciding part 5 as a pair of pulses whose polarities are in inverse relation. A delay circuit 7 delays an input vertical synchronizing signal by several H or several tens of H, and outputs it to a field order right or wrong deciding part 8. When the field is properly decided to be odd or even, the printed picture without blurring and double profiles can be obtained. If the output of a field order right or wrong deciding output terminal 10 is erroneously outputted, a printed picture similar to a frame picture can be obtained with a dummy frame signal as an input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a video printer that prints a television screen using a television signal as input information, and particularly to a field order determining device suitable for field determination.

[Background of the invention]

Conventional devices, as described in Japanese Patent Application Laid-Open No. 50-67515, perform vertical synchronization with the first or second pulse within the vertical retrace period, which is obtained by a signal triggered by a horizontal pulse signal. It is known to detect odd and even fields by detecting a difference in phase with a signal. However, this method does not take into consideration cases such as when the horizontal synchronizing signal is missing in a weak electric field, when noise is superimposed on the horizontal synchronizing signal, or when the input video signal is discontinuous due to jitter etc. . For this reason, a video printer that prints one frame screen corresponding to one screen on a television screen may not be able to print a screen that is faithful to the original image. This will be explained briefly. Video printers usually use two printers that make up one frame in order to obtain a resolution higher than that of a television screen.
All the signal information of the video part of the field image is A at high speed.
/ Converts to D, stores it in memory, reads it out at low speed, and prints it.

Therefore, if the two fields, that is, the odd and even fields, are incorrectly determined, print images such as f and zl in FIG. 8 will result, which will be drastically different from the correct flag screen of fhl.

Furthermore, if only one of the odd-even fields can be discriminated, a print image in which the signal is missing for each line or a print image in which two screens become one may be obtained.

[Purpose of the invention]

An object of the present invention is to be able to obtain a correct frame signal based on the original signal even when a television signal in a weak electric field is input or when the input video signal is a discontinuous signal including jitter etc. It is an object of the present invention to provide a field order determination device for a video printer that can print without double contours.

[Summary of the invention]

The present invention discriminates between an even field and an odd field of an input signal based on the phase relationship between the rising phase of a vertical synchronizing signal and a horizontal synchronizing signal or a signal synchronized thereto. -1o number H
The correctness or incorrectness of the Shifield order is determined based on the pulses of several H periods of delay. Furthermore, if the above determination is incorrect, a device is added that focuses on one arbitrary field and outputs an interlaced pseudo frame signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the block diagram of FIG. 1 and the timing chart of FIG. 3. 1 is a video signal input terminal, 2 is a synchronization signal separation circuit section, and 6 is A F
C (Automatic Fraq-anct Con
trol) circuit section, 4 is a first waveform shaping circuit section, 6
is a vertical synchronization signal separation circuit section, 1] is a second waveform shaping section,
7 is a delay circuit section, 5 is a field odd-even discrimination section, 8 is a field order correct/incorrect judgment section, 9 is a field discrimination output terminal, l
O is an output terminal for determining whether the field order is correct or incorrect. A video signal input from an input terminal 1 is separated by a synchronization signal separation circuit section 2 into which only a composite synchronization signal is output. The AFC circuit unit 3 at the next stage outputs a synchronization H pulse (FIG. 3) synchronized with the horizontal synchronization signal included in the composite synchronization signal (H is the period of the horizontal synchronization signal). The output pulse of this AFC circuit section 3 is waveform-shaped by a waveform shaping circuit section 4 into a field discrimination pulse (FIG. 3, 21) with a duty ratio of 1:1 and a period of H.
The pulses are input to the field odd/even discriminator 5 as a pair of pulses with opposite polarities (FIG. 3, 22). The output of the synchronization signal separation circuit section 2 is further input to the vertical synchronization signal separation circuit section 6, where the vertical synchronization signal portion is extracted from the composite synchronization signal and output to the second waveform shaping circuit section 1] and the delay circuit 7. be done. In the second waveform shaping circuit section 1, a VD pulse (
FIG. 6 23) is generated. This VD pulse is output to the field odd/even discriminator 5.

In the delay circuit 7, the input vertical synchronization signal is
The data is output to the field order correct/incorrect determining unit 8 with a certain delay.

A specific example of the field odd/even discriminator 5 is shown in FIG. 2, and its operation will be explained using the timing chart of FIG. 21 and 22 are the input terminals of the output of the first waveform shaping circuit shown in FIG. It is a NAND gate, and two gates 26 and 27 constitute an S-R type switch. The output terminal 4 is an output terminal for even field determination output, and the output terminal 29 is an output terminal for odd field determination output. 5 and 9 are blocks with the same numbers as in FIG.

As shown in the timing chart of Figure 3, each output of the two-man NAND gates 24 and 25 becomes 1 when a normal signal is input.
One pulse with negative polarity is output every vertical period (hereinafter abbreviated as 1V). This means that the period of the vertical synchronization signal is NTSC.
This is because in the case of the method, I V = 262.5H.

Because of this fraction of 0.5H, the rising phase of the vertical synchronization signal repeats matching and mismatching with the "H level period of the horizontal synchronization signal every 1r. Paying attention to this point, determine whether the field is even or odd. The VD pulse (FIG. 6, 23) obtained by waveform-shaping the vertical synchronizing signal output to the field odd-even discriminating section 5 by the waveform shaping section 1 is the vertical synchronizing signal included in the composite synchronizing signal output from the synchronizing signal separation circuit section 2. The rising height is about 4
It is necessary to design so that the margin for discrimination is maximized by delaying 8μ5. The outputs of the two-manpower NAND gates U and 25 are input to the S-R type switch consisting of two-manpower NAND gates 26 and 27. Therefore, the output terminal 9 outputs a signal that is High during even fields and Low during odd fields. The reason why the fi pulse output from the AFC section is used instead of directly creating the fi (fH: horizontal synchronizing signal frequency) pulse for field even-odd determination from the horizontal synchronizing signal is as follows.

(If llTJ' broadcast is received in a weak electric field, extra pulses or missing pulses will occur from the synchronization signal separation circuit, making it impossible to generate stable ht pulses for field discrimination.

('2) In many cases, the horizontal synchronization signal is missing from the input signal itself, such as when variable speed playback or tracking is off in VTR playback images, and as in 1, the fH pulse for field discrimination cannot be generated correctly.

(3) Similarly, if there are extra pulses, omissions, jitter, etc. in other possible input sources, +1
1 and +21, a stable and correct fir pulse for field discrimination may not be generated.

For such bad image #, if the AFC loop is configured and the loop time constant is slowed down, a nearly stable 1g pulse can be output even in response to an incorrect input horizontal synchronization signal, and the fly pulse for field discrimination can be output. can be supplied to the stable Nifield odd-even discriminator 5.

Next, an embodiment of the field order correct/incorrect determining section 8 will be described with reference to FIG. 4 and a timing chart of one operation shown in FIG. 3. 3
1 input terminal is the output terminal of the second delay circuit 7, 290 input terminal is the same as in FIG. 2, 34 to 36 are inverters, 37
, 39, 45 are D-type F, F.

(Flip-flop is abbreviated as F, F) 38 is 2-man power N
OR gate, 40-43 are two-man NAND gate.

40 and 41, 42 and 43 constitute the S and R type switches. 44 is a three-person NAND. The field order correct/incorrect determining section 8 performs determination using the following two functions.

m Does an even field pulse occur between odd field pulses?

(2) Odd field pulses and even field pulses are generated alternately in each field.

When this condition is met, a low level is output from the output terminal 10.

Inverter 34, 35, F, F・37 and 2N
A judgment section of one frame is set by OR3s. 2 person power N
The S and R latches consisting of AND gates 40 and 41 become High when an odd field pulse (FIG. 3, 29) is input. Similarly, the S and R latches consisting of 42 and 43 are even field pulses (Figure 3, 28)
When input, HSUAK becomes. D, F, F 39 uses the output of the gate 40 as the D input, and the signal from the input terminal 31 as the CK
When there is a large input and the function fl) above is satisfied, Hsh is output from the i output. The function (2) above can be confirmed when the outputs of the gates 40 and 42 (2A', 4Nl) become Highk. Since the functions of fil and (2) must be satisfied at the same time, the period for performing logical operations using the three-man NAND gate 44 and determining whether the CK input of the D-F-F 45 is correct is determined by the two-man NAND gate 44.
The output of the OR gate 38 is used again to obtain a low output when it is positive, and a high output when it is false (FIG. 3, 1O). FIG. 3 is an example showing timing during correct operation.

When an erroneous judgment signal is output, for example, if the output terminal 28 indicating even field output continues to be at H level, the output of the gate 42 remains at Low level, and the gate 44 and the output terminal 1o are at H level. This results in an erroneous judgment signal being output.

As explained above, when the odd-even field is correctly determined, it becomes possible to print a correct and beautiful frame image.
You can get prints without pre-prints or double outlines.

However, if the output 1o of the field order correctness determination unit is incorrect, that is, Mi
When outputting gh, it is possible to use a pseudo frame signal as an input signal using the circuit of the embodiment shown in FIG. This allows you to obtain prints that are as good as frame images. In FIG. 6, 51 is a switching signal input terminal for creating a pseudo frame, and 52 is a 1H delay line (hereinafter referred to as DL).
), 53 is the first HDL, 54 is the adder, and 55 is the first HDL.
The signal switching SF, 56, is a second signal switching SF. The pseudo frame signal generating circuit shown in FIG. 6 is for an MSN video signal of a personal computer in which the input source is only field fraction information and the same fields are continuous. Explain the operation. The field information video signal from the input terminal 1 is determined to be incorrect by the field order correct/incorrect judgment output, and the second SF 56 is switched to the b side. On the other hand, adder I adds together what passed through 1HD L 52 and what did not pass through,
The averaged output is sent to the contact α of the first 5F55, T
The output that has passed through the HDL 53 is connected to contact bK, and is switched and output by a switching signal from the input terminal 51. first science fiction
Then, by switching the terminals, α, b Fukuko inter-quantum code FC
A TH delay difference occurs, which can cause a TH offset between fields. That is, at the leading edge of the point at the end of one field, the first 5W55 is switched from α to AK and 1r
By setting the period to 262.5H, information can be stored in the memory as a frame signal, and a high-quality frame image can be printed during printing.

Another method is to focus on one field and store the information in the memory when the field order correct/incorrect judgment unit output lO is incorrect, and when printing receives the correct/incorrect judgment output erroneous output, as shown in Fig. 7. A pseudo frame image can be printed by interpolating the memory output and arranging the true information and interpolated information alternately as shown in the example shown in FIG. In this signal interpolation, in a video printing method where the printing direction is horizontal, the interpolation data becomes information on adjacent positions, so signal processing is also simple. Furthermore, in a video printer system in which the print direction is vertical, similar pixel interpolation is possible by using several horizontal line memories, and a pseudo frame image can be printed.

〔Effect of the invention〕

As explained above, since the present invention is applied to a video printer, the line arrangement of odd-even fields can be maintained even when the horizontal synchronization signal is missing, discontinuous video signals containing jitter, etc., or video signals with superimposed noise. Information equivalent to one frame required for a proper video printer can be obtained, making it possible to print images that are faithful to the original.

Furthermore, even when there is an error in the field order, the false frame signal generation circuit operates due to the erroneous determination output from the field order correctness determination circuit, and a print image close to the original image can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of an example of a field odd/even discriminator, Fig. 3 is a timing chart of the circuit shown in Fig. 2, and Fig. 4 is a correct or incorrect field order. Judgment unit circuit diagram, Figure 3 is a timing chart of the circuit in Figure 41, Figure 6 is a circuit diagram of a pseudo frame creation circuit, and Figure 7 is frame information created by interpolating pseudo frame information based on field information. FIG. 8 is an explanatory diagram illustrating the printing state of the conventional example. 1...Video signal input terminal 6...Vertical synchronization signal separation circuit section 8...Field order correct/incorrect judgment section 5...Field odd/even judgment section 4 Figure 5 Figure ILJ □ Figure 6, ]O 8 Figure

Claims (1)

[Claims] 1. A horizontal synchronization signal from a composite synchronization signal or a signal synchronized with the horizontal synchronization signal has a pulse width duty of approximately 50% and a polarity in the horizontal synchronization signal period (hereinafter referred to as "H"). a first means for obtaining a pair of opposite pulses; and a second means for obtaining a signal based on a vertical synchronization signal from the composite synchronization signal.
and a logical operation NAND output or AN output of a pair of two outputs of the first means and an output of the second means.
1. A field order determining device for a video printer, comprising a determining means for determining even and odd fields in the composite synchronizing signal based on the D output. 2. A signal based on the vertical synchronization signal obtained from the first means and the second means, the logical operation NAND or AND circuit, and the second means according to claim 1, and the number H The pulse width is several tens of microseconds with a delay of several tens of hours or more.
field order correctness/incorrect determination means for determining whether the field order of the input composite synchronization signal is correct or incorrect based on the output of the logical operation and the output of the third means; Claim 1, characterized in that it has a pseudo frame signal creating means for creating pseudo frame information from arbitrary one field information when
A field order determining device for a video printer as described in Section 1.