JPS63148780A - Interlace control circuit for television receiver - Google Patents

Abstract

PURPOSE:To normalize an interlace relation by a simple constitution, by quickening a display of a small screen in a second field of a large screen by one horizontal scanning portion, when fields of the large screen and the small screen do not coincide. CONSTITUTION:When fields of a large screen and a small screen do not coincide, in the second field being next to the large screen, a display line counter 5 is cleared by a vertical synchronizing signal MV from a large screen use synchronizing separator circuit 3. Accordingly, from a horizontal synchronizing signal MH from the circuit 3, a horizontal synchronizing signal of the second field is counted. Also, in the next first field, it is cleared by a delay signal MV1, therefore, from the horizontal synchronizing signal MH, a horizontal synchronizing signal of a first field is counted. That is to say, a display of the small screen in the second field of the large screen is quickened by one horizontal scanning portion. In such a way, it is unnecessary to discriminate the field of the large screen and a normal interlace relation can be held by a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an interlace control circuit in a picture-in-picture TV receiver.

<Prior art> In a picture-in-picture RV receiver that simultaneously displays a small monitor image (small screen) within a mark image (large screen), there is a phase difference between the video signal for the large screen and that for the small screen. Due to the fact that there is a small screen image signal, it is common practice to temporarily store the video signal for a small screen in a field memory. Picture-in-picture TV like this
In a television receiver, if the fields of the large-screen video signal and the small-screen video signal are not matched, the interlace relationship will be reversed, resulting in a significant loss of image quality.

For this reason, in the past, the fields of the large-screen and small-screen video signals were determined to match the fields of both video signals. Devices that perform discrimination have drawbacks such as a complicated configuration.

<Objective of the Invention> The present invention has been made in view of the above-mentioned points, and an object of the present invention is to maintain a normal interlace relationship with a relatively simple configuration.

<Configuration of the Invention> In order to achieve the above-mentioned object, the present invention provides a small screen synchronization separation circuit that separates a vertical synchronization signal and a horizontal synchronization signal from a small screen video signal written in a field memory, and a small screen Based on both the synchronization signals from the synchronization separation circuit and the display start signal corresponding to the timing to start displaying the small screen, the field of the small screen video signal to be written is determined in the field memory, and the corresponding gate is set. A small screen field discrimination means that outputs a signal, a large screen sync separation circuit that separates a vertical sync signal and a horizontal sync signal from a large screen video signal, and a vertical sync signal from this large screen sync separation circuit. and an output circuit that outputs a delayed signal delayed by a predetermined time from the vertical synchronization signal, a display line counter that counts the horizontal synchronization signal from the large screen synchronization separation circuit, and based on the gate signal, and a gate circuit that outputs the vertical synchronization signal from the large screen sync separation circuit or the delayed signal as a clear signal for clearing the display line counter, and when the fields of the large screen and the small screen do not match,
Based on the count value of the display line counter, the display of the small screen in the second field of the large screen is advanced by one horizontal scan.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings. The interlace control circuit for a television receiver of this embodiment is applicable to a picture-in-picture TV receiver that displays a small screen B of 1/9 the size on a large screen as shown in FIG. It is equipped.

FIG. 2 is a signal waveform diagram for explaining the writing line of the small screen video signal to the field memory in this Picture/Jinha Picture TV receiver. Figure (B) shows the first field (
(C) is the horizontal synchronization signal of the second field (b field); al
, a2 , a3 .-; bl , b2 .

b3 . . . indicates lines respectively written to the field memory. As shown in this Figure 2,
From the vertical synchronization signal, select a video signal from 1611 or later video signals for small screens at a ratio of one for every three lines, and perform A/D.
Convert and write to field memory sequentially. This written field memory data is synchronized with the scanning of the large screen and the small screen is scanned to a predetermined value of 1! The signal is read out and D/A converted so as to be displayed in the x position, and then switched to a video signal for a large screen and displayed.

At this time, in order to compress the small screen line to 1/3 of its original length, the read cycle is three times faster than the write cycle, and the field memory is It is designed so that it can be written and read at the same time so that it can be written while being displayed. This configuration is similar to a conventional picture-in-picture TV receiver. In the following explanation of this embodiment, if the read address of the field memory overtakes the write address in the middle of displaying a small screen,
Normality shall be restored immediately by adjusting the write line.

FIG. 3 is a block diagram of the interlace control circuit for a television receiver according to this embodiment, and FIG. 4 is a time chart for explaining the operation.

The interlace control circuit of this embodiment outputs a vertical synchronization signal S from a small screen video signal written in a field memory.
A small screen sync separation circuit 1 that separates V and horizontal sync signal S small screen field determination means 2 for determining the field of the small screen video signal written in the field memory based on the corresponding display start signal and outputting a corresponding gate signal; and vertical synchronization from the large screen video signal. A large screen sync separation circuit 3 that separates the signal MV and the horizontal sync signal MH, and a vertical sync signal MV from the large screen sync separation circuit 3, which is delayed by a predetermined period of time from the vertical sync signal MV. A D flip-flop 4 as an output circuit that outputs the delayed signal MVI, a display line counter 5 that counts the horizontal synchronization signal M H from the large double-sided synchronization separation circuit 3, and a gate from the small screen field discrimination means 2. Based on the signal, the vertical synchronization signal MV from the large screen synchronization separation circuit 3 or the delay signal M
A gate circuit 6 is provided for outputting VI as a clear signal for clearing the display line counter 5.

The small screen sync separation circuit 1 receives a video signal for the 1 screen which is written into a field memory (not shown), and from this video signal a vertical sync signal S shown in FIG. 4(A) is generated.
The horizontal synchronizing signal S H shown in FIG. FIG. 4 (t3) shows the horizontal synchronizing signal S H when the video signal for the small screen is the first field (a field).
FIG. 4(C) shows the horizontal synchronizing signal S I when the video signal for small screen is the second field (b field).
−[ are shown respectively.

The vertical synchronization signal SV from the small screen sync separation circuit l is transmitted to the first monomultivibrator 7, ! of the small screen field discrimination means 2. Clear input terminal of hexadecimal counter 8 and second
D flip-flop 9 is applied to each input terminal. The horizontal synchronizing signal S H from the small screen sync separation circuit 1 is applied to the second mono multivibrator 10 of the small screen field discriminating means 2 . The first mono-multivibrator 7 outputs a pulse having the width shown in FIG. 4(F) in synchronization with the rise of the vertical synchronization signal Sv,
The clock signal is applied to the clock input terminal of the first D flip-flop 12 via the inverter 11. The second mono multivibrator IO generates pulses as shown in FIG. 4(D) or FIG. 4(E) based on the horizontal synchronizing signal S H shown in FIG. 4(B) or FIG. 4(C). is output from the clock input terminal of the hexadecimal counter 8 and the first D flip-flop I.
2 to the D input terminals.

In the first D flip-flop I2, at the falling timing of the output pulse of the first monomulti-by-break 7 shown in FIG. 4(F'),
) is taken in from the output of the second mono multivibrator 10 shown in FIG.
The signal for field discrimination shown in FIG.
It is applied to AND gate 14. The field discrimination signal output from the first D flip-flop 12 is as shown in FIG. 4(G) when the small screen video signal changes from the second field (b field) to the first field (a field). On the other hand, when the small screen video signal changes from the first field (a field) to the second field (b field), the low level changes as shown in Figure 4 (H). It becomes a high level.

The clock input terminal of the hexadecimal counter 8 is connected to the clock input terminal shown in FIG.
) or the output pulses of the second monomultivibrator 10 shown in FIG. 4(E) are applied and counted. In this FIG. 4, the hexadecimal counter 8 has a
) is shown for the case where the output is not given. Qa, Qb, Qc, Qd of hexadecimal counter 8
The respective outputs become as shown in FIGS. 4(1) to 4(L) in synchronization with the rise of the output pulse of the second mono-multivibrator IO shown in FIG. 4(D). Each output of Qa, Qb, Qc, and Qd of this hexadecimal counter 8 is given to a first AND gate 15,
The AND gate 15 outputs a signal corresponding to the horizontal synchronization signal of the 15th day, as shown in FIG. 4(M).
The clear input terminal of the second D flip-flop 9 and the third
The clock input terminals of the D flip-flop 13 are respectively provided.

In this 3D flip-flop 13, the first AND gate! shown in FIG. The 1st D flip is 70 times at the rising edge of the 5th output pulse! The signal for field discrimination from 2 is taken in, and the signal for field discrimination shown in FIG. 4 (It) or FIG. 4 (S) is applied from the Q output terminal to the fifth AND gate 16. The field determination signal from the 3D flip-flop 13 is also low level when the field of the small screen video signal written to the field memory is the first field (a field), and is low level when the field is the second field (b field).
When it is, it is at a high level.

The Qc and Qd outputs of the hexadecimal counter 8 are given to the second AND gate 17, and from this F2AND gate 17,
The signal shown in FIG. 4(0) is output and applied to the third AND gate I8. The second D flip-flop 9 outputs a high signal from the rising edge of the vertical synchronizing signal sv to the rising edge of the output pulse of the first AND gate 15.
The signal shown in FIG. 4 (N) that maintains the level is output and applied to the 3rd AN1) gate 18.
The D gate 18 outputs the signal shown in FIG.
)available. The clock input terminal of this fourth D flip-flop 19 is connected to a second monomulti-by-break! 0 is given, and this fourth D flip-flop! 9
The signal shown in FIG.

A display start signal given from a display control circuit (not shown) rises at the timing of the start of the horizontal scanning line of the large screen that starts displaying the small screen, and this display start signal is applied to the fifth D.
It is applied to the clock input terminal of flip-flop 20 and delay circuit 21.

The Q output of the fifth D flip-flop 20 is applied to the fourth AND gate 14, and the Q output is applied to the fifth AND gate 16.
given to. 4th. The fifth AND gates 14 and 16 include the first. Field discrimination signals from the 3D flip-flops 12 and 13 are provided, respectively. 4th.
The output of the fifth AND gate 14.16 is the output of the OR gate 22.
The output of this OR gate 22 is applied to the D input terminal of the sixth D flip-flop 23.

Since the rise of the display start signal and the small screen video signal are not synchronized, the field discrimination signal from the first D flip-flop 12 or the field discrimination signal from the third D flip-flop 13 is switched between high level and low level. The display start signal may rise at the wrong point, and in this case, there is a possibility that the data acquisition of the sixth D flip-flop 23 may become uncertain. Therefore, in this embodiment, the field determination signal from the third D flip-flop 13 is normally transferred to the sixth D flip-flop 23.
However, what role does the high level/low level switching point of the field discrimination signal of the 3rd D flip-flop 13 play?
Two field discrimination signals are applied to the (2) input terminal of the sixth D flip-flop 23.

That is, when the display start signal rises while the output of the 4th D flip-flop 19 is at a low level, the Q output of the 5th D flip-flop 20 becomes a low level, the Q output becomes a high level, and the output from the 31st flip-flop 70 block 13 becomes low. The signals for field discrimination are sent to gates 14, 16, and 22.
(selected in the sixth circle) is applied to the flip 70 knob 23.

On the other hand, when the display start signal rises while the output of the 41st flip-flop 19 is at a high level, the field determination signal from the 11th flip-flop 12 is selected and applied to the 6th D flip-flop 23.

A display start signal delayed by about 100 ns from the delay circuit 21 is applied to the clock input terminal of the sixth D flip-flop 23, and at the timing when this delayed display start signal is applied, the output of the oR gate 22 is taken in.
A gate signal corresponding to the field of the small screen video signal to be written into the field memory is output from the Q and ζ outputs.

That is, at the start of display, when the field of the small screen video signal written to the field memory is the first field (a field), the Q output of the 6th D flip-flop 23 becomes low level, the Q output becomes high level, and , in the second field (b field), the Q output of the sixth D flip-flop 23 becomes high level and the Q output becomes low level.

In this way, the small screen field determining means 2 outputs to the gate circuit 6 a gate signal corresponding to the field of the small screen video signal written into the field memory at the start of display.

The large screen sync separation circuit 3 converts the large screen video signal into a composite sync signal in FIG. 5(A), a vertical sync signal MV in FIG. 5(B), and a horizontal sync signal in FIGS. Synchronous signal M
Separate and output H. FIG. 5(D) shows a horizontal synchronizing signal when the large screen video signal is the first field (a field), and FIG. 5(E) shows the horizontal synchronizing signal when the large screen video signal is the second field (b field). This is the horizontal synchronization signal when the field is

The horizontal synchronization signal MII from the large screen synchronization separation circuit 3 is
It is applied to the clock input terminal of the display line counter 5 and counted. A vertical synchronization signal MV is applied to the D input terminal of the D flip-flop 4 serving as an output circuit, and a composite synchronization signal 4 is applied to the clock input terminal. As shown in FIG. 5(C), the D flip-flop 4 outputs a signal that corresponds to the vertical synchronizing signal MV and is delayed by a predetermined time (0,511 or more and less than I0) from the vertical synchronizing signal MV. A delayed signal MVI is output.

The vertical synchronizing signal MV shown in FIG. 5 (I3) from the large screen synchronization separation circuit 3 and the fifth
The delay signal MVI shown in FIG.
1st. applied to a second AND gate 24.25. The Q output and Q output of the sixth D flip-flop 23 of the small screen field discriminating means 2 are applied to each of these AND gates 24 and 25 as gate signals, respectively.

1st. The output of the second AND gate 24.25 is applied to an OR gate 26, and the output of this OR gate 26 is applied to the clear input terminal of the display line counter 5 as a clear signal for clearing the display line counter 5.

The display line counter 5 counts the horizontal synchronization signal M H from the large screen synchronization separation circuit 3, and this counted value is given to a display control circuit (not shown), for example, from the 150th line to the 230th line. The vertical display position of the small screen is determined. This display line counter 5 is cleared by the vertical synchronization signal MV or delay signal MVI from the gate circuit 6.

Here, when the display line counter 5 is cleared with the vertical synchronizing signal MV shown in FIG. 5 (, r3), in the I field (a field), the count is started from the horizontal synchronizing signal Ah shown in FIG. 5 (D). Therefore, in the second field (b field), the horizontal synchronizing signal Bhl shown in FIG. 5(E) is counted. On the other hand, the display line counter 5
When cleared by the delay signal MVI shown in FIG. 5(C), in the first field (a field), FIG. 5(D
), and in the second field (b field), it is counted from the horizontal synchronous signal "7 A h" in Fig. 5 (E
) is counted from the horizontal synchronization signal nh2. That is, when clearing the display line counter 5 with the vertical synchronization signal shown in FIG. 5(n), it is easier to start counting in the second field (b field) than when clearing with the delayed signal shown in FIG. 5(C). IH will be faster.

Therefore, in this case, the line at which the display of the small screen starts will also be ILI earlier and shifted upward.

Next, the operation of the interlace control circuit for a television receiver having the above configuration will be explained.

At the start of displaying a small screen, if the field of the small screen video signal written in the field memory is, for example, the second field (b field), the 6D flip-flop of the small screen field discriminating means 2 23
The Q output of becomes high level, and the Q output becomes low level. Therefore, the display line counter 5 is cleared by the vertical synchronization signal MV from the gate circuit 6.

When the field of the large screen that displays the video signal for the small screen in the second field is the second field, that is, when the fields of the large screen and the small screen match, the next small screen of the first field The field of the large screen that displays the screen is also the first field, therefore, it is cleared by the vertical synchronization signal MV, and from the horizontal synchronization signal Ah in FIG. 5(D), the horizontal synchronization of the first field is performed by the display line counter 5. Signals are counted. Furthermore, in this first field, the sixth D of the small screen field discriminating means 2
The Q output of the flip-flop 23 becomes low level, the b output becomes high level, and the delay signal MVI is output from the gate circuit 6.
is output and the display line counter 5 is cleared. Therefore, in the next second field, since it is cleared by the delayed signal MVI, the horizontal synchronizing signal Bh2 in FIG. 5(E)
The horizontal synchronization signals of the second field are counted from . When the fields of the large screen and the small screen match in this way, the first field (a field) is 0.51 times faster than the second field (b field), and a normal interlace relationship is maintained. The video signal for the small screen is displayed in the second field of Uko, while the large screen field is displayed in the first field.
field, that is, when the fields of the large screen and the small screen do not match, the display line counter 5 is cleared by the vertical synchronizing signal MV in the second field, which is the next field after the large screen. , 5th
The horizontal synchronizing signal of the second field is counted from the horizontal synchronizing signal Bh1 of FIG.
In the field, it is cleared by the delayed signal MVI, so
The horizontal synchronizing signal of the first field is counted from the horizontal synchronizing signal Ah in FIG. 5(D). That is, when the fields on the large screen and the small screen do not match, the second field on the large screen is counted from Bht at an early time, and therefore the display on the small screen also becomes IH early. The interlace relationship will be maintained.

For example, as shown in FIG. 6(A), because the fields of the large screen and the small screen do not match, the first field (a field) and the second field (b field) of the small screen are If it is reversed, in the present invention, the display on the small screen is advanced by 11-1 in the second field on the large screen, so that the normal interlace relationship can be maintained as shown in FIG. 6(B). It will be.

Even if the field of the video signal for the small screen written in the field memory is the first field at the start of display of the small screen, the normal interlacing relationship is established in the same manner as described for the second field above. is maintained.

In this way, by determining the field of the small screen video signal written to the field memory without determining the field for the large screen, it is possible to maintain a normal interlace relationship. The configuration is simplified compared to the conventional example in which fields are determined.

<Effects of the Invention> As described above, according to the present invention, when the fields of the large screen and the small screen do not match, the display of the small screen in the second field of the large screen is made lIf faster to maintain a normal interlace relationship. will be maintained.

However, in the present invention, since there is no need to discriminate between fields on a large screen, the configuration can be simplified compared to the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a display screen according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the old line to the field memory, and FIG. 3 is a block diagram of an embodiment of the present invention. 4 and 5 are time charts for explaining the operation, and FIG. 6 is a diagram for explaining the interlacing relationship of the small screen. ! . . . Sync separation circuit for small screens, 2. Field determination means for small screens, 3. Sync separation circuit for large screens, 4.
...D flip-flop (output circuit), 5...display line counter, 6...gate circuit.

Claims (1)

[Claims] (1) A small screen sync separation circuit that separates a vertical sync signal and a horizontal sync signal from a small screen video signal written to the field memory, and a display of both of the sync signals and the small screen from this small screen sync separation circuit. small screen field determining means for determining a field of a small screen video signal to be written into the field memory and outputting a corresponding gate signal based on a display start signal corresponding to a timing for starting a large screen video signal; A large-screen sync separation circuit that separates a vertical sync signal and a horizontal sync signal from a signal, and a delayed signal that corresponds to the vertical sync signal from the large-screen sync separation circuit and is delayed by a predetermined time from the vertical sync signal. a display line counter that counts the horizontal synchronization signal from the large screen sync separation circuit, and a display line counter that counts the horizontal sync signal from the large screen sync separation circuit or the delayed signal based on the gate signal. and a gate circuit that outputs as a clear signal to clear the display line counter, and when the fields of the large screen and the small screen do not match, the second field of the large screen is output based on the counted value of the display line counter. An interlace control circuit for a television receiver, characterized in that the display of a small screen in a television receiver is accelerated by one horizontal scan.