JPH0681277B2 - Video special effect device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video special effect device for giving a special video effect to video equipment such as a television and a VTR.

2. Description of the Related Art A conventional video special effect device will be described below. 7th
FIG. 1 is a block diagram showing the configuration of a conventional video special effect device for performing special effects such as two-screen combination. The first video signal input from the input terminal 27 is input to the A / D converter 25 and the first sync signal separator 23, and the signal of the A / D converter 25 is written in the field memory (hereinafter referred to as memory) 21. Be done. The second video signal input from the input terminal 28 is input to the second sync signal separator 24 and the switch 30 and serves as a reference for the timing of reading data from the memory 21. First sync signal separator
The horizontal and vertical sync signals separated by 23 and the second sync signal separator 24 are input to the timing signal generator 22. The timing signal generator 22 generates a write timing signal synchronized with the first video signal, a read timing signal synchronized with the second video signal, and a switching signal for switching between the memory data and the second video signal. D
It is supplied to the converter 25, the D / A converter 26, and the switch 30.
As a result, the first video signal from the input terminal 27 is the A / D converter 2
5, A / D converted and written to the memory 21, the data of the memory 21 is read out in synchronization with the second video signal from the input terminal 28, A / D converted by the A / D converter 26, and switched. It is switched to the second video signal at 30 and two screens are combined and output.

However, in the above-described conventional configuration, since the memory 21 is a field memory, only data within a certain range of one field of the first video signal is read from the memory, as in the case of two-screen composition. When the second video signal is used as it is, the other part is written in the odd field data of the first video signal, but the second video signal is the even field If the signal is read as an even field or vice versa, the even field of the read signal is
(H: horizontal scanning period) As it becomes faster and the even field lines that should originally be below the odd field lines are above, the image as shown in FIG. 8 (a) is as shown in (b). The entire screen becomes unsightly.

Further description will be given below with reference to FIGS. 9 and 10. FIG. 9 is a view showing, in 1H units, a case where two screens are combined and the first 49 lines of the field use the second video signal, and the lines from the 50th line are replaced with the read data of the memory. The odd field signal to be written is A1, and the even field signal is B1, which is shown from the portion of the vertical synchronizing signal (first 3H). The squares under the signal represent the data written in the memory. The numbers 1, 2, 3, ... And <1>, <2>, <3>, ... Show line numbers. A1
The data of B is read at the timing of the odd field A2, the data of B1 is read at the timing of the even field B2, and the signals obtained by the two-screen synthesis are represented as A1A2 and B1B2, respectively. (1), (2), (3), ... And {1},
{2}, {3}, ... are line numbers of A2 and B2, respectively, and the horizontal direction address in the timing signal generator 22 is based on the timing of the vertical address reset signal (indicated by an arrow at the head of the vertical synchronizing signal) It is counted each time the reset signal comes. Focusing on the timing of the data on and after the 50th line, in this case <50> is between 50 and 51,
<51> is between 51 and 52, and the vertical relationship between the lines of the two fields is correct.

However, as shown in FIG. 10, A1 is read at the timing of the even field B2 and B1 is read at the timing of the odd field A2, and in the case of the signals A1B2 and B1A2 obtained by combining two screens, <50> and <51> , <52>, ... is relatively faster by 1H.

If the memory 21 is a frame memory and the odd field is written as described above and is read in synchronization with the even field, the problem can be solved by reading the even field, but the field memory There is a problem that the memory capacity is required to be twice as large as that of the conventional one.

The present invention solves the above-mentioned conventional problems, and provides a read signal in which the vertical relationship of the even field and odd field lines is always maintained correctly regardless of the field states of the first video signal and the second video signal. It is an object of the present invention to provide a video special effect device that can be used.

In order to achieve this object, a video special effect device of the present invention is a first video signal separation device for separating horizontal and vertical sync signals of a first video signal.
A sync signal separator, a second sync signal separator for separating horizontal and vertical sync signals of a second video signal, and A / D conversion of the first video signal to synchronize with an output of the first sync signal separator. Field memory for writing and reading in synchronization with the output of the second sync signal separator, a timing generator for controlling reading and writing of data from and to the memory, a field of the first video signal and the second video signal. First and second field discriminators for discriminating between odd and even fields of a video signal, a coincidence detector for detecting coincidence between the outputs of the first and second field discriminators, and an output of the second synchronization signal separator A delay means for delaying the vertical synchronizing signal by a predetermined amount; and a vertical synchronizing signal when the output of the second field discriminator indicates an even field, and a delay means when indicating an odd field. The first selecting means for selecting and outputting the output of the delay means and the vertical synchronizing signal when the coincidence detector output indicates coincidence, and the timing for selecting the first selecting means output when the coincidence detector output indicates disagreement. Second selection means for outputting to a generator and the field memory output
It has a configuration of a third selection unit that outputs an image by synthesizing an image by switching between the D / A converted signal and the second video signal.

Operation The present invention has the above-described configuration to check the evenness / oddness of the field of the first video signal and the field of the second video signal, and if they are different, read vertical only when the second video signal becomes an odd field. Correct the data read timing from the memory by delaying the address reset signal by 1H.

Embodiment An image special effect device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video special effect device according to an embodiment of the present invention. In FIG. 1, the first video signal from the input terminal 14 is input to the first sync signal separator 6, the A / D converter 11 and the first field discriminator 3. Input terminal
The second video signal from 15 is input to the second sync signal separator 7 and the second field discriminator 4. The first field discriminator 3 and the second field discriminator 4 discriminate whether the fields of the first video signal and the second video signal are even fields or odd fields, respectively.
Output a discrimination signal. The vertical synchronizing signal of the output of the second synchronizing signal separator 7 is input to the delay element 8 and delayed by 1H. The coincidence detector 5 compares the outputs of the first field discriminator 3 and the second field discriminator 4 and switches 10
Switch. The switch 9 is also switched according to the output signal of the second field discriminator 4. Switch 9
Is the output of the second sync signal separator 7 when the second field discriminator 4 outputs a signal indicating an even field,
When outputting a signal indicating an odd field, the output of the delay element 8 is controlled to be selected. Switch 10 is 2
When the even / odd of two fields match, the output of the second sync signal separator 7 is selected, and when they do not match, the output of the switch 9 is selected and output to the timing signal generator 2 is controlled. It

FIG. 2 shows a concrete example of the coincidence detector 5. Input terminals 39, 40
A vertical and horizontal address reset signal for writing is input to each. Similarly, input terminals 41, 42
A vertical and horizontal address reset signal for reading is input to each. Therefore, the output signals of the D-type flip-flops (hereinafter, D-FF) 31 and 32 are output when the writing and reading addresses in the horizontal and vertical directions are both reset, that is, at the start of field reading and writing. The first and second field discriminator outputs are input to the input terminals 37 and 38, respectively. Therefore, the even / odd discrimination signal of the field currently written is held in the D-FF33, and the even / odd match between the field currently written and the field which becomes the reference of the read timing is output to the D-FF34. ， Inconsistency appears. This signal is sent from the output terminal 43 to the switch 10 of FIG.
Is output to. The output of D-FF36 holds the even / odd discrimination signal at the start of reading the field.
It is output from the output terminal 44 to the switch 9 in FIG.

FIGS. 3 and 4 are timing charts of the signals of the respective parts (a) to (l) of the circuit of FIG. 2, and the case of even / odd field coincidence is not shown in FIG. The case is shown in FIG.

When the coincidence detector 5 detects a non-coincidence, the vertical synchronizing signal of the second video signal or the same signal delayed by 1H is alternately input to the timing signal generator 2 every other field, and only the odd fields are read out. The vertical address reset timing is delayed by 1H. This is shown in FIG. The counting of the line number of the signal B1A2 is delayed by 1H as compared with the case of FIG. 10, and the vertical relationship of the lines is maintained correctly after the 50th line.

In the above example, no consideration is given to the case where the output of D-FF33 and the output of D-FF32 change at substantially the same time. However, as shown in FIG. 6, between the XOR circuit 35 and D-FF34. By inserting the arbiter unit 45, arbitration of two outputs can be performed. In FIG. 6, the delay element 49 delays by Δt. Δt is D
It is enough if it is sufficiently longer than the setup time of -FF, and for example, there is a delay of about 20 to 30 nsec. The output of D-FF46 becomes 1 only when the data change point exists within Δt immediately before the rising edge of the clock, and the switch 48
Selects the output signal of the delay element 49. Therefore, in the D-FF34, the data setup time can be secured and malfunction can be prevented.

As described above, according to this embodiment, even when the even and odd fields of the first video signal and the second video signal are opposite, the read vertical address reset signal is delayed to correct the data read timing from the memory. can do.

As described above, according to the present invention, the coincidence detector for detecting the even / odd coincidence of the fields of the first video signal and the second video signal,
When a discrepancy is detected, the vertical synchronizing signal of the second video signal or the signal obtained by delaying the same signal by 1H is alternately input to the timing generator every other field, so that even or odd fields are reversed evenly. It is possible to obtain a video signal in which the vertical relationship between the lines of the fields and the odd fields is properly maintained. As a result, a two-screen compositing system with stable performance can be realized, and its practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram of a video special effect device in a first embodiment of the present invention, FIG. 2 is a circuit diagram of the same detector, FIG.
FIG. 4 is a timing chart of signals of respective parts of the circuit of FIG. 2, FIG. 5 is a timing chart of data read from the memory,
FIG. 6 is a circuit diagram of a detector equipped with an arbiter, FIG. 7 is a block diagram of a conventional image special effect device, and FIG. 8 is a screen when the lines of two odd and even fields are turned upside down. FIGS. 9, 9 and 10 are timing charts of data read from the memory. 1 ... Field memory, 2 ... Timing generator, 3
...... First field discriminator, 4 ...... Second field discriminator, 5 ...... Match detector, 6 ...... First sync signal separator, 7
...... Second sync signal separator, 8 ... Delay element, 9,10,13 ...
… Switch, 11 …… A / D converter, 12 …… D / A converter.

Claims (1)

[Claims] 1. A first sync signal separator for separating the horizontal and vertical sync signals of a first video signal, and a second for separating the horizontal and vertical sync signals of a second video signal.
A sync signal separator; and a field memory that A / D-converts the first video signal, writes the same in synchronization with the output of the first sync signal separator, and reads the same in synchronization with the output of the second sync signal separator. A timing generator for controlling reading / writing of data from / to the field memory, and first and second field discriminators for discriminating odd / even of the field of the first video signal and the field of the second video signal, respectively. A coincidence detector for detecting coincidence between the outputs of the first and second field discriminators, a delay means for delaying a vertical synchronization signal of the output of the second synchronization signal separator by a predetermined amount, and the second field discrimination The vertical synchronizing signal when the container output indicates an even field, and the first selecting means for selecting and outputting the output of the delay means when indicating an odd field, When the output of the coincidence detector indicates coincidence, the vertical synchronizing signal is output, and when the output of the coincidence detector indicates disagreement, second selection means for selecting the output of the first selection means and outputting to the timing generator, and the field memory output. A video special effect device comprising: a third selection means for synthesizing and outputting a screen by switching a D / A converted signal and the second video signal.